mb/amd,google: move fch_irq_routing struct definition to soc/amd
Define the fch_irq_routing struct once in a common header file instead of in every mainboard's code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I11d9000b6ed7529e4afd7f6e8a7332c390da6dab Reviewed-on: https://review.coreboot.org/c/coreboot/+/68817 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -33,11 +33,7 @@ static uint8_t fch_apic_routing[0x80];
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_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing),
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_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing),
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"PIC and APIC FCH interrupt tables must be the same size");
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"PIC and APIC FCH interrupt tables must be the same size");
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static const struct fch_irq_routing {
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static const struct fch_irq_routing bilby_fch[] = {
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uint8_t intr_index;
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uint8_t pic_irq_num;
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uint8_t apic_irq_num;
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} bilby_fch[] = {
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{ PIRQ_A, 8, 16 },
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{ PIRQ_A, 8, 16 },
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{ PIRQ_B, 10, 17 },
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{ PIRQ_B, 10, 17 },
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{ PIRQ_C, 11, 18 },
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{ PIRQ_C, 11, 18 },
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@ -34,11 +34,7 @@ _Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing),
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* 8: rtc0 <- soc/amd/common/acpi/lpc.asl
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* 8: rtc0 <- soc/amd/common/acpi/lpc.asl
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* 9: acpi <- soc/amd/common/acpi/lpc.asl
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* 9: acpi <- soc/amd/common/acpi/lpc.asl
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*/
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*/
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static const struct fch_irq_routing {
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static const struct fch_irq_routing birman_fch[] = {
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uint8_t intr_index;
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uint8_t pic_irq_num;
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uint8_t apic_irq_num;
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} birman_fch[] = {
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{ PIRQ_A, 12, PIRQ_NC },
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{ PIRQ_A, 12, PIRQ_NC },
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{ PIRQ_B, 14, PIRQ_NC },
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{ PIRQ_B, 14, PIRQ_NC },
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{ PIRQ_C, 15, PIRQ_NC },
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{ PIRQ_C, 15, PIRQ_NC },
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@ -32,11 +32,7 @@ _Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing),
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* 8: rtc0 <- soc/amd/common/acpi/lpc.asl
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* 8: rtc0 <- soc/amd/common/acpi/lpc.asl
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* 9: acpi <- soc/amd/common/acpi/lpc.asl
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* 9: acpi <- soc/amd/common/acpi/lpc.asl
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*/
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*/
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static const struct fch_irq_routing {
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static const struct fch_irq_routing chausie_fch[] = {
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uint8_t intr_index;
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uint8_t pic_irq_num;
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uint8_t apic_irq_num;
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} chausie_fch[] = {
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{ PIRQ_A, 12, PIRQ_NC },
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{ PIRQ_A, 12, PIRQ_NC },
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{ PIRQ_B, 14, PIRQ_NC },
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{ PIRQ_B, 14, PIRQ_NC },
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{ PIRQ_C, 15, PIRQ_NC },
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{ PIRQ_C, 15, PIRQ_NC },
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@ -31,11 +31,7 @@ _Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing),
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* 8: rtc0 <- soc/amd/common/acpi/lpc.asl
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* 8: rtc0 <- soc/amd/common/acpi/lpc.asl
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* 9: acpi <- soc/amd/common/acpi/lpc.asl
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* 9: acpi <- soc/amd/common/acpi/lpc.asl
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*/
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*/
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static const struct fch_irq_routing {
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static const struct fch_irq_routing majolica_fch[] = {
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uint8_t intr_index;
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uint8_t pic_irq_num;
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uint8_t apic_irq_num;
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} majolica_fch[] = {
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{ PIRQ_A, 12, PIRQ_NC },
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{ PIRQ_A, 12, PIRQ_NC },
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{ PIRQ_B, 14, PIRQ_NC },
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{ PIRQ_B, 14, PIRQ_NC },
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{ PIRQ_C, 15, PIRQ_NC },
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{ PIRQ_C, 15, PIRQ_NC },
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@ -28,11 +28,7 @@ static uint8_t fch_apic_routing[0x80];
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_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing),
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_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing),
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"PIC and APIC FCH interrupt tables must be the same size");
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"PIC and APIC FCH interrupt tables must be the same size");
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static const struct fch_irq_routing {
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static const struct fch_irq_routing mandolin_fch[] = {
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uint8_t intr_index;
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uint8_t pic_irq_num;
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uint8_t apic_irq_num;
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} mandolin_fch[] = {
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{ PIRQ_A, 8, 16 },
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{ PIRQ_A, 8, 16 },
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{ PIRQ_B, 10, 17 },
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{ PIRQ_B, 10, 17 },
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{ PIRQ_C, 11, 18 },
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{ PIRQ_C, 11, 18 },
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@ -46,11 +46,7 @@ _Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing),
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* 8: rtc0 <- soc/amd/common/acpi/lpc.asl
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* 8: rtc0 <- soc/amd/common/acpi/lpc.asl
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* 9: acpi <- soc/amd/common/acpi/lpc.asl
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* 9: acpi <- soc/amd/common/acpi/lpc.asl
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*/
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*/
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static const struct fch_irq_routing {
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static const struct fch_irq_routing guybrush_fch[] = {
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uint8_t intr_index;
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uint8_t pic_irq_num;
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uint8_t apic_irq_num;
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} guybrush_fch[] = {
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{ PIRQ_A, 12, PIRQ_NC },
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{ PIRQ_A, 12, PIRQ_NC },
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{ PIRQ_B, 14, PIRQ_NC },
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{ PIRQ_B, 14, PIRQ_NC },
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{ PIRQ_C, 15, PIRQ_NC },
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{ PIRQ_C, 15, PIRQ_NC },
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@ -33,11 +33,7 @@ _Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing),
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* 9: acpi <- soc/amd/common/acpi/lpc.asl
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* 9: acpi <- soc/amd/common/acpi/lpc.asl
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*/
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*/
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static const struct fch_irq_routing {
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static const struct fch_irq_routing skyrim_fch[] = {
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uint8_t intr_index;
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uint8_t pic_irq_num;
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uint8_t apic_irq_num;
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} skyrim_fch[] = {
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{ PIRQ_A, 12, PIRQ_NC },
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{ PIRQ_A, 12, PIRQ_NC },
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{ PIRQ_B, 14, PIRQ_NC },
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{ PIRQ_B, 14, PIRQ_NC },
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{ PIRQ_C, 15, PIRQ_NC },
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{ PIRQ_C, 15, PIRQ_NC },
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@ -56,11 +56,7 @@ _Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing),
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* 9: acpi <- soc/amd/common/acpi/lpc.asl
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* 9: acpi <- soc/amd/common/acpi/lpc.asl
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* 12: i8042 <- ec/google/chromeec/acpi/superio.asl
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* 12: i8042 <- ec/google/chromeec/acpi/superio.asl
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*/
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*/
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static const struct fch_irq_routing {
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static const struct fch_irq_routing fch_pirq[] = {
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uint8_t intr_index;
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uint8_t pic_irq_num;
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uint8_t apic_irq_num;
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} fch_pirq[] = {
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{ PIRQ_A, 6, PIRQ_NC },
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{ PIRQ_A, 6, PIRQ_NC },
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{ PIRQ_B, 13, PIRQ_NC },
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{ PIRQ_B, 13, PIRQ_NC },
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{ PIRQ_C, 14, PIRQ_NC },
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{ PIRQ_C, 14, PIRQ_NC },
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@ -11,6 +11,12 @@
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#define PCI_INTR_INDEX 0xc00
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#define PCI_INTR_INDEX 0xc00
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#define PCI_INTR_DATA 0xc01
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#define PCI_INTR_DATA 0xc01
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struct fch_irq_routing {
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uint8_t intr_index;
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uint8_t pic_irq_num;
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uint8_t apic_irq_num;
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};
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struct pirq_struct {
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struct pirq_struct {
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u8 devfn;
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u8 devfn;
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u8 PIN[4]; /* PINA/B/C/D are index 0/1/2/3 */
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u8 PIN[4]; /* PINA/B/C/D are index 0/1/2/3 */
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