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cpu/intel/haswell: Switch to POSTCAR_STAGE

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Tested on Google Peppy (Acer C720).

Change-Id: I1802547d7a5b3875689cc4e126e7c189a75defa9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26793
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
2018-06-03 12:37:54 +02:00
parent 02b13fd8cd
commit 88af0f38eb
6 changed files with 28 additions and 394 deletions
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5
src/cpu/intel/haswell/Makefile.inc
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@@ -9,17 +9,14 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
ramstage-y += monotonic_timer.c
romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
smm-y += monotonic_timer.c
ifneq ($(CONFIG_POSTCAR_STAGE),y)
cpu_incs-y += $(src)/cpu/intel/haswell/cache_as_ram.inc
else
cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
postcar-y += ../car/non-evict/exit_car.S
endif
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr