cpu/intel/haswell: Switch to POSTCAR_STAGE

Tested on Google Peppy (Acer C720).

Change-Id: I1802547d7a5b3875689cc4e126e7c189a75defa9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26793
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/intel/haswell/haswell.h

@@ -181,9 +181,6 @@ void romstage_common(const struct romstage_params *params);
  *  ...
  */
 asmlinkage void *romstage_main(unsigned long bist);
-/* romstage_after_car() is the C function called after cache-as-ram has
- * been torn down. It is responsible for loading the ramstage. */
-asmlinkage void romstage_after_car(void);
 #endif
 
 #ifdef __SMM__