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fixes for EPIA.

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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1227 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
2003-10-22 21:54:19 +00:00
parent 7f1105c431
commit 88fbae24bc
6 changed files with 24 additions and 32 deletions
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8
src/cpu/p6/earlymtrr.c
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@@ -37,7 +37,7 @@ static void early_mtrr_init(void)
const unsigned long *msr_addr;
unsigned long cr0;
print_err("Disabling cache\n");
print_err("Disabling cache\r\n");
/* Just to be sure, take all the steps to disable the cache.
* This may not be needed, but C3's may...
* Invalidate the cache */
@@ -56,7 +56,7 @@ static void early_mtrr_init(void)
/* Invalidate the cache again */
asm volatile ("invd");
print_err("Clearing mtrr\n");
print_err("Clearing mtrr\r\n");
/* Inialize all of the relevant msrs to 0 */
msr.lo = 0;
@@ -81,7 +81,7 @@ static void early_mtrr_init(void)
wrmsr(0x201, msr);
#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
print_err("Setting XIP\n");
print_err("Setting XIP\r\n");
/* enable write through caching so we can do execute in place
* on the flash rom.
*/
@@ -104,5 +104,5 @@ static void early_mtrr_init(void)
cr0 = read_cr0();
cr0 &= 0x9fffffff;
write_cr0(cr0);
print_err("Enabled the cache\n");
print_err("Enabled the cache\r\n");
}