diff --git a/.gitmodules b/.gitmodules index f4f7c4ff27..81da73c055 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,28 +1,28 @@ [submodule "3rdparty/blobs"] path = 3rdparty/blobs - url = ../blobs.git + url = https://github.com/coreboot/blobs.git update = none ignore = dirty [submodule "util/nvidia-cbootimage"] path = util/nvidia/cbootimage - url = ../nvidia-cbootimage.git + url = https://github.com/coreboot/nvidia-cbootimage.git [submodule "vboot"] path = 3rdparty/vboot - url = ../vboot.git + url = https://github.com/coreboot/vboot.git [submodule "arm-trusted-firmware"] path = 3rdparty/arm-trusted-firmware - url = ../arm-trusted-firmware.git + url = https://github.com/coreboot/arm-trusted-firmware.git [submodule "3rdparty/chromeec"] path = 3rdparty/chromeec - url = ../chrome-ec.git + url = https://github.com/coreboot/chrome-ec.git [submodule "libhwbase"] path = 3rdparty/libhwbase - url = ../libhwbase.git + url = https://github.com/coreboot/libhwbase.git [submodule "libgfxinit"] path = 3rdparty/libgfxinit - url = ../libgfxinit.git + url = https://github.com/coreboot/libgfxinit.git [submodule "3rdparty/fsp"] path = 3rdparty/fsp - url = ../fsp.git + url = https://github.com/coreboot/fsp.git update = none ignore = dirty diff --git a/src/mainboard/system76/Kconfig b/src/mainboard/system76/Kconfig new file mode 100644 index 0000000000..62034a4222 --- /dev/null +++ b/src/mainboard/system76/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_SYSTEM76 + +choice + prompt "Mainboard model" + +source "src/mainboard/system76/*/Kconfig.name" + +endchoice + +source "src/mainboard/system76/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "System76" + +endif diff --git a/src/mainboard/system76/Kconfig.name b/src/mainboard/system76/Kconfig.name new file mode 100644 index 0000000000..7155721bee --- /dev/null +++ b/src/mainboard/system76/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_SYSTEM76 + bool "System76" diff --git a/src/mainboard/system76/kbl-u/Kconfig b/src/mainboard/system76/kbl-u/Kconfig new file mode 100644 index 0000000000..5955236336 --- /dev/null +++ b/src/mainboard/system76/kbl-u/Kconfig @@ -0,0 +1,100 @@ +if BOARD_SYSTEM76_GALP2 || BOARD_SYSTEM76_GALP3 || BOARD_SYSTEM76_GALP3_B + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ADD_FSP_BINARIES + select BOARD_ROMSIZE_KB_8192 + select EC_ACPI + select FSP_USE_REPO + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES +# select HAVE_CMOS_DEFAULT + select HAVE_SMI_HANDLER + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select MAINBOARD_USES_FSP2_0 + select SERIRQ_CONTINUOUS_MODE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_KABYLAKE + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + select USE_BLOBS + +config MAINBOARD_DIR + string + default system76/kbl-u + +config VARIANT_DIR + string + default "galp2" if BOARD_SYSTEM76_GALP2 + default "galp3" if BOARD_SYSTEM76_GALP3 + default "galp3-b" if BOARD_SYSTEM76_GALP3_B + +config MAINBOARD_PART_NUMBER + string + default "galp2" if BOARD_SYSTEM76_GALP2 + default "galp3" if BOARD_SYSTEM76_GALP3 + default "galp3-b" if BOARD_SYSTEM76_GALP3_B + +config CBFS_SIZE + hex + default 0x600000 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1558 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x1303 if BOARD_SYSTEM76_GALP2 + default 0x1313 if BOARD_SYSTEM76_GALP3 + default 0x1413 if BOARD_SYSTEM76_GALP3_B + +config CONSOLE_POST + bool + default y + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config UART_FOR_CONSOLE + int + default 2 + +config MAX_CPUS + int + default 8 + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config VGA_BIOS_FILE + string + default "pci8086,5916.rom" if BOARD_SYSTEM76_GALP2 + default "pci8086,5917.rom" if BOARD_SYSTEM76_GALP3 || BOARD_SYSTEM76_GALP3_B + +config VGA_BIOS_ID + string + default "8086,5916" if BOARD_SYSTEM76_GALP2 + default "8086,5917" if BOARD_SYSTEM76_GALP3 || BOARD_SYSTEM76_GALP3_B + +config PXE_ROM_ID + string + default "10ec,8168" + +config FSP_M_XIP + bool + default y + +config POST_DEVICE + bool + default n + +endif diff --git a/src/mainboard/system76/kbl-u/Kconfig.name b/src/mainboard/system76/kbl-u/Kconfig.name new file mode 100644 index 0000000000..143ac15789 --- /dev/null +++ b/src/mainboard/system76/kbl-u/Kconfig.name @@ -0,0 +1,8 @@ +config BOARD_SYSTEM76_GALP2 + bool "galp2" + +config BOARD_SYSTEM76_GALP3 + bool "galp3" + +config BOARD_SYSTEM76_GALP3_B + bool "galp3-b" diff --git a/src/mainboard/system76/kbl-u/Makefile.inc b/src/mainboard/system76/kbl-u/Makefile.inc new file mode 100644 index 0000000000..5ffe936e09 --- /dev/null +++ b/src/mainboard/system76/kbl-u/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += pei_data.c +ramstage-y += ramstage.c pei_data.c variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/system76/kbl-u/acpi/ac.asl b/src/mainboard/system76/kbl-u/acpi/ac.asl new file mode 100644 index 0000000000..7a55e45ca3 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/ac.asl @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (AC) +{ + Name (_HID, "ACPI0003" /* Power Source Device */) // _HID: Hardware ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + + Name (ACFG, One) + + Method (_PSR, 0, NotSerialized) // _PSR: Power Source + { + Return (ACFG) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } +} diff --git a/src/mainboard/system76/kbl-u/acpi/battery.asl b/src/mainboard/system76/kbl-u/acpi/battery.asl new file mode 100644 index 0000000000..da26474d62 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/battery.asl @@ -0,0 +1,183 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (BAT0) +{ + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + Name (BFCC, Zero) + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (^^PCI0.LPCB.EC.ECOK) + { + If (^^PCI0.LPCB.EC.BAT0) + { + Return (0x1F) + } + Else + { + Return (0x0F) + } + } + Else + { + Return (0x0F) + } + } + + Name (PBIF, Package (0x0D) + { + One, + 0xFFFFFFFF, + 0xFFFFFFFF, + One, + 0x39D0, + Zero, + Zero, + 0x40, + 0x40, + "BAT", + "0001", + "LION", + "Notebook" + }) + Method (IVBI, 0, NotSerialized) + { + PBIF [One] = 0xFFFFFFFF + PBIF [0x02] = 0xFFFFFFFF + PBIF [0x04] = 0xFFFFFFFF + PBIF [0x09] = " " + PBIF [0x0A] = " " + PBIF [0x0B] = " " + PBIF [0x0C] = " " + BFCC = Zero + } + + Method (UPBI, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC.BAT0) + { + Local0 = (^^PCI0.LPCB.EC.BDC0 & 0xFFFF) + PBIF [One] = Local0 + Local0 = (^^PCI0.LPCB.EC.BFC0 & 0xFFFF) + PBIF [0x02] = Local0 + BFCC = Local0 + Local0 = (^^PCI0.LPCB.EC.BDV0 & 0xFFFF) + PBIF [0x04] = Local0 + Local0 = (^^PCI0.LPCB.EC.BCW0 & 0xFFFF) + PBIF [0x05] = Local0 + Local0 = (^^PCI0.LPCB.EC.BCL0 & 0xFFFF) + PBIF [0x06] = Local0 + PBIF [0x09] = "BAT" + PBIF [0x0A] = "0001" + PBIF [0x0B] = "LION" + PBIF [0x0C] = "Notebook" + } + Else + { + IVBI () + } + } + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + If (^^PCI0.LPCB.EC.ECOK) + { + UPBI () + } + Else + { + IVBI () + } + + Return (PBIF) /* \_SB_.BAT0.PBIF */ + } + + Name (PBST, Package (0x04) + { + Zero, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0x3D90 + }) + Method (IVBS, 0, NotSerialized) + { + PBST [Zero] = Zero + PBST [One] = 0xFFFFFFFF + PBST [0x02] = 0xFFFFFFFF + PBST [0x03] = 0x2710 + } + + Method (UPBS, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC.BAT0) + { + Local0 = Zero + Local1 = Zero + If (^^AC.ACFG) + { + If (((^^PCI0.LPCB.EC.BST0 & 0x02) == 0x02)) + { + Local0 |= 0x02 + Local1 = (^^PCI0.LPCB.EC.BPR0 & 0xFFFF) + } + } + Else + { + Local0 |= One + Local1 = (^^PCI0.LPCB.EC.BPR0 & 0xFFFF) + } + + Local7 = (Local1 & 0x8000) + If ((Local7 == 0x8000)) + { + Local1 ^= 0xFFFF + } + + Local2 = (^^PCI0.LPCB.EC.BRC0 & 0xFFFF) + Local3 = (^^PCI0.LPCB.EC.BPV0 & 0xFFFF) + PBST [Zero] = Local0 + PBST [One] = Local1 + PBST [0x02] = Local2 + PBST [0x03] = Local3 + If ((BFCC != ^^PCI0.LPCB.EC.BFC0)) + { + Notify (BAT0, 0x81) // Information Change + } + } + Else + { + IVBS () + } + } + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + If (^^PCI0.LPCB.EC.ECOK) + { + UPBS () + } + Else + { + IVBS () + } + + Return (PBST) /* \_SB_.BAT0.PBST */ + } +} diff --git a/src/mainboard/system76/kbl-u/acpi/buttons.asl b/src/mainboard/system76/kbl-u/acpi/buttons.asl new file mode 100644 index 0000000000..6be52792c1 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/buttons.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (PWRB) +{ + Name (_HID, EisaId ("PNP0C0C")) + Name (_PRW, Package () { 0x13 /* GPP_C19 */, 3 }) +} + +Device (SLPB) +{ + Name (_HID, EisaId ("PNP0C0E")) + Name (_PRW, Package () { 0x13 /* GPP_C19 */, 3 }) +} diff --git a/src/mainboard/system76/kbl-u/acpi/ec.asl b/src/mainboard/system76/kbl-u/acpi/ec.asl new file mode 100644 index 0000000000..4209ee4169 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/ec.asl @@ -0,0 +1,170 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (EC) +{ + Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID + Name (_GPE, 0x50 /* GPP_E16 */) // _GPE: General Purpose Events + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0062, // Range Minimum + 0x0062, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0066, // Range Minimum + 0x0066, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + }) + + #include "acpi/ec_ram.asl" + + Name (ECOK, Zero) + Method (_REG, 2, NotSerialized) // _REG: Region Availability + { + Store ("EC: _REG", Debug) + If (((Arg0 == 0x03) && (Arg1 == One))) + { + ECOK = Arg1 + ECOS = One + WINF = One + + ^^^^AC.ACFG = ADP + + PNOT () + } + } + + Method (_Q0A, 0, NotSerialized) // Touchpad Toggle + { + Store ("EC: Touchpad Toggle", Debug) + } + + Method (_Q0B, 0, NotSerialized) // Screen Toggle + { + Store ("EC: Screen Toggle", Debug) + } + + Method (_Q0C, 0, NotSerialized) // Mute + { + Store ("EC: Mute", Debug) + } + + Method (_Q0D, 0, NotSerialized) // Keyboard Backlight + { + Store ("EC: Keyboard Backlight", Debug) + } + + Method (_Q0E, 0, NotSerialized) // Volume Down + { + Store ("EC: Volume Down", Debug) + } + + Method (_Q0F, 0, NotSerialized) // Volume Up + { + Store ("EC: Volume Up", Debug) + } + + Method (_Q10, 0, NotSerialized) // Switch Video Mode + { + Store ("EC: Switch Video Mode", Debug) + } + + Method (_Q11, 0, NotSerialized) // Brightness Down + { + Store ("EC: Brightness Down", Debug) + ^^^^HIDD.HPEM (20) + } + + Method (_Q12, 0, NotSerialized) // Brightness Up + { + Store ("EC: Brightness Up", Debug) + ^^^^HIDD.HPEM (19) + } + + Method (_Q13, 0, NotSerialized) // Camera Toggle + { + Store ("EC: Camera Toggle", Debug) + } + + Method (_Q14, 0, NotSerialized) // Airplane Mode + { + Store ("EC: Airplane Mode", Debug) + ^^^^HIDD.HPEM (8) + } + + Method (_Q15, 0, NotSerialized) // Suspend Button + { + Store ("EC: Suspend Button", Debug) + Notify (SLPB, 0x80) + } + + Method (_Q16, 0, NotSerialized) // AC Detect + { + Store ("EC: AC Detect", Debug) + ^^^^AC.ACFG = ADP + Notify (AC, 0x80) // Status Change + Sleep (0x01F4) + If (BAT0) + { + Notify (^^^^BAT0, 0x81) // Information Change + Sleep (0x32) + Notify (^^^^BAT0, 0x80) // Status Change + Sleep (0x32) + } + } + + Method (_Q17, 0, NotSerialized) // BAT0 Update + { + Store ("EC: BAT0 Update (17)", Debug) + Notify (^^^^BAT0, 0x81) // Information Change + } + + Method (_Q19, 0, NotSerialized) // BAT0 Update + { + Store ("EC: BAT0 Update (19)", Debug) + Notify (^^^^BAT0, 0x81) // Information Change + } + + Method (_Q1B, 0, NotSerialized) // Lid Close + { + Store ("EC: Lid Close", Debug) + Notify (LID0, 0x80) + } + + Method (_Q1C, 0, NotSerialized) // Thermal Trip + { + Store ("EC: Thermal Trip", Debug) + /* TODO + Notify (\_TZ.TZ0, 0x81) // Thermal Trip Point Change + Notify (\_TZ.TZ0, 0x80) // Thermal Status Change + */ + } + + Method (_Q1D, 0, NotSerialized) // Power Button + { + Store ("EC: Power Button", Debug) + Notify (PWRB, 0x80) + } + + Method (_Q50, 0, NotSerialized) // TODO + { + Store ("EC: 50", Debug) + } +} diff --git a/src/mainboard/system76/kbl-u/acpi/ec_ram.asl b/src/mainboard/system76/kbl-u/acpi/ec_ram.asl new file mode 100644 index 0000000000..8820fd0d34 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/ec_ram.asl @@ -0,0 +1,185 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF) +Field (ERAM, ByteAcc, Lock, Preserve) +{ + NMSG, 8, + SLED, 4, + Offset (0x02), + MODE, 1, + FAN0, 1, + TME0, 1, + TME1, 1, + FAN1, 1, + , 2, + Offset (0x03), + LSTE, 1, + LSW0, 1, + LWKE, 1, + WAKF, 1, + , 2, + PWKE, 1, + MWKE, 1, + AC0, 8, + PSV, 8, + CRT, 8, + TMP, 8, + AC1, 8, + BBST, 8, + Offset (0x0B), + Offset (0x0C), + Offset (0x0D), + Offset (0x0E), + SLPT, 8, + SWEJ, 1, + SWCH, 1, + Offset (0x10), + ADP, 1, + AFLT, 1, + BAT0, 1, + BAT1, 1, + , 3, + PWOF, 1, + WFNO, 8, + BPU0, 32, + BDC0, 32, + BFC0, 32, + BTC0, 32, + BDV0, 32, + BST0, 32, + BPR0, 32, + BRC0, 32, + BPV0, 32, + BTP0, 16, + BRS0, 16, + BCW0, 32, + BCL0, 32, + BCG0, 32, + BG20, 32, + BMO0, 64, + BIF0, 64, + BSN0, 32, + BTY0, 64, + Offset (0x67), + Offset (0x68), + ECOS, 8, + LNXD, 8, + ECPS, 8, + Offset (0x6C), + BTMP, 16, + EVTN, 8, + Offset (0x72), + PRCL, 8, + PRC0, 8, + PRC1, 8, + PRCM, 8, + PRIN, 8, + PSTE, 8, + PCAD, 8, + PEWL, 8, + PWRL, 8, + PECD, 8, + PEHI, 8, + PECI, 8, + PEPL, 8, + PEPM, 8, + PWFC, 8, + PECC, 8, + PDT0, 8, + PDT1, 8, + PDT2, 8, + PDT3, 8, + PRFC, 8, + PRS0, 8, + PRS1, 8, + PRS2, 8, + PRS3, 8, + PRS4, 8, + PRCS, 8, + PEC0, 8, + PEC1, 8, + PEC2, 8, + PEC3, 8, + CMDR, 8, + CVRT, 8, + GTVR, 8, + FANT, 8, + SKNT, 8, + AMBT, 8, + MCRT, 8, + DIM0, 8, + DIM1, 8, + PMAX, 8, + PPDT, 8, + PECH, 8, + PMDT, 8, + TSD0, 8, + TSD1, 8, + TSD2, 8, + TSD3, 8, + CPUP, 16, + MCHP, 16, + SYSP, 16, + CPAP, 16, + MCAP, 16, + SYAP, 16, + CFSP, 16, + CPUE, 16, + Offset (0xC6), + Offset (0xC7), + VGAT, 8, + OEM1, 8, + OEM2, 8, + OEM3, 16, + OEM4, 8, + Offset (0xCE), + DUT1, 8, + DUT2, 8, + RPM1, 16, + RPM2, 16, + RPM4, 16, + Offset (0xD7), + DTHL, 8, + DTBP, 8, + AIRP, 8, + WINF, 8, + RINF, 8, + Offset (0xDD), + INF2, 8, + MUTE, 1, + Offset (0xE0), + RPM3, 16, + ECKS, 8, + Offset (0xE4), + , 4, + XTUF, 1, + EP12, 1, + Offset (0xE5), + INF3, 8, + Offset (0xE7), + GFOF, 8, + Offset (0xF0), + PL1T, 16, + PL2T, 16, + TAUT, 8, + Offset (0xF8), + FCMD, 8, + FDAT, 8, + FBUF, 8, + FBF1, 8, + FBF2, 8, + FBF3, 8 +} diff --git a/src/mainboard/system76/kbl-u/acpi/hid.asl b/src/mainboard/system76/kbl-u/acpi/hid.asl new file mode 100644 index 0000000000..c75fefa6a0 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/hid.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (HIDD) +{ + Name (_HID, "INT33D5") + Name (HBSY, Zero) + Name (HIDX, Zero) + Name (HRDY, Zero) + + Method (HDEM, 0, Serialized) + { + HBSY = Zero + Return (HIDX) + } + + Method (HDMM, 0, Serialized) + { + Return (Zero) + } + + Method (HDSM, 1, Serialized) + { + HRDY = Arg0 + } + + Method (HPEM, 1, Serialized) + { + HBSY = One + HIDX = Arg0 + + Notify (HIDD, 0xC0) + Local0 = Zero + While (((Local0 < 0xFA) && HBSY)) + { + Sleep (0x04) + Local0++ + } + + If ((HBSY == One)) + { + HBSY = Zero + HIDX = Zero + Return (One) + } + Else + { + Return (Zero) + } + } +} diff --git a/src/mainboard/system76/kbl-u/acpi/lid.asl b/src/mainboard/system76/kbl-u/acpi/lid.asl new file mode 100644 index 0000000000..8698048eaf --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/lid.asl @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (LID0) +{ + Name (_HID, EisaId ("PNP0C0D")) + Name (_PRW, Package () { 0x13 /* GPP_C19 */, 3 }) + + Method (_LID, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC.ECOK) + { + Return (\_SB.PCI0.LPCB.EC.LSTE) + } + Else + { + Return (One) + } + } + + Method (_PSW, 1, NotSerialized) + { + If (^^PCI0.LPCB.EC.ECOK) + { + ^^PCI0.LPCB.EC.LWKE = Arg0 + } + } +} diff --git a/src/mainboard/system76/kbl-u/acpi/mainboard.asl b/src/mainboard/system76/kbl-u/acpi/mainboard.asl new file mode 100644 index 0000000000..a25a269a68 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/mainboard.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + #include "ac.asl" + #include "battery.asl" + #include "buttons.asl" + #include "hid.asl" + #include "lid.asl" +} diff --git a/src/mainboard/system76/kbl-u/acpi/superio.asl b/src/mainboard/system76/kbl-u/acpi/superio.asl new file mode 100644 index 0000000000..9e01ed8b92 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/superio.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/system76/kbl-u/acpi_tables.c b/src/mainboard/system76/kbl-u/acpi_tables.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/system76/kbl-u/board_info.txt b/src/mainboard/system76/kbl-u/board_info.txt new file mode 100644 index 0000000000..56e98a39e3 --- /dev/null +++ b/src/mainboard/system76/kbl-u/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: System76 +Board name: kbl-u +Category: laptop +Release year: 2018 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb new file mode 100644 index 0000000000..9c3bdb5064 --- /dev/null +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -0,0 +1,251 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x000c0081" + register "gen4_dec" = "0x00040069" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "0" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "SataSpeedLimit" = "2" + register "EnableAzalia" = "1" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "1" + register "SaGv" = "3" + register "SerialIrqConfigSirqEnable" = "1" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # Root port #1 x4 (TBT) + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "4" + register "PcieRpClkSrcNumber[0]" = "4" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpHotPlug[0]" = "1" + + # Root port #5 x1 (LAN) + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkSrcNumber[4]" = "3" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + + # Root port #6 x1 (WLAN) + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "2" + register "PcieRpClkSrcNumber[5]" = "2" + register "PcieRpAdvancedErrorReporting[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + + # Root port #9 x4 (NVMe) + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "5" + register "PcieRpClkSrcNumber[8]" = "5" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + + # Configure USB2 ports + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port right + register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # 3G / LTE + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A port left + register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[9]" = "USB2_PORT_EMPTY" # NC + + # Configure USB3 ports + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port right + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C port right + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port left + + # PL2 override 44W + register "tdp_pl2_override" = "40" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 5A | 64A | 31A | 31A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(5), + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(64), + .voltage_limit = 1520, + .ac_loadline = 240, + .dc_loadline = 240, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/system76/kbl-u/dsdt.asl b/src/mainboard/system76/kbl-u/dsdt.asl new file mode 100644 index 0000000000..2c7f2ddf7d --- /dev/null +++ b/src/mainboard/system76/kbl-u/dsdt.asl @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include + + // global NVS and variables + #include + + // CPU + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + } + } + + // Chipset specific sleep states + #include + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/system76/kbl-u/gpio.h b/src/mainboard/system76/kbl-u/gpio.h new file mode 100644 index 0000000000..031719a783 --- /dev/null +++ b/src/mainboard/system76/kbl-u/gpio.h @@ -0,0 +1,366 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include +#include + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + /* PM_BATLOW# */ + _PAD_CFG_STRUCT(GPD0, 0x4000700, 0x0), + /* AC_PRESENT */ + _PAD_CFG_STRUCT(GPD1, 0x4000700, 0x0), + /* LAN_WAKEUP# */ + _PAD_CFG_STRUCT(GPD2, 0x880500, 0x0), + /* PWR_BTN# */ + _PAD_CFG_STRUCT(GPD3, 0x4000700, 0x3000), + /* SUSB#_PCH */ + _PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), + /* SUSC#_PCH */ + _PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), + /* SLP_A# */ + _PAD_CFG_STRUCT(GPD6, 0x4000700, 0x0), + /* PCH_GPD7 with pull-up */ + _PAD_CFG_STRUCT(GPD7, 0x4000301, 0x0), + /* SUSCLK */ + _PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), + /* PCH_SLP_WLAN#_R */ + _PAD_CFG_STRUCT(GPD9, 0x4000700, 0x0), + /* NC */ + PAD_CFG_NC(GPD10), + /* NC */ + PAD_CFG_NC(GPD11), + /* SB_KBCRST# */ + _PAD_CFG_STRUCT(GPP_A0, 0x44000500, 0x0), + /* LPC_AD0 */ + _PAD_CFG_STRUCT(GPP_A1, 0x44000400, 0x0), + /* LPC_AD1 */ + _PAD_CFG_STRUCT(GPP_A2, 0x44000400, 0x0), + /* LPC_AD2 */ + _PAD_CFG_STRUCT(GPP_A3, 0x44000400, 0x0), + /* LPC_AD3 */ + _PAD_CFG_STRUCT(GPP_A4, 0x44000400, 0x0), + /* LPC_FRAME# */ + _PAD_CFG_STRUCT(GPP_A5, 0x44000600, 0x0), + /* SERIRQ with pull up */ + _PAD_CFG_STRUCT(GPP_A6, 0x44000400, 0x0), + /* G_INT1 */ + _PAD_CFG_STRUCT(GPP_A7, 0x44000100, 0x0), + /* PM_CLKRUN# with pull-up */ + _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0), + /* PCLK_KBC */ + _PAD_CFG_STRUCT(GPP_A9, 0x44000600, 0x0), + /* PCLK_TPM */ + _PAD_CFG_STRUCT(GPP_A10, 0x44000600, 0x1000), + /* LAN_WAKEUP# */ + _PAD_CFG_STRUCT(GPP_A11, 0x44000200, 0x0), + /* PCH_GPP_A12 with pull-up */ + _PAD_CFG_STRUCT(GPP_A12, 0x44000200, 0x0), + /* SUSWARN# with tie to SUS_PWR_ACK */ + _PAD_CFG_STRUCT(GPP_A13, 0x44000200, 0x0), + /* S4_STATE# */ + _PAD_CFG_STRUCT(GPP_A14, 0x44000600, 0x0), + /* SUS_PWR_ACK with tie to SUSWARN# */ + _PAD_CFG_STRUCT(GPP_A15, 0x44000500, 0x0), + /* NC */ + PAD_CFG_NC(GPP_A16), + /* NC */ + PAD_CFG_NC(GPP_A17), + /* TBTA_ACE_GPIO3 */ + _PAD_CFG_STRUCT(GPP_A18, 0x44000201, 0x0), + /* SATA_PWR_EN */ + _PAD_CFG_STRUCT(GPP_A19, 0x44000601, 0x0), + /* TBTA_ACE_GPIO0 */ + _PAD_CFG_STRUCT(GPP_A20, 0x44000200, 0x0), + /* TBT_FRC_PW tied to PCH_GPP_E0 */ + _PAD_CFG_STRUCT(GPP_A21, 0x84000200, 0x1000), + /* PS8338B_SW */ + _PAD_CFG_STRUCT(GPP_A22, 0x4000201, 0x0), + /* PS8338B_PCH */ + _PAD_CFG_STRUCT(GPP_A23, 0x4000200, 0x0), + /* CORE_VID0 with pull-up */ + _PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), + /* CORE_VID1 with pull-up */ + _PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), + /* VRALERT# */ + _PAD_CFG_STRUCT(GPP_B2, 0x44000200, 0x0), + /* NC */ + PAD_CFG_NC(GPP_B3), + /* NC */ + PAD_CFG_NC(GPP_B4), + /* NC */ + PAD_CFG_NC(GPP_B5), + /* NC */ + PAD_CFG_NC(GPP_B6), + /* WLAN_CLKREQ# */ + _PAD_CFG_STRUCT(GPP_B7, 0x44000700, 0x0), + /* LAN_CLKREQ# */ + _PAD_CFG_STRUCT(GPP_B8, 0x44000700, 0x0), + /* TBT_CLKREQ# */ + _PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), + /* SSD_CLKREQ# */ + _PAD_CFG_STRUCT(GPP_B10, 0x44000700, 0x0), + /* NC */ + PAD_CFG_NC(GPP_B11), + /* NC */ + PAD_CFG_NC(GPP_B12), + /* PLT_RST# with pull-down */ + _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), + /* PCH_SPKR */ + _PAD_CFG_STRUCT(GPP_B14, 0x44000600, 0x1000), + /* NC */ + PAD_CFG_NC(GPP_B15), + /* T16 */ + _PAD_CFG_STRUCT(GPP_B16, 0x44000200, 0x0), + /* T35 */ + _PAD_CFG_STRUCT(GPP_B17, 0x44000200, 0x0), + /* PCH_GPP_B18 with pull-down - strap for disabling no reboot mode */ + _PAD_CFG_STRUCT(GPP_B18, 0x44000600, 0x3000), + /* NC */ + PAD_CFG_NC(GPP_B19), + /* NC */ + PAD_CFG_NC(GPP_B20), + /* NC */ + PAD_CFG_NC(GPP_B21), + /* PCH_GPP_B22 with pull-down - strap for BIOS on SPI on n130wu */ + _PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), + /* NC */ + PAD_CFG_NC(GPP_B23), + /* SMB_CLK */ + _PAD_CFG_STRUCT(GPP_C0, 0x44000700, 0x0), + /* SMB_DATA */ + _PAD_CFG_STRUCT(GPP_C1, 0x44000700, 0x1000), + /* NC */ + _PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), + /* NC */ + PAD_CFG_NC(GPP_C3), + /* NC */ + PAD_CFG_NC(GPP_C4), + /* NC */ + PAD_CFG_NC(GPP_C5), + /* NC */ + PAD_CFG_NC(GPP_C6), + /* NC */ + PAD_CFG_NC(GPP_C7), + /* NC */ + PAD_CFG_NC(GPP_C8), + /* NC */ + PAD_CFG_NC(GPP_C9), + /* NC */ + PAD_CFG_NC(GPP_C10), + /* NC */ + PAD_CFG_NC(GPP_C11), + /* TBTA_ACE_GPIO2 */ + _PAD_CFG_STRUCT(GPP_C12, 0x44000700, 0x0), + /* TBCIO_PLUG_EVENT tied to PCH_GPP_B17 */ + _PAD_CFG_STRUCT(GPP_C13, 0x82880100, 0x0), + /* TBTA_MRESET */ + _PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), + /* TBTA_ACE_GPIO7 */ + _PAD_CFG_STRUCT(GPP_C15, 0x44000700, 0x0), + /* T_SDA */ + _PAD_CFG_STRUCT(GPP_C16, 0x44000200, 0x0), + /* T_SCL */ + _PAD_CFG_STRUCT(GPP_C17, 0x44000200, 0x0), + /* NC */ + PAD_CFG_NC(GPP_C18), + /* SWI# */ + _PAD_CFG_STRUCT(GPP_C19, 0x40880100, 0x0), + /* UART2_RXD */ + _PAD_CFG_STRUCT(GPP_C20, 0x44000700, 0x0), + /* UART2_TXD */ + _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), + /* UART2_RTS_N */ + _PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), + /* UART2_CTS_N */ + _PAD_CFG_STRUCT(GPP_C23, 0x44000700, 0x0), + /* NC */ + PAD_CFG_NC(GPP_D0), + /* NC */ + PAD_CFG_NC(GPP_D1), + /* NC */ + PAD_CFG_NC(GPP_D2), + /* NC */ + PAD_CFG_NC(GPP_D3), + /* NC */ + PAD_CFG_NC(GPP_D4), + /* NC */ + PAD_CFG_NC(GPP_D5), + /* NC */ + PAD_CFG_NC(GPP_D6), + /* NC */ + PAD_CFG_NC(GPP_D7), + /* SB_BLON */ + _PAD_CFG_STRUCT(GPP_D8, 0x44000201, 0x0), + /* T_INT */ + _PAD_CFG_STRUCT(GPP_D9, 0x44000200, 0x0), + /* EDP_DET */ + _PAD_CFG_STRUCT(GPP_D10, 0x44000200, 0x0), + /* NC */ + PAD_CFG_NC(GPP_D11), + /* NC */ + PAD_CFG_NC(GPP_D12), + /* NC */ + PAD_CFG_NC(GPP_D13), + /* NC */ + PAD_CFG_NC(GPP_D14), + /* NC */ + PAD_CFG_NC(GPP_D15), + /* NC */ + PAD_CFG_NC(GPP_D16), + /* NC */ + PAD_CFG_NC(GPP_D17), + /* NC */ + PAD_CFG_NC(GPP_D18), + /* NC */ + PAD_CFG_NC(GPP_D19), + /* NC */ + PAD_CFG_NC(GPP_D20), + /* TPM_DET# */ + _PAD_CFG_STRUCT(GPP_D21, 0x44000100, 0x0), + /* NC */ + PAD_CFG_NC(GPP_D22), + /* NC */ + PAD_CFG_NC(GPP_D23), + /* PCH_GPP_E0 tied to TBT_FRC_PW */ + _PAD_CFG_STRUCT(GPP_E0, 0x42100100, 0x1000), + /* SATA_ODD_PRSNT# */ + _PAD_CFG_STRUCT(GPP_E1, 0x44000700, 0x0), + /* SATAGP2 */ + _PAD_CFG_STRUCT(GPP_E2, 0x44000500, 0x0), + /* NC */ + PAD_CFG_NC(GPP_E3), + /* NC */ + PAD_CFG_NC(GPP_E4), + /* NC */ + PAD_CFG_NC(GPP_E5), + /* DEVSLP2 */ + _PAD_CFG_STRUCT(GPP_E6, 0x44000600, 0x0), + /* NC */ + PAD_CFG_NC(GPP_E7), + /* PCH_SATA_LED# */ + _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), + /* NC */ + PAD_CFG_NC(GPP_E9), + /* NC */ + PAD_CFG_NC(GPP_E10), + /* NC */ + PAD_CFG_NC(GPP_E11), + /* NC */ + PAD_CFG_NC(GPP_E12), + /* MUX_HPD */ + _PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), + /* HDMI_HPD */ + _PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), + /* SMI# */ + _PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0), + /* SCI# */ + _PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0), + /* EDP_HPD */ + _PAD_CFG_STRUCT(GPP_E17, 0x44000700, 0x0), + /* MDP_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x0), + /* MDP_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), + /* HDMI_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_E20, 0x44000700, 0x0), + /* HDMI_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_E21, 0x44000700, 0x1000), + /* NC */ + PAD_CFG_NC(GPP_E22), + /* NC */ + PAD_CFG_NC(GPP_E23), + /* NC */ + PAD_CFG_NC(GPP_F0), + /* NC */ + PAD_CFG_NC(GPP_F1), + /* NC */ + PAD_CFG_NC(GPP_F2), + /* NC */ + PAD_CFG_NC(GPP_F3), + /* Pull-up */ + _PAD_CFG_STRUCT(GPP_F4, 0x44000700, 0x2000000), + /* Pull-up */ + _PAD_CFG_STRUCT(GPP_F5, 0x44000700, 0x2000000), + /* Pull-up */ + _PAD_CFG_STRUCT(GPP_F6, 0x44000700, 0x2000000), + /* Pull-up */ + _PAD_CFG_STRUCT(GPP_F7, 0x44000700, 0x2000000), + /* Pull-up */ + _PAD_CFG_STRUCT(GPP_F8, 0x44000700, 0x2000000), + /* Pull-up */ + _PAD_CFG_STRUCT(GPP_F9, 0x44000700, 0x2000000), + /* NC */ + PAD_CFG_NC(GPP_F10), + /* NC */ + PAD_CFG_NC(GPP_F11), + /* NC */ + PAD_CFG_NC(GPP_F12), + /* NC */ + PAD_CFG_NC(GPP_F13), + /* NC */ + PAD_CFG_NC(GPP_F14), + /* NC */ + PAD_CFG_NC(GPP_F15), + /* NC */ + PAD_CFG_NC(GPP_F16), + /* NC */ + PAD_CFG_NC(GPP_F17), + /* NC */ + PAD_CFG_NC(GPP_F18), + /* NC */ + PAD_CFG_NC(GPP_F19), + /* NC */ + PAD_CFG_NC(GPP_F20), + /* NC */ + PAD_CFG_NC(GPP_F21), + /* NC */ + PAD_CFG_NC(GPP_F22), + /* LIGHT_KB_DET# */ + _PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0), + /* NC */ + PAD_CFG_NC(GPP_G0), + /* TBT_Detect */ + _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x0), + /* NC */ + PAD_CFG_NC(GPP_G2), + /* ASM1543_I_SEL0 */ + _PAD_CFG_STRUCT(GPP_G3, 0x44000200, 0x0), + /* ASM1543_I_SEL1 */ + _PAD_CFG_STRUCT(GPP_G4, 0x44000200, 0x0), + /* NC */ + PAD_CFG_NC(GPP_G5), + /* NC */ + PAD_CFG_NC(GPP_G6), + /* NC */ + PAD_CFG_NC(GPP_G7), +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + /* UART2_RXD */ + _PAD_CFG_STRUCT(GPP_C20, 0x44000700, 0x0), + /* UART2_TXD */ + _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), +}; + +#endif + +#endif diff --git a/src/mainboard/system76/kbl-u/pei_data.c b/src/mainboard/system76/kbl-u/pei_data.c new file mode 100644 index 0000000000..0840def0fc --- /dev/null +++ b/src/mainboard/system76/kbl-u/pei_data.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include "pei_data.h" + +void mainboard_fill_dq_map_data(void *dq_map_ptr) { + /* DQ byte map */ + const u8 dq_map[2][12] = { + {0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00}, + {0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00} + }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data(void *dqs_map_ptr) { + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + {0, 1, 3, 2, 4, 5, 6, 7}, + {1, 0, 4, 5, 2, 3, 6, 7} + }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) { + /* Rcomp resistor */ + const u16 RcompResistor[3] = {121, 81, 100}; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) { + /* Rcomp target */ + const u16 RcompTarget[5] = {100, 40, 20, 20, 26}; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) { + mainboard_fill_dq_map_data(&pei_data->dq_map); + mainboard_fill_dqs_map_data(&pei_data->dqs_map); + mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); + mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); +} diff --git a/src/mainboard/system76/kbl-u/pei_data.h b/src/mainboard/system76/kbl-u/pei_data.h new file mode 100644 index 0000000000..9ad002319e --- /dev/null +++ b/src/mainboard/system76/kbl-u/pei_data.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MAINBOARD_PEI_DATA_H_ +#define _MAINBOARD_PEI_DATA_H_ + +void mainboard_fill_dq_map_data(void *dq_map_ptr); +void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); + +#endif diff --git a/src/mainboard/system76/kbl-u/ramstage.c b/src/mainboard/system76/kbl-u/ramstage.c new file mode 100644 index 0000000000..689331d6cf --- /dev/null +++ b/src/mainboard/system76/kbl-u/ramstage.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) { + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +static void mainboard_enable(struct device *dev) { + pc_keyboard_init(NO_AUX_DEVICE); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/system76/kbl-u/romstage.c b/src/mainboard/system76/kbl-u/romstage.c new file mode 100644 index 0000000000..1537f96a2a --- /dev/null +++ b/src/mainboard/system76/kbl-u/romstage.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include "pei_data.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) { + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = {0x50, 0x52}, + }; + + mem_cfg = &mupd->FspmConfig; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + assert(blk.spd_array[0][0] != 0); + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; +} diff --git a/src/mainboard/system76/kbl-u/variants/galp2/hda_verb.c b/src/mainboard/system76/kbl-u/variants/galp2/hda_verb.c new file mode 100644 index 0000000000..23ce3e9f0e --- /dev/null +++ b/src/mainboard/system76/kbl-u/variants/galp2/hda_verb.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC269VC */ + 0x10ec0269, /* Vendor ID */ + 0x15581303, /* Subsystem ID */ + 11, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15581303), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x14, 0x90170120), + AZALIA_PIN_CFG(0, 0x15, 0x02211010), + AZALIA_PIN_CFG(0, 0x17, 0x40000000), + AZALIA_PIN_CFG(0, 0x18, 0x02a11030), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40f4a205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + /* Intel, KabylakeHDMI */ + 0x8086280b, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c b/src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c new file mode 100644 index 0000000000..f346acd917 --- /dev/null +++ b/src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC269VC */ + 0x10ec0269, /* Vendor ID */ + 0x15581414, /* Subsystem ID */ + 11, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15581414), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x14, 0x90170120), + AZALIA_PIN_CFG(0, 0x15, 0x02211010), + AZALIA_PIN_CFG(0, 0x17, 0x40000000), + AZALIA_PIN_CFG(0, 0x18, 0x02a11030), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40f4a205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + /* Intel, KabylakeHDMI */ + 0x8086280b, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/src/mainboard/system76/kbl-u/variants/galp3/hda_verb.c b/src/mainboard/system76/kbl-u/variants/galp3/hda_verb.c new file mode 100644 index 0000000000..70a90de7fd --- /dev/null +++ b/src/mainboard/system76/kbl-u/variants/galp3/hda_verb.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC269VC */ + 0x10ec0269, /* Vendor ID */ + 0x15581313, /* Subsystem ID */ + 11, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15581313), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x14, 0x90170120), + AZALIA_PIN_CFG(0, 0x15, 0x02211010), + AZALIA_PIN_CFG(0, 0x17, 0x40000000), + AZALIA_PIN_CFG(0, 0x18, 0x02a11030), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40f4a205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + /* Intel, KabylakeHDMI */ + 0x8086280b, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/src/mainboard/system76/whl-u/Kconfig b/src/mainboard/system76/whl-u/Kconfig new file mode 100644 index 0000000000..a282887b4e --- /dev/null +++ b/src/mainboard/system76/whl-u/Kconfig @@ -0,0 +1,102 @@ +if BOARD_SYSTEM76_GALP3_C || BOARD_SYSTEM76_DARP5 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ADD_FSP_BINARIES + select BOARD_ROMSIZE_KB_16384 + select EC_ACPI + select EXCLUDE_EMMC_INTERFACE + select FSP_USE_REPO + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES +# select HAVE_CMOS_DEFAULT + select HAVE_SMI_HANDLER + select INTEL_GMA_HAVE_VBT +# select MAINBOARD_HAS_SPI_TPM_CR50 +# select MAINBOARD_HAS_TPM2 + select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_WHISKEYLAKE + select SYSTEM_TYPE_LAPTOP + select USE_BLOBS + +config MAINBOARD_DIR + string + default system76/whl-u + +config VARIANT_DIR + string + default "galp3-c" if BOARD_SYSTEM76_GALP3_C + default "darp5" if BOARD_SYSTEM76_DARP5 + +config MAINBOARD_PART_NUMBER + string + default "galp3-c" if BOARD_SYSTEM76_GALP3_C + default "darp5" if BOARD_SYSTEM76_DARP5 + +config CBFS_SIZE + hex + default 0xA00000 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1558 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x1323 if BOARD_SYSTEM76_GALP3_C + default 0x1325 if BOARD_SYSTEM76_DARP5 + +config CONSOLE_POST + bool + default y + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config UART_FOR_CONSOLE + int + default 2 + +config MAX_CPUS + int + default 8 + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config VGA_BIOS_FILE + string + default "pci8086,3ea0.rom" + +config VGA_BIOS_ID + string + default "8086,3ea0" + +config PXE_ROM_ID + string + default "10ec,8168" + +config FSP_M_XIP + bool + default y + +config POST_DEVICE + bool + default n + +#config DRIVER_TPM_SPI_BUS +# hex +# default 0x0 + +#config DRIVER_TPM_SPI_CHIP +# int +# default 2 + +endif diff --git a/src/mainboard/system76/whl-u/Kconfig.name b/src/mainboard/system76/whl-u/Kconfig.name new file mode 100644 index 0000000000..6379e79abb --- /dev/null +++ b/src/mainboard/system76/whl-u/Kconfig.name @@ -0,0 +1,5 @@ +config BOARD_SYSTEM76_GALP3_C + bool "galp3-c" + +config BOARD_SYSTEM76_DARP5 + bool "darp5" diff --git a/src/mainboard/system76/whl-u/Makefile.inc b/src/mainboard/system76/whl-u/Makefile.inc new file mode 100644 index 0000000000..e9e47a7ff0 --- /dev/null +++ b/src/mainboard/system76/whl-u/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += ramstage.c variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/system76/whl-u/acpi/ac.asl b/src/mainboard/system76/whl-u/acpi/ac.asl new file mode 100644 index 0000000000..7a55e45ca3 --- /dev/null +++ b/src/mainboard/system76/whl-u/acpi/ac.asl @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (AC) +{ + Name (_HID, "ACPI0003" /* Power Source Device */) // _HID: Hardware ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + + Name (ACFG, One) + + Method (_PSR, 0, NotSerialized) // _PSR: Power Source + { + Return (ACFG) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } +} diff --git a/src/mainboard/system76/whl-u/acpi/battery.asl b/src/mainboard/system76/whl-u/acpi/battery.asl new file mode 100644 index 0000000000..da26474d62 --- /dev/null +++ b/src/mainboard/system76/whl-u/acpi/battery.asl @@ -0,0 +1,183 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (BAT0) +{ + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + Name (BFCC, Zero) + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (^^PCI0.LPCB.EC.ECOK) + { + If (^^PCI0.LPCB.EC.BAT0) + { + Return (0x1F) + } + Else + { + Return (0x0F) + } + } + Else + { + Return (0x0F) + } + } + + Name (PBIF, Package (0x0D) + { + One, + 0xFFFFFFFF, + 0xFFFFFFFF, + One, + 0x39D0, + Zero, + Zero, + 0x40, + 0x40, + "BAT", + "0001", + "LION", + "Notebook" + }) + Method (IVBI, 0, NotSerialized) + { + PBIF [One] = 0xFFFFFFFF + PBIF [0x02] = 0xFFFFFFFF + PBIF [0x04] = 0xFFFFFFFF + PBIF [0x09] = " " + PBIF [0x0A] = " " + PBIF [0x0B] = " " + PBIF [0x0C] = " " + BFCC = Zero + } + + Method (UPBI, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC.BAT0) + { + Local0 = (^^PCI0.LPCB.EC.BDC0 & 0xFFFF) + PBIF [One] = Local0 + Local0 = (^^PCI0.LPCB.EC.BFC0 & 0xFFFF) + PBIF [0x02] = Local0 + BFCC = Local0 + Local0 = (^^PCI0.LPCB.EC.BDV0 & 0xFFFF) + PBIF [0x04] = Local0 + Local0 = (^^PCI0.LPCB.EC.BCW0 & 0xFFFF) + PBIF [0x05] = Local0 + Local0 = (^^PCI0.LPCB.EC.BCL0 & 0xFFFF) + PBIF [0x06] = Local0 + PBIF [0x09] = "BAT" + PBIF [0x0A] = "0001" + PBIF [0x0B] = "LION" + PBIF [0x0C] = "Notebook" + } + Else + { + IVBI () + } + } + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + If (^^PCI0.LPCB.EC.ECOK) + { + UPBI () + } + Else + { + IVBI () + } + + Return (PBIF) /* \_SB_.BAT0.PBIF */ + } + + Name (PBST, Package (0x04) + { + Zero, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0x3D90 + }) + Method (IVBS, 0, NotSerialized) + { + PBST [Zero] = Zero + PBST [One] = 0xFFFFFFFF + PBST [0x02] = 0xFFFFFFFF + PBST [0x03] = 0x2710 + } + + Method (UPBS, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC.BAT0) + { + Local0 = Zero + Local1 = Zero + If (^^AC.ACFG) + { + If (((^^PCI0.LPCB.EC.BST0 & 0x02) == 0x02)) + { + Local0 |= 0x02 + Local1 = (^^PCI0.LPCB.EC.BPR0 & 0xFFFF) + } + } + Else + { + Local0 |= One + Local1 = (^^PCI0.LPCB.EC.BPR0 & 0xFFFF) + } + + Local7 = (Local1 & 0x8000) + If ((Local7 == 0x8000)) + { + Local1 ^= 0xFFFF + } + + Local2 = (^^PCI0.LPCB.EC.BRC0 & 0xFFFF) + Local3 = (^^PCI0.LPCB.EC.BPV0 & 0xFFFF) + PBST [Zero] = Local0 + PBST [One] = Local1 + PBST [0x02] = Local2 + PBST [0x03] = Local3 + If ((BFCC != ^^PCI0.LPCB.EC.BFC0)) + { + Notify (BAT0, 0x81) // Information Change + } + } + Else + { + IVBS () + } + } + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + If (^^PCI0.LPCB.EC.ECOK) + { + UPBS () + } + Else + { + IVBS () + } + + Return (PBST) /* \_SB_.BAT0.PBST */ + } +} diff --git a/src/mainboard/system76/whl-u/acpi/buttons.asl b/src/mainboard/system76/whl-u/acpi/buttons.asl new file mode 100644 index 0000000000..52331598e2 --- /dev/null +++ b/src/mainboard/system76/whl-u/acpi/buttons.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (PWRB) +{ + Name (_HID, EisaId ("PNP0C0C")) + Name (_PRW, Package () { 0x29 /* GPP_D9 */, 3 }) +} + +Device (SLPB) +{ + Name (_HID, EisaId ("PNP0C0E")) + Name (_PRW, Package () { 0x29 /* GPP_D9 */, 3 }) +} diff --git a/src/mainboard/system76/whl-u/acpi/ec.asl b/src/mainboard/system76/whl-u/acpi/ec.asl new file mode 100644 index 0000000000..4209ee4169 --- /dev/null +++ b/src/mainboard/system76/whl-u/acpi/ec.asl @@ -0,0 +1,170 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (EC) +{ + Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID + Name (_GPE, 0x50 /* GPP_E16 */) // _GPE: General Purpose Events + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0062, // Range Minimum + 0x0062, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0066, // Range Minimum + 0x0066, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + }) + + #include "acpi/ec_ram.asl" + + Name (ECOK, Zero) + Method (_REG, 2, NotSerialized) // _REG: Region Availability + { + Store ("EC: _REG", Debug) + If (((Arg0 == 0x03) && (Arg1 == One))) + { + ECOK = Arg1 + ECOS = One + WINF = One + + ^^^^AC.ACFG = ADP + + PNOT () + } + } + + Method (_Q0A, 0, NotSerialized) // Touchpad Toggle + { + Store ("EC: Touchpad Toggle", Debug) + } + + Method (_Q0B, 0, NotSerialized) // Screen Toggle + { + Store ("EC: Screen Toggle", Debug) + } + + Method (_Q0C, 0, NotSerialized) // Mute + { + Store ("EC: Mute", Debug) + } + + Method (_Q0D, 0, NotSerialized) // Keyboard Backlight + { + Store ("EC: Keyboard Backlight", Debug) + } + + Method (_Q0E, 0, NotSerialized) // Volume Down + { + Store ("EC: Volume Down", Debug) + } + + Method (_Q0F, 0, NotSerialized) // Volume Up + { + Store ("EC: Volume Up", Debug) + } + + Method (_Q10, 0, NotSerialized) // Switch Video Mode + { + Store ("EC: Switch Video Mode", Debug) + } + + Method (_Q11, 0, NotSerialized) // Brightness Down + { + Store ("EC: Brightness Down", Debug) + ^^^^HIDD.HPEM (20) + } + + Method (_Q12, 0, NotSerialized) // Brightness Up + { + Store ("EC: Brightness Up", Debug) + ^^^^HIDD.HPEM (19) + } + + Method (_Q13, 0, NotSerialized) // Camera Toggle + { + Store ("EC: Camera Toggle", Debug) + } + + Method (_Q14, 0, NotSerialized) // Airplane Mode + { + Store ("EC: Airplane Mode", Debug) + ^^^^HIDD.HPEM (8) + } + + Method (_Q15, 0, NotSerialized) // Suspend Button + { + Store ("EC: Suspend Button", Debug) + Notify (SLPB, 0x80) + } + + Method (_Q16, 0, NotSerialized) // AC Detect + { + Store ("EC: AC Detect", Debug) + ^^^^AC.ACFG = ADP + Notify (AC, 0x80) // Status Change + Sleep (0x01F4) + If (BAT0) + { + Notify (^^^^BAT0, 0x81) // Information Change + Sleep (0x32) + Notify (^^^^BAT0, 0x80) // Status Change + Sleep (0x32) + } + } + + Method (_Q17, 0, NotSerialized) // BAT0 Update + { + Store ("EC: BAT0 Update (17)", Debug) + Notify (^^^^BAT0, 0x81) // Information Change + } + + Method (_Q19, 0, NotSerialized) // BAT0 Update + { + Store ("EC: BAT0 Update (19)", Debug) + Notify (^^^^BAT0, 0x81) // Information Change + } + + Method (_Q1B, 0, NotSerialized) // Lid Close + { + Store ("EC: Lid Close", Debug) + Notify (LID0, 0x80) + } + + Method (_Q1C, 0, NotSerialized) // Thermal Trip + { + Store ("EC: Thermal Trip", Debug) + /* TODO + Notify (\_TZ.TZ0, 0x81) // Thermal Trip Point Change + Notify (\_TZ.TZ0, 0x80) // Thermal Status Change + */ + } + + Method (_Q1D, 0, NotSerialized) // Power Button + { + Store ("EC: Power Button", Debug) + Notify (PWRB, 0x80) + } + + Method (_Q50, 0, NotSerialized) // TODO + { + Store ("EC: 50", Debug) + } +} diff --git a/src/mainboard/system76/whl-u/acpi/ec_ram.asl b/src/mainboard/system76/whl-u/acpi/ec_ram.asl new file mode 100644 index 0000000000..9502f5f057 --- /dev/null +++ b/src/mainboard/system76/whl-u/acpi/ec_ram.asl @@ -0,0 +1,188 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF) +Field (ERAM, ByteAcc, Lock, Preserve) +{ + NMSG, 8, + SLED, 4, + Offset (0x02), + MODE, 1, + FAN0, 1, + TME0, 1, + TME1, 1, + FAN1, 1, + , 2, + Offset (0x03), + LSTE, 1, + LSW0, 1, + LWKE, 1, + WAKF, 1, + , 2, + PWKE, 1, + MWKE, 1, + AC0, 8, + PSV, 8, + CRT, 8, + TMP, 8, + AC1, 8, + BBST, 8, + Offset (0x0B), + Offset (0x0C), + Offset (0x0D), + Offset (0x0E), + SLPT, 8, + SWEJ, 1, + SWCH, 1, + Offset (0x10), + ADP, 1, + AFLT, 1, + BAT0, 1, + BAT1, 1, + , 3, + PWOF, 1, + WFNO, 8, + BPU0, 32, + BDC0, 32, + BFC0, 32, + BTC0, 32, + BDV0, 32, + BST0, 32, + BPR0, 32, + BRC0, 32, + BPV0, 32, + BTP0, 16, + BRS0, 16, + BCW0, 32, + BCL0, 32, + BCG0, 32, + BG20, 32, + BMO0, 64, + BIF0, 64, + BSN0, 32, + BTY0, 64, + Offset (0x67), + Offset (0x68), + ECOS, 8, + LNXD, 8, + ECPS, 8, + Offset (0x6C), + BTMP, 16, + EVTN, 8, + Offset (0x72), + PRCL, 8, + PRC0, 8, + PRC1, 8, + PRCM, 8, + PRIN, 8, + PSTE, 8, + PCAD, 8, + PEWL, 8, + PWRL, 8, + PECD, 8, + PEHI, 8, + PECI, 8, + PEPL, 8, + PEPM, 8, + PWFC, 8, + PECC, 8, + PDT0, 8, + PDT1, 8, + PDT2, 8, + PDT3, 8, + PRFC, 8, + PRS0, 8, + PRS1, 8, + PRS2, 8, + PRS3, 8, + PRS4, 8, + PRCS, 8, + PEC0, 8, + PEC1, 8, + PEC2, 8, + PEC3, 8, + CMDR, 8, + CVRT, 8, + GTVR, 8, + FANT, 8, + SKNT, 8, + AMBT, 8, + MCRT, 8, + DIM0, 8, + DIM1, 8, + PMAX, 8, + PPDT, 8, + PECH, 8, + PMDT, 8, + TSD0, 8, + TSD1, 8, + TSD2, 8, + TSD3, 8, + CPUP, 16, + MCHP, 16, + SYSP, 16, + CPAP, 16, + MCAP, 16, + SYAP, 16, + CFSP, 16, + CPUE, 16, + Offset (0xC6), + Offset (0xC7), + VGAT, 8, + OEM1, 8, + OEM2, 8, + OEM3, 16, + OEM4, 8, + Offset (0xCE), + DUT1, 8, + DUT2, 8, + RPM1, 16, + RPM2, 16, + RPM4, 16, + Offset (0xD7), + DTHL, 8, + DTBP, 8, + AIRP, 8, + WINF, 8, + RINF, 8, + Offset (0xDD), + INF2, 8, + MUTE, 1, + Offset (0xE0), + RPM3, 16, + ECKS, 8, + Offset (0xE4), + , 4, + XTUF, 1, + EP12, 1, + Offset (0xE5), + INF3, 8, + Offset (0xE7), + GFOF, 8, + Offset (0xE9), + KPCR, 1, + Offset (0xEA), + Offset (0xF0), + PL1T, 16, + PL2T, 16, + TAUT, 8, + Offset (0xF8), + FCMD, 8, + FDAT, 8, + FBUF, 8, + FBF1, 8, + FBF2, 8, + FBF3, 8 +} diff --git a/src/mainboard/system76/whl-u/acpi/hid.asl b/src/mainboard/system76/whl-u/acpi/hid.asl new file mode 100644 index 0000000000..c75fefa6a0 --- /dev/null +++ b/src/mainboard/system76/whl-u/acpi/hid.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (HIDD) +{ + Name (_HID, "INT33D5") + Name (HBSY, Zero) + Name (HIDX, Zero) + Name (HRDY, Zero) + + Method (HDEM, 0, Serialized) + { + HBSY = Zero + Return (HIDX) + } + + Method (HDMM, 0, Serialized) + { + Return (Zero) + } + + Method (HDSM, 1, Serialized) + { + HRDY = Arg0 + } + + Method (HPEM, 1, Serialized) + { + HBSY = One + HIDX = Arg0 + + Notify (HIDD, 0xC0) + Local0 = Zero + While (((Local0 < 0xFA) && HBSY)) + { + Sleep (0x04) + Local0++ + } + + If ((HBSY == One)) + { + HBSY = Zero + HIDX = Zero + Return (One) + } + Else + { + Return (Zero) + } + } +} diff --git a/src/mainboard/system76/whl-u/acpi/lid.asl b/src/mainboard/system76/whl-u/acpi/lid.asl new file mode 100644 index 0000000000..9ffdd18314 --- /dev/null +++ b/src/mainboard/system76/whl-u/acpi/lid.asl @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (LID0) +{ + Name (_HID, EisaId ("PNP0C0D")) + Name (_PRW, Package () { 0x29 /* GPP_D9 */, 3 }) + + Method (_LID, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC.ECOK) + { + Return (\_SB.PCI0.LPCB.EC.LSTE) + } + Else + { + Return (One) + } + } + + Method (_PSW, 1, NotSerialized) + { + If (^^PCI0.LPCB.EC.ECOK) + { + ^^PCI0.LPCB.EC.LWKE = Arg0 + } + } +} diff --git a/src/mainboard/system76/whl-u/acpi/mainboard.asl b/src/mainboard/system76/whl-u/acpi/mainboard.asl new file mode 100644 index 0000000000..a25a269a68 --- /dev/null +++ b/src/mainboard/system76/whl-u/acpi/mainboard.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + #include "ac.asl" + #include "battery.asl" + #include "buttons.asl" + #include "hid.asl" + #include "lid.asl" +} diff --git a/src/mainboard/system76/whl-u/acpi/superio.asl b/src/mainboard/system76/whl-u/acpi/superio.asl new file mode 100644 index 0000000000..9e01ed8b92 --- /dev/null +++ b/src/mainboard/system76/whl-u/acpi/superio.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/system76/whl-u/acpi_tables.c b/src/mainboard/system76/whl-u/acpi_tables.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/system76/whl-u/board_info.txt b/src/mainboard/system76/whl-u/board_info.txt new file mode 100644 index 0000000000..6ae000b0e6 --- /dev/null +++ b/src/mainboard/system76/whl-u/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: System76 +Board name: whl-u +Category: laptop +Release year: 2019 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb new file mode 100644 index 0000000000..1a5a85100d --- /dev/null +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -0,0 +1,241 @@ +chip soc/intel/cannonlake + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + +# ACPI (soc/intel/cannonlake/acpi.c) + # Enable s0ix + register "s0ix_enable" = "0" + + # PM Timer Enabled + register "PmTimerDisabled" = "0" + + # Disable DPTF + register "dptf_enable" = "0" + +# CPU (soc/intel/cannonlake/cpu.c) + # Power limit + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "25" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + +# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) + register "SaGv" = "SaGv_Enabled" + register "VmxEnable" = "1" + #register "enable_c6dram" = "1" + register "DebugConsent" = "DebugConsent_Disabled" + +# FSP Silicon (soc/intel/cannonlake/fsp_params.c) + # SATA + register "SataMode" = "Sata_AHCI" + register "SataSalpSupport" = "0" + + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "0" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "0" + register "SataPortsEnable[4]" = "0" + register "SataPortsEnable[5]" = "0" + register "SataPortsEnable[6]" = "0" + register "SataPortsEnable[7]" = "0" + + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "SataPortsDevSlp[3]" = "0" + register "SataPortsDevSlp[4]" = "0" + register "SataPortsDevSlp[5]" = "0" + register "SataPortsDevSlp[6]" = "0" + register "SataPortsDevSlp[7]" = "0" + + # Audio + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkHda" = "1" + register "PchHdaAudioLinkDmic0" = "1" + register "PchHdaAudioLinkDmic1" = "1" + register "PchHdaAudioLinkSsp0" = "0" + register "PchHdaAudioLinkSsp1" = "0" + register "PchHdaAudioLinkSsp2" = "0" + register "PchHdaAudioLinkSndw1" = "0" + register "PchHdaAudioLinkSndw2" = "0" + register "PchHdaAudioLinkSndw3" = "0" + register "PchHdaAudioLinkSndw4" = "0" + + # USB + register "SsicPortEnable" = "0" + + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # 3G / LTE + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB Board port 4 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Finger print + register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # T17, T18 + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[10]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[11]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[12]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[13]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[14]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[15]" = "USB2_PORT_EMPTY" # NC + + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C port 3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Board port 4 + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Used by TBT + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Used by TBT + register "usb3_ports[6]" = "USB3_PORT_EMPTY" # NC + register "usb3_ports[7]" = "USB3_PORT_EMPTY" # NC + register "usb3_ports[8]" = "USB3_PORT_EMPTY" # NC + register "usb3_ports[9]" = "USB3_PORT_EMPTY" # NC + + # PCI Express Root port #5 x4, Clock 4 (TBT) + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpHotPlug[4]" = "1" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcClkReq[4]" = "4" + + # PCI Express Root port #9 x1, Clock 3 (LAN) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[3]" = "8" + register "PcieClkSrcClkReq[3]" = "3" + + # PCI Express Root port #10 x1, Clock 2 (WLAN) + register "PcieRpEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "0" + register "PcieClkSrcUsage[2]" = "9" + register "PcieClkSrcClkReq[2]" = "2" + + # PCI Express Root port #13 x4, Clock 5 (NVMe) + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[5]" = "12" + register "PcieClkSrcClkReq[5]" = "5" + + # Misc + register "Device4Enable" = "1" + register "HeciEnabled" = "1" + register "AcousticNoiseMitigation" = "1" + #register "dmipwroptimize" = "1" + #register "satapwroptimize" = "1" + + # Power + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "2" # 500ms + register "PchPmSlpAMinAssert" = "4" # 2s + + # Thermal + register "tcc_offset" = "12" + + # Serial IRQ Continuous + register "SerialIrqConfigSirqMode" = "1" + +# LPC (soc/intel/cannonlake/lpc.c) + # LPC configuration from lspci -xxx + register "gen1_dec" = "0x000c0081" + register "gen2_dec" = "0x00040069" + register "gen3_dec" = "0x000c3321" + register "gen4_dec" = "0x00000000" + + # 8254 + register "clock_gate_8254" = "0" + +# PMC (soc/intel/cannonlake/pmc.c) + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "0" + +# PM Util (soc/intel/cannonlake/pmutil.c) + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + register "gpe0_dw0" = "PMC_GPP_C" + register "gpe0_dw1" = "PMC_GPP_D" + register "gpe0_dw2" = "PMC_GPP_E" + +# Actual device tree + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + #chip drivers/intel/wifi + # register "wake" = "PME_B0_EN_BIT" + device pci 14.3 on end # CNVi wifi + #end + device pci 14.5 off end # SDCard + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 on end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 off end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/system76/whl-u/dsdt.asl b/src/mainboard/system76/whl-u/dsdt.asl new file mode 100644 index 0000000000..0c04ff6342 --- /dev/null +++ b/src/mainboard/system76/whl-u/dsdt.asl @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include + + // global NVS and variables + #include + + // CPU + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + } + } + + // Chipset specific sleep states + #include + + // Mainboard specific + #include "acpi/mainboard.asl" + + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include "acpi/superio.asl" + /* ACPI code for EC functions */ + #include "acpi/ec.asl" + } +} diff --git a/src/mainboard/system76/whl-u/gpio.h b/src/mainboard/system76/whl-u/gpio.h new file mode 100644 index 0000000000..04a6f732a6 --- /dev/null +++ b/src/mainboard/system76/whl-u/gpio.h @@ -0,0 +1,449 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include +#include + +#ifndef __ACPI__ + +#define PAD_CFG_NC(pad) PAD_NC(pad, NONE) + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + /* PM_BATLOW# */ + _PAD_CFG_STRUCT(GPD0, 0x4000100, 0x0), + /* AC_PRESENT */ + _PAD_CFG_STRUCT(GPD1, 0x44000700, 0x3c00), + /* NC */ + PAD_CFG_NC(GPD2), + /* PWR_BTN# */ + _PAD_CFG_STRUCT(GPD3, 0x44000700, 0x3000), + /* SUSB#_PCH */ + _PAD_CFG_STRUCT(GPD4, 0x44000600, 0x0), + /* SUSC#_PCH */ + _PAD_CFG_STRUCT(GPD5, 0x44000600, 0x0), + /* SLP_A# */ + _PAD_CFG_STRUCT(GPD6, 0x44000600, 0x0), + /* SUSWARN# */ + _PAD_CFG_STRUCT(GPD7, 0x4000100, 0x0), + /* SUS_CLK */ + _PAD_CFG_STRUCT(GPD8, 0x44000700, 0x0), + /* T69 */ + _PAD_CFG_STRUCT(GPD9, 0x4000100, 0x0), + /* T21 */ + _PAD_CFG_STRUCT(GPD10, 0x44000600, 0x0), + /* NC */ + PAD_CFG_NC(GPD11), + /* SB_KBCRST# */ + _PAD_CFG_STRUCT(GPP_A0, 0x44000700, 0x0), + /* LPC_AD0 */ + _PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x3c00), + /* LPC_AD1 */ + _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x3c00), + /* LPC_AD2 */ + _PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x3c00), + /* LPC_AD3 */ + _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x3c00), + /* LPC_FRAME# */ + _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), + /* SERIRQ with pull up */ + _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x0), + /* TPM_PIRQ# */ + _PAD_CFG_STRUCT(GPP_A7, 0x44000100, 0x0), + /* PM_CLKRUN# with pull-up */ + _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0), + /* PCLK_KBC */ + _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), + /* NC */ + PAD_CFG_NC(GPP_A10), + /* NC */ + PAD_CFG_NC(GPP_A11), + /* PCH_GPP_A12 with pull-up */ + _PAD_CFG_STRUCT(GPP_A12, 0x44000100, 0x0), + /* SUSWARN# with tie to SUS_PWR_ACK */ + _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), + /* SUS_STAT# T15 */ + _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), + /* SUS_PWR_ACK with tie to SUSWARN# */ + _PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x3000), + /* NC */ + PAD_CFG_NC(GPP_A16), + /* LIGHT_KB_DET# */ + _PAD_CFG_STRUCT(GPP_A17, 0x44000100, 0x0), + /* T56 */ + _PAD_CFG_STRUCT(GPP_A18, 0x44000100, 0x0), + /* SATA_PWR_EN */ + _PAD_CFG_STRUCT(GPP_A19, 0x44000100, 0x0), + /* NC */ + PAD_CFG_NC(GPP_A20), + /* NC */ + PAD_CFG_NC(GPP_A21), + /* PS8338B_SW */ + _PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), + /* PS8338B_PCH */ + _PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x0), + /* CORE_VID0 with pull-up and pull-down */ + _PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), + /* CORE_VID1 with pull-up and pull-down */ + _PAD_CFG_STRUCT(GPP_B1, 0x44000100, 0x0), + /* CNVI_WAKE# */ + _PAD_CFG_STRUCT(GPP_B2, 0x44000100, 0x0), + /* NC */ + PAD_CFG_NC(GPP_B3), + /* NC */ + PAD_CFG_NC(GPP_B4), + /* NC */ + PAD_CFG_NC(GPP_B5), + /* NC */ + PAD_CFG_NC(GPP_B6), + /* WLAN_CLKREQ# */ + _PAD_CFG_STRUCT(GPP_B7, 0x44000700, 0x0), + /* LAN_CLKREQ# */ + _PAD_CFG_STRUCT(GPP_B8, 0x44000700, 0x0), + /* TBT_CLKREQ# */ + _PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), + /* SSD_CLKREQ# */ + _PAD_CFG_STRUCT(GPP_B10, 0x44000700, 0x0), + /* EXT_PWR_GATE# */ + _PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), + /* SLP_S0# with pull-down */ + _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0), + /* PLT_RST# with pull-down */ + _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), + /* PCH_SPKR */ + _PAD_CFG_STRUCT(GPP_B14, 0x44000700, 0x0), + /* NC */ + PAD_CFG_NC(GPP_B15), + /* T16 */ + PAD_CFG_NC(GPP_B16), + /* T35 */ + PAD_CFG_NC(GPP_B17), + /* Pull-down - strap for disabling no reboot mode */ + PAD_CFG_NC(GPP_B18), + /* NC */ + PAD_CFG_NC(GPP_B19), + /* NC */ + PAD_CFG_NC(GPP_B20), + /* NC */ + PAD_CFG_NC(GPP_B21), + /* T14 */ + PAD_CFG_NC(GPP_B22), + /* T57 */ + PAD_CFG_NC(GPP_B23), + /* SMB_CLK_DDR */ + _PAD_CFG_STRUCT(GPP_C0, 0x44000700, 0x0), + /* SMB_DAT_DDR */ + _PAD_CFG_STRUCT(GPP_C1, 0x44000700, 0x0), + /* PCH_GPP_C2 with pull-up */ + _PAD_CFG_STRUCT(GPP_C2, 0x44000100, 0x0), + /* NC */ + PAD_CFG_NC(GPP_C3), + /* NC */ + PAD_CFG_NC(GPP_C4), + /* WLAN_WAKEUP#, NC */ + _PAD_CFG_STRUCT(GPP_C5, 0x44000100, 0x0), + /* T61, LAN_WAKEUP# */ + _PAD_CFG_STRUCT(GPP_C6, 0x44000100, 0x0), + /* T64 */ + PAD_CFG_NC(GPP_C7), + /* NC */ + PAD_CFG_NC(GPP_C8), +#if CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID == 0x1325 + /* TBCIO_PLUG_EVENT */ + _PAD_CFG_STRUCT(GPP_C9, 0x84800100, 0x3000), +#elif CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID == 0x1323 + /* TBCIO_PLUG_EVENT */ + _PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000), +#else + #error Unknown Mainboard +#endif + /* TBT_FRC_PWR */ + _PAD_CFG_STRUCT(GPP_C10, 0x84000200, 0x0), + /* NC */ + PAD_CFG_NC(GPP_C11), + /* GPP_C12_RTD3 */ + _PAD_CFG_STRUCT(GPP_C12, 0x84000201, 0x0), + /* SSD_PW R_DN# */ + _PAD_CFG_STRUCT(GPP_C13, 0x84000201, 0x0), + /* TBTA_HRESET */ + _PAD_CFG_STRUCT(GPP_C14, 0x84000200, 0x0), + /* TBT_PERST_N */ + _PAD_CFG_STRUCT(GPP_C15, 0x84000201, 0x3000), +#if CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID == 0x1325 + /* I2C_SDA_TP */ + _PAD_CFG_STRUCT(GPP_C16, 0x44000700, 0x0), + /* I2C_SCL_TP */ + _PAD_CFG_STRUCT(GPP_C17, 0x44000700, 0x0), +#elif CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID == 0x1323 + /* T_SDA */ + _PAD_CFG_STRUCT(GPP_C16, 0x44000700, 0x0), + /* T_SCL */ + _PAD_CFG_STRUCT(GPP_C17, 0x44000700, 0x0), +#else + #error Unknown Mainboard +#endif + /* NC */ + PAD_CFG_NC(GPP_C18), + /* NC, SWI */ + _PAD_CFG_STRUCT(GPP_C19, 0x44000100, 0x0), + /* UART2_RXD */ + _PAD_CFG_STRUCT(GPP_C20, 0x44000700, 0x0), + /* UART2_TXD */ + _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), + /* NC */ + PAD_CFG_NC(GPP_C22), +#if CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID == 0x1325 + /* TP_ATTN# */ + _PAD_CFG_STRUCT(GPP_C23, 0x80100100, 0x0), +#elif CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID == 0x1323 + /* NC */ + PAD_CFG_NC(GPP_C23), +#else + #error Unknown Mainboard +#endif + /* NC */ + PAD_CFG_NC(GPP_D0), + /* NC */ + PAD_CFG_NC(GPP_D1), + /* NC */ + PAD_CFG_NC(GPP_D2), + /* NC */ + PAD_CFG_NC(GPP_D3), + /* NC */ + PAD_CFG_NC(GPP_D4), + /* NC */ + PAD_CFG_NC(GPP_D5), + /* NC */ + PAD_CFG_NC(GPP_D6), + /* NC */ + PAD_CFG_NC(GPP_D7), + /* SB_BLON */ + _PAD_CFG_STRUCT(GPP_D8, 0x44000201, 0x0), + /* SWI# */ + _PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0), + /* NC */ + PAD_CFG_NC(GPP_D10), + /* RTD3_PCIE_WAKE# */ + _PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000), + /* T33 */ + PAD_CFG_NC(GPP_D12), + /* NC */ + PAD_CFG_NC(GPP_D13), + /* NC */ + PAD_CFG_NC(GPP_D14), + /* NC */ + PAD_CFG_NC(GPP_D15), + /* NC, RTD3_3G_PW R_EN */ + _PAD_CFG_STRUCT(GPP_D16, 0x4000201, 0x0), + /* NC */ + PAD_CFG_NC(GPP_D17), + /* NC */ + PAD_CFG_NC(GPP_D18), + /* GPPC_DMIC_CLK */ + _PAD_CFG_STRUCT(GPP_D19, 0x44000500, 0x0), + /* GPPC_DMIC_DATA */ + _PAD_CFG_STRUCT(GPP_D20, 0x44000500, 0x0), + /* TPM_DET# */ + _PAD_CFG_STRUCT(GPP_D21, 0x44000100, 0x0), + /* TPM_TCM_Detect */ + _PAD_CFG_STRUCT(GPP_D22, 0x44000100, 0x0), + /* T32 */ + PAD_CFG_NC(GPP_D23), + /* PCH_GPP_E0 with pull-up */ + _PAD_CFG_STRUCT(GPP_E0, 0x44000100, 0x0), + /* SATA_ODD_PRSNT# */ + _PAD_CFG_STRUCT(GPP_E1, 0x44000100, 0x0), + /* SATAGP2 */ + //TODO: Should this be function 2? + _PAD_CFG_STRUCT(GPP_E2, 0x44000700, 0x3000), + /* NC */ + PAD_CFG_NC(GPP_E3), + /* T64 */ + PAD_CFG_NC(GPP_E4), + /* T60 */ + PAD_CFG_NC(GPP_E5), + /* DEVSLP2 */ + _PAD_CFG_STRUCT(GPP_E6, 0x44000700, 0x0), + /* NC */ + PAD_CFG_NC(GPP_E7), + /* PCH_SATAHDD_LED# */ + _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), + /* GP_BSSB_CLK with pull-up, T30 */ + _PAD_CFG_STRUCT(GPP_E9, 0x44000100, 0x0), + /* GPP_E10 with pull-up, T31 */ + _PAD_CFG_STRUCT(GPP_E10, 0x44000100, 0x0), + /* GPP_E11 with pull-up, T28 */ + _PAD_CFG_STRUCT(GPP_E11, 0x44000100, 0x0), + /* USB_OC#78 with pull-up, T29 */ + _PAD_CFG_STRUCT(GPP_E12, 0x44000100, 0x0), + /* MUX_HPD */ + _PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), + /* HDMI_HPD */ + _PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), + /* SMI# */ + _PAD_CFG_STRUCT(GPP_E15, 0x44000100, 0x0), + /* SCI# */ + _PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0), + /* EDP_HPD */ + _PAD_CFG_STRUCT(GPP_E17, 0x44000700, 0x0), + /* MDP_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x0), + /* MDP_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_E19, 0x44000600, 0x0), + /* HDMI_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_E20, 0x44000700, 0x0), + /* HDMI_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_E21, 0x44000600, 0x0), + /* NC */ + PAD_CFG_NC(GPP_E22), + /* NC */ + PAD_CFG_NC(GPP_E23), + /* CNVI_GNSS_PA_BLANKING */ + _PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0), + /* NC */ + PAD_CFG_NC(GPP_F1), + /* NC */ + PAD_CFG_NC(GPP_F2), + /* NC */ + PAD_CFG_NC(GPP_F3), + /* CNVI_BRI_DT */ + _PAD_CFG_STRUCT(GPP_F4, 0x44000700, 0x0), + /* CNVI_BRI_RSP */ + _PAD_CFG_STRUCT(GPP_F5, 0x44000700, 0x0), + /* CNVI_RGI_DT */ + _PAD_CFG_STRUCT(GPP_F6, 0x44000700, 0x3000), + /* CNVI_RGI_RSP */ + _PAD_CFG_STRUCT(GPP_F7, 0x44000700, 0x0), + /* CNVI_MFUART2_RXD */ + _PAD_CFG_STRUCT(GPP_F8, 0x44000700, 0x3000), + /* CNVI_MFUART2_TXD */ + _PAD_CFG_STRUCT(GPP_F9, 0x44000700, 0x0), + /* NC */ + PAD_CFG_NC(GPP_F10), + /* NC */ + PAD_CFG_NC(GPP_F11), + /* NC */ + PAD_CFG_NC(GPP_F12), + /* NC */ + PAD_CFG_NC(GPP_F13), + /* NC */ + PAD_CFG_NC(GPP_F14), + /* NC */ + PAD_CFG_NC(GPP_F15), + /* NC */ + PAD_CFG_NC(GPP_F16), + /* NC */ + PAD_CFG_NC(GPP_F17), + /* NC */ + PAD_CFG_NC(GPP_F18), + /* NC */ + PAD_CFG_NC(GPP_F19), + /* NC */ + PAD_CFG_NC(GPP_F20), + /* NC */ + PAD_CFG_NC(GPP_F21), + /* NC */ + PAD_CFG_NC(GPP_F22), + /* A4WP_PRESENT */ + _PAD_CFG_STRUCT(GPP_F23, 0x44000700, 0x0), + /* NC, EDP_DET */ + PAD_CFG_NC(GPP_G0), + /* NC */ + PAD_CFG_NC(GPP_G1), + /* NC */ + PAD_CFG_NC(GPP_G2), +#if CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID == 0x1325 + /* NC */ + _PAD_CFG_STRUCT(GPP_G3, 0x44000100, 0x0), + /* NC */ + _PAD_CFG_STRUCT(GPP_G4, 0x44000100, 0x0), +#elif CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID == 0x1323 + /* ASM1543_I_SEL0 */ + _PAD_CFG_STRUCT(GPP_G3, 0x44000200, 0x0), + /* ASM1543_I_SEL1 */ + _PAD_CFG_STRUCT(GPP_G4, 0x44000200, 0x0), +#else + #error Unknown Mainboard +#endif + /* BOARD_ID */ + _PAD_CFG_STRUCT(GPP_G5, 0x44000100, 0x0), + /* NC */ + _PAD_CFG_STRUCT(GPP_G6, 0x44000100, 0x0), + /* TBT_Detect */ + _PAD_CFG_STRUCT(GPP_G7, 0x44000100, 0x0), + /* NC */ + PAD_CFG_NC(GPP_H0), + /* CNVI_RST# */ + _PAD_CFG_STRUCT(GPP_H1, 0x44000f00, 0x0), + /* CNVI_CLKREQ */ + _PAD_CFG_STRUCT(GPP_H2, 0x44000f00, 0x0), + /* NC */ + PAD_CFG_NC(GPP_H3), + /* T23 */ + PAD_CFG_NC(GPP_H4), + /* T22 */ + PAD_CFG_NC(GPP_H5), + /* NC */ + PAD_CFG_NC(GPP_H6), + /* NC */ + PAD_CFG_NC(GPP_H7), + /* NC */ + PAD_CFG_NC(GPP_H8), + /* NC */ + PAD_CFG_NC(GPP_H9), + /* NC */ + PAD_CFG_NC(GPP_H10), + /* NC */ + PAD_CFG_NC(GPP_H11), + /* NC */ + PAD_CFG_NC(GPP_H12), + /* NC */ + PAD_CFG_NC(GPP_H13), + /* G_INT1 */ + _PAD_CFG_STRUCT(GPP_H14, 0x44000100, 0x0), + /* NC */ + PAD_CFG_NC(GPP_H15), + /* NC */ + PAD_CFG_NC(GPP_H16), + /* NC */ + PAD_CFG_NC(GPP_H17), + /* CPU_C10_GATE# */ + _PAD_CFG_STRUCT(GPP_H18, 0x44000700, 0x0), + /* NC */ + PAD_CFG_NC(GPP_H19), + /* NC */ + PAD_CFG_NC(GPP_H20), + /* Pull-up and pull-down */ + _PAD_CFG_STRUCT(GPP_H21, 0x44000100, 0x0), + /* TBT_RTD3_PWR_EN_R */ + _PAD_CFG_STRUCT(GPP_H22, 0x44000100, 0x0), + /* NC, WIGIG_PEWAKE */ + _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x0), +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + /* UART2_RXD */ + _PAD_CFG_STRUCT(GPP_C20, 0x44000700, 0x0), + /* UART2_TXD */ + _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), +}; + +#endif + +#endif diff --git a/src/mainboard/system76/whl-u/ramstage.c b/src/mainboard/system76/whl-u/ramstage.c new file mode 100644 index 0000000000..ec125ecfa6 --- /dev/null +++ b/src/mainboard/system76/whl-u/ramstage.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) { + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +static void mainboard_enable(struct device *dev) { + pc_keyboard_init(NO_AUX_DEVICE); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/system76/whl-u/romstage.c b/src/mainboard/system76/whl-u/romstage.c new file mode 100644 index 0000000000..0a4e208c82 --- /dev/null +++ b/src/mainboard/system76/whl-u/romstage.c @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +//TODO: find correct values +static const struct cnl_mb_cfg memcfg = { + /* + * For each channel, there are 3 sets of DQ byte mappings, + * where each set has a package 0 and a package 1 value (package 0 + * represents the first 64-bit lpddr4 chip combination, and package 1 + * represents the second 64-bit lpddr4 chip combination). + * The first three sets are for CLK, CMD, and CTL. + * The fsp package actually expects 6 sets, but the last 3 sets are + * not used in CNL, so we only define the three sets that are used + * and let the meminit_lpddr4() routine take care of clearing the + * unused fields for the caller. + */ + .dq_map[DDR_CH0] = { + {0x0F, 0xF0}, {0x00, 0xF0}, {0x0F, 0xF0}, + //{0x0F, 0x00}, {0xFF, 0x00}, {0xFF, 0x00} + }, + .dq_map[DDR_CH1] = { + {0x33, 0xCC}, {0x00, 0xCC}, {0x33, 0xCC}, + //{0x33, 0x00}, {0xFF, 0x00}, {0xFF, 0x00} + }, + + /* + * DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a + * mapping of a dq bit on the CPU to the bit it's connected to on + * the memory part. The array index represents the dqs bit number + * on the memory part, and the values in the array represent which + * pin on the CPU that DRAM pin connects to. + */ + .dqs_map[DDR_CH0] = {0, 1, 3, 2, 4, 5, 6, 7}, + .dqs_map[DDR_CH1] = {1, 0, 4, 5, 2, 3, 6, 7}, + + /* + * Rcomp resistor values. These values represent the resistance in + * ohms of the three rcomp resistors attached to the DDR_COMP_0, + * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. + */ + .rcomp_resistor = { 121, 81, 100 }, + + /* + * Rcomp target values. These will typically be the following + * values for Cannon Lake : { 80, 40, 40, 40, 30 } + */ + .rcomp_targets = { 100, 40, 20, 20, 26 }, + + /* + * Indicates whether memory is interleaved. + * Set to 1 for an interleaved design, + * set to 0 for non-interleaved design. + */ + .dq_pins_interleaved = 1, + + /* + * VREF_CA configuraation. + * Set to 0 VREF_CA goes to both CH_A and CH_B, + * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, + * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. + */ + .vref_ca_config = 2, + + /* Early Command Training Enabled */ + .ect = 1, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) { + const struct spd_info spd = { + .spd_smbus_address[0] = 0xA0, + .spd_smbus_address[2] = 0xA4, + }; + + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg, &spd); +} diff --git a/src/mainboard/system76/whl-u/variants/darp5/hda_verb.c b/src/mainboard/system76/whl-u/variants/darp5/hda_verb.c new file mode 100644 index 0000000000..ce9aed8ae5 --- /dev/null +++ b/src/mainboard/system76/whl-u/variants/darp5/hda_verb.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC293 */ + 0x10ec0293, /* Vendor ID */ + 0x15581325, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15581325), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x02211020), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x02a11050), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x41738205), + AZALIA_PIN_CFG(0, 0x1e, 0x02451130), + /* Intel, KabylakeHDMI */ + 0x8086280b, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/src/mainboard/system76/whl-u/variants/galp3-c/hda_verb.c b/src/mainboard/system76/whl-u/variants/galp3-c/hda_verb.c new file mode 100644 index 0000000000..200748515f --- /dev/null +++ b/src/mainboard/system76/whl-u/variants/galp3-c/hda_verb.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC293 */ + 0x10ec0293, /* Vendor ID */ + 0x15581323, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15581323), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x02211020), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x02a11040), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40738205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + /* Intel, KabylakeHDMI */ + 0x8086280b, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index ab7c765043..fe53f3e202 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -315,6 +315,11 @@ struct soc_intel_cannonlake_config { */ uint8_t SerialIoDevMode[PchSerialIoIndexMAX]; + enum { + SERIAL_IRQ_QUIET_MODE = 0, + SERIAL_IRQ_CONTINUOUS_MODE = 1, + } SerialIrqConfigSirqMode; + /* GPIO SD card detect pin */ unsigned int sdcard_cd_gpio; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 17a014b97e..358fac5e8b 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -255,6 +255,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Set TccActivationOffset */ tconfig->TccActivationOffset = config->tcc_offset; + + /* Set correct Sirq mode based on config */ + params->PchSirqMode = config->SerialIrqConfigSirqMode; } /* Mainboard GPIO Configuration */ diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index c33b3c33d4..226e1010d6 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -212,6 +212,8 @@ static void clock_gate_8254(const struct device *dev) void lpc_soc_init(struct device *dev) { + const config_t *config = dev->chip_info; + /* Legacy initialization */ isa_dma_init(); pch_misc_init(); @@ -220,7 +222,7 @@ void lpc_soc_init(struct device *dev) lpc_enable_pci_clk_cntl(); /* Set LPC Serial IRQ mode */ - if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) + if (config->SerialIrqConfigSirqMode) lpc_set_serirq_mode(SERIRQ_CONTINUOUS); else lpc_set_serirq_mode(SERIRQ_QUIET); diff --git a/system76/build.sh b/system76/build.sh new file mode 100755 index 0000000000..1b7dfa63da --- /dev/null +++ b/system76/build.sh @@ -0,0 +1,31 @@ +#!/usr/bin/env bash + +set -e + +export BUILD_TIMELESS=1 + +D="$(dirname "$(realpath "$0")")" + +for N in "$@" +do + P="$D/$N" + if [ ! -d "$P" ] + then + echo "$0 [model]" + exit 1 + fi + + # Ensure a clean build + make distclean + + # Copy motherboard configuration + cp -v "$P/config" ".config" + + # Compile coreboot + make oldconfig + make seabios + time make -j$(nproc) + + # Copy coreboot file to product directory + cp -v build/coreboot.rom "$P/coreboot" +done diff --git a/system76/darp5/chip b/system76/darp5/chip new file mode 100644 index 0000000000..f762617b72 --- /dev/null +++ b/system76/darp5/chip @@ -0,0 +1 @@ +GD25Q128C diff --git a/system76/darp5/config b/system76/darp5/config new file mode 100644 index 0000000000..d8280614d6 --- /dev/null +++ b/system76/darp5/config @@ -0,0 +1,855 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +CONFIG_CCACHE=y +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +# CONFIG_NO_RELOCATABLE_RAMSTAGE is not set +CONFIG_RELOCATABLE_RAMSTAGE=y +CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM=y +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_ELMEX is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SCALEWAY is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_SUPERMICRO is not set +CONFIG_VENDOR_SYSTEM76=y +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="system76/whl-u" +CONFIG_MAINBOARD_PART_NUMBER="darp5" +CONFIG_MAX_CPUS=8 +CONFIG_CBFS_SIZE=0xA00000 +CONFIG_UART_FOR_CONSOLE=2 +CONFIG_PAYLOAD_CONFIGFILE="" +CONFIG_MAINBOARD_VENDOR="System76" +CONFIG_VGA_BIOS_ID="8086,3ea0" +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_DIMM_SPD_SIZE=512 +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_VGA_BIOS_FILE="system76/$(VARIANT_DIR)/vga" +CONFIG_C_ENV_BOOTBLOCK_SIZE=0xC000 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1558 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1325 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="System76" +CONFIG_VARIANT_DIR="darp5" +CONFIG_DEVICETREE="devicetree.cb" +CONFIG_INTEL_GMA_VBT_FILE="system76/$(VARIANT_DIR)/vbt" +# CONFIG_POST_IO is not set +CONFIG_DCACHE_RAM_BASE=0xfef00000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_OVERRIDE_DEVICETREE="" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 +CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 +CONFIG_HAVE_INTEL_FIRMWARE=y +# CONFIG_POST_DEVICE is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_VBOOT is not set +CONFIG_DIMM_MAX=2 +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_TTYS0_LCS=3 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Darter Pro" +CONFIG_IFD_BIN_PATH="system76/$(VARIANT_DIR)/descriptor" +CONFIG_ME_BIN_PATH="system76/$(VARIANT_DIR)/me" +CONFIG_HAVE_IFD_BIN=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_M_FILE="$(obj)/Fsp_M.fd" +CONFIG_FSP_S_FILE="$(obj)/Fsp_S.fd" +CONFIG_FSP_S_CBFS="fsps.bin" +CONFIG_FSP_M_CBFS="fspm.bin" +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_MAINBOARD_VERSION="darp5" +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_CPU_MICROCODE_CBFS_LEN=0x0 +CONFIG_CPU_MICROCODE_CBFS_LOC=0x0 +CONFIG_SMBIOS_ENCLOSURE_TYPE=0x09 +# CONFIG_BOARD_SYSTEM76_GALP2 is not set +# CONFIG_BOARD_SYSTEM76_GALP3 is not set +# CONFIG_BOARD_SYSTEM76_GALP3_B is not set +# CONFIG_BOARD_SYSTEM76_GALP3_C is not set +CONFIG_BOARD_SYSTEM76_DARP5=y +CONFIG_CONSOLE_POST=y +CONFIG_PXE_ROM_ID="10ec,8168" +CONFIG_FSP_M_XIP=y +CONFIG_BOARD_ROMSIZE_KB_16384=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x1000000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y +# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set +CONFIG_POWER_STATE_ON_AFTER_FAILURE=y +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=1 +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_SYSTEM_TYPE_TABLET is not set +# CONFIG_SYSTEM_TYPE_DETACHABLE is not set +# CONFIG_SYSTEM_TYPE_CONVERTIBLE is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +CONFIG_CPU_SPECIFIC_OPTIONS=y +CONFIG_HEAP_SIZE=0x8000 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x200000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" +CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=216 +# CONFIG_SOC_CAVIUM_CN81XX is not set +CONFIG_ARCH_ARMV8_EXTENSION=0 +CONFIG_STACK_SIZE=0x1000 +# CONFIG_SOC_CAVIUM_COMMON is not set +# CONFIG_SOC_INTEL_GLK is not set +CONFIG_PCR_BASE_ADDRESS=0xfd000000 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_FSP_HEADER_PATH="3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" +CONFIG_FSP_FD_PATH="3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" +# CONFIG_NHLT_DMIC_1CH_16B is not set +# CONFIG_NHLT_DMIC_2CH_16B is not set +# CONFIG_NHLT_DMIC_4CH_16B is not set +# CONFIG_NHLT_MAX98357 is not set +# CONFIG_NHLT_DA7219 is not set +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_IFD_CHIPSET="cnl" +CONFIG_CPU_BCLK_MHZ=100 +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30 +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=3 +CONFIG_SOC_INTEL_I2C_DEV_MAX=6 +# CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE is not set +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_TTYS0_BASE=0x3e8 +CONFIG_SOC_INTEL_CANNONLAKE=y +CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE=y +# CONFIG_SOC_INTEL_COFFEELAKE is not set +CONFIG_SOC_INTEL_WHISKEYLAKE=y +# CONFIG_SOC_INTEL_CANNONLAKE_PCH_H is not set +# CONFIG_NHLT_MAX98373 is not set +CONFIG_MAX_ROOT_PORTS=16 +CONFIG_EXCLUDE_EMMC_INTERFACE=y +# CONFIG_USE_CANNONLAKE_CAR_NEM_ENHANCED is not set +CONFIG_USE_CANNONLAKE_FSP_CAR=y +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +# CONFIG_SOC_INTEL_KABYLAKE is not set +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=4 +CONFIG_SOC_INTEL_COMMON=y + +# +# Intel SoC Common Code +# +CONFIG_SOC_INTEL_COMMON_BLOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_CAR is not set +# CONFIG_INTEL_CAR_NEM is not set +# CONFIG_INTEL_CAR_CQOS is not set +# CONFIG_INTEL_CAR_NEM_ENHANCED is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y +CONFIG_SOC_INTEL_COMMON_BLOCK_EBDA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y +CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2=y +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y +# CONFIG_PMC_INVALID_READ_AFTER_WRITE is not set +CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y +CONFIG_SOC_AHCI_PORT_IMPLEMENTED_INVERT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0 +CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y +CONFIG_SA_PCIEX_LENGTH=0x10000000 +# CONFIG_SA_ENABLE_IMR is not set +# CONFIG_SA_ENABLE_DPR is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y +CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_VMX is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y + +# +# Intel SoC Common PCH Code +# +CONFIG_SOC_INTEL_COMMON_PCH_BASE=y +CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y +CONFIG_PCH_SPECIFIC_OPTIONS=y + +# +# Intel SoC Common coreboot stages +# +# CONFIG_DISPLAY_SMM_MEMORY_MAP is not set +CONFIG_SOC_INTEL_COMMON_RESET=y +CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y +# CONFIG_ACPI_CONSOLE is not set +# CONFIG_SOC_INTEL_COMMON_ACPI is not set +# CONFIG_SOC_INTEL_COMMON_ACPI_EC_PTS_WAK is not set +CONFIG_SOC_INTEL_COMMON_NHLT=y +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_MEDIATEK_MT8183 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_QUALCOMM_SDM845 is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_SSE2=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_MICROCODE_UPDATE_PRE_RAM=y +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +CONFIG_PARALLEL_MP=y +CONFIG_PARALLEL_MP_AP_WORK=y +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_CONSTANT_RATE=y +CONFIG_TSC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +# CONFIG_TSC_SYNC_MFENCE is not set +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_MODULE_HEAP_SIZE=0x4000 +CONFIG_SMM_STUB_STACK_SIZE=0x400 +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_NO_CAR_GLOBAL_MIGRATION=y +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set +CONFIG_CPU_UCODE_BINARIES="system76/$(VARIANT_DIR)/microcode" + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set + +# +# Super I/O +# +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +# CONFIG_EC_GOOGLE_WILCO is not set +CONFIG_EC_BASE_ACPI_DATA=0x930 +CONFIG_EC_BASE_ACPI_COMMAND=0x934 +CONFIG_EC_BASE_HOST_DATA=0x940 +CONFIG_EC_BASE_HOST_COMMAND=0x944 +CONFIG_EC_BASE_PACKET=0x950 +CONFIG_SEABIOS_PS2_TIMEOUT=1000 + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_MAINBOARD_USES_IFD_GBE_REGION is not set +# CONFIG_MAINBOARD_USES_IFD_EC_REGION is not set +# CONFIG_CAVIUM_BDK is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set +CONFIG_UDK_2017_BINDING=y +CONFIG_UDK_2013_VERSION=2013 +CONFIG_UDK_2015_VERSION=2015 +CONFIG_UDK_2017_VERSION=2017 +CONFIG_UDK_VERSION=2017 +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_USE_ARCH_TIMER is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_PPC64 is not set +# CONFIG_ARCH_BOOTBLOCK_PPC64 is not set +# CONFIG_ARCH_VERSTAGE_PPC64 is not set +# CONFIG_ARCH_ROMSTAGE_PPC64 is not set +# CONFIG_ARCH_RAMSTAGE_PPC64 is not set +# CONFIG_ARCH_RISCV is not set +CONFIG_ARCH_RISCV_M=y +# CONFIG_ARCH_RISCV_S is not set +# CONFIG_ARCH_RISCV_U is not set +# CONFIG_ARCH_RISCV_RV64 is not set +# CONFIG_ARCH_RISCV_RV32 is not set +# CONFIG_ARCH_RISCV_PMP is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +# CONFIG_RISCV_USE_ARCH_TIMER is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_POSTCAR_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_RAMBASE=0xe00000 +CONFIG_RAMTOP=0x1000000 +# CONFIG_CBMEM_TOP_BACKUP is not set +CONFIG_EARLY_EBDA_INIT=y +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_HPET_ADDRESS_OVERRIDE is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POSTCAR_STAGE=y +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +# CONFIG_PAGING_IN_CACHE_AS_RAM is not set +CONFIG_IDT_IN_EVERY_STAGE=y +CONFIG_HAVE_CF9_RESET=y + +# +# Devices +# +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_HAVE_FSP_GOP=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +# CONFIG_VGA_ROM_RUN is not set +CONFIG_RUN_FSP_GOP=y +# CONFIG_NO_GFX_INIT is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +CONFIG_PCI=y +# CONFIG_NO_MMCONF_SUPPORT is not set +CONFIG_MMCONF_SUPPORT=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_ELOG is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +CONFIG_CACHE_MRC_SETTINGS=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_MRC_SETTINGS_PROTECT=y +# CONFIG_HAS_RECOVERY_MRC_CACHE is not set +# CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN is not set +# CONFIG_MRC_SETTINGS_VARIABLE_DATA is not set +# CONFIG_MRC_WRITE_NV_LATE is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +# CONFIG_SMMSTORE is not set +# CONFIG_SMMSTORE_IN_CBFS is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +# CONFIG_HAVE_USBDEBUG is not set +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_AMD_PI is not set +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +CONFIG_DRIVERS_I2C_DESIGNWARE=y +# CONFIG_DRIVERS_I2C_DESIGNWARE_DEBUG is not set +# CONFIG_DRIVERS_I2C_MAX98373 is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCA9538 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_DRIVERS_I2C_SX9310 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set +# CONFIG_DISPLAY_HOBS is not set +# CONFIG_DISPLAY_UPD_DATA is not set +CONFIG_PLATFORM_USES_FSP2_0=y +# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set +# CONFIG_DISPLAY_FSP_HEADER is not set +CONFIG_FSP_T_CBFS="fspt.bin" +CONFIG_FSP_USE_REPO=y +CONFIG_FSP_T_FILE="$(obj)/Fsp_T.fd" +CONFIG_FSP_CAR=y +CONFIG_FSP_T_XIP=y +# CONFIG_FSP_USES_CB_STACK is not set +# CONFIG_VERIFY_HOBS is not set +CONFIG_DISPLAY_FSP_VERSION_INFO=y +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set +# CONFIG_INTEL_GMA_SWSMISCI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_LPC_TPM is not set +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_USB_ACPI is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# + +# +# Trusted Platform Module +# +CONFIG_USER_NO_TPM=y +# CONFIG_ACPI_SATA_GENERATOR is not set +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3e8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +# CONFIG_HAVE_OPTION_TABLE is not set +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_COMMON_FADT=y +CONFIG_ACPI_NHLT=y + +# +# System tables +# +# CONFIG_GENERATE_MP_TABLE is not set +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_BAYOU is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_LINUXBOOT is not set +CONFIG_PAYLOAD_SEABIOS=y +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_YABITS is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf" +CONFIG_SEABIOS_STABLE=y +# CONFIG_SEABIOS_MASTER is not set +# CONFIG_SEABIOS_REVISION is not set +CONFIG_SEABIOS_THREAD_OPTIONROMS=y +CONFIG_SEABIOS_VGA_COREBOOT=y +CONFIG_SEABIOS_BOOTORDER_FILE="" +# CONFIG_SEABIOS_ADD_SERCON_PORT_FILE is not set +CONFIG_PAYLOAD_VGABIOS_FILE="payloads/external/SeaBIOS/seabios/out/vgabios.bin" +CONFIG_SEABIOS_DEBUG_LEVEL=-1 + +# +# Using default SeaBIOS log level +# +CONFIG_PAYLOAD_OPTIONS="" +CONFIG_PXE=y + +# +# PXE Options +# +CONFIG_PXE_ROM=y +# CONFIG_BUILD_IPXE is not set +CONFIG_PXE_ROM_FILE="system76/$(VARIANT_DIR)/pxe" +# CONFIG_PXE_SERIAL_CONSOLE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +# CONFIG_PAYLOAD_FIT_SUPPORT is not set +CONFIG_COMPRESS_SECONDARY_PAYLOAD=y + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# + +# +# CPU Debug Settings +# +CONFIG_HAVE_DISPLAY_MTRRS=y +# CONFIG_DISPLAY_MTRRS is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +CONFIG_HAVE_DEBUG_GPIO=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_CBFS is not set +# CONFIG_HAVE_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +CONFIG_NO_EDID_FILL_FB=y +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +CONFIG_REG_SCRIPT=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_GENERIC_GPIO_LIB=y +CONFIG_C_ENVIRONMENT_BOOTBLOCK=y diff --git a/system76/darp5/coreboot b/system76/darp5/coreboot new file mode 100644 index 0000000000..0880741c9e Binary files /dev/null and b/system76/darp5/coreboot differ diff --git a/system76/darp5/coreboot-collector b/system76/darp5/coreboot-collector new file mode 100644 index 0000000000..4481e16f73 --- /dev/null +++ b/system76/darp5/coreboot-collector @@ -0,0 +1,234 @@ +## PCI ## +PCI Device: 0000:00:00.0: Class 0x00060000, Vendor 0x8086, Device 0x3E34, Revision 0x0B +PCI Device: 0000:00:02.0: Class 0x00030000, Vendor 0x8086, Device 0x3EA0, Revision 0x00 +PCI Device: 0000:00:12.0: Class 0x00118000, Vendor 0x8086, Device 0x9DF9, Revision 0x30 +PCI Device: 0000:00:14.0: Class 0x000C0330, Vendor 0x8086, Device 0x9DED, Revision 0x30 +PCI Device: 0000:00:14.2: Class 0x00050000, Vendor 0x8086, Device 0x9DEF, Revision 0x30 +PCI Device: 0000:00:14.3: Class 0x00028000, Vendor 0x8086, Device 0x9DF0, Revision 0x30 +PCI Device: 0000:00:15.0: Class 0x000C8000, Vendor 0x8086, Device 0x9DE8, Revision 0x30 +PCI Device: 0000:00:17.0: Class 0x00010601, Vendor 0x8086, Device 0x9DD3, Revision 0x30 +PCI Device: 0000:00:1c.0: Class 0x00060400, Vendor 0x8086, Device 0x9DBC, Revision 0xF0 +PCI Device: 0000:00:1d.0: Class 0x00060400, Vendor 0x8086, Device 0x9DB0, Revision 0xF0 +PCI Device: 0000:00:1f.0: Class 0x00060100, Vendor 0x8086, Device 0x9D84, Revision 0x30 +PCI Device: 0000:00:1f.3: Class 0x00040300, Vendor 0x8086, Device 0x9DC8, Revision 0x30 +PCI Device: 0000:00:1f.4: Class 0x000C0500, Vendor 0x8086, Device 0x9DA3, Revision 0x30 +PCI Device: 0000:00:1f.5: Class 0x000C8000, Vendor 0x8086, Device 0x9DA4, Revision 0x30 +PCI Device: 0000:39:00.0: Class 0x00FF0000, Vendor 0x10EC, Device 0x5287, Revision 0x01 +PCI Device: 0000:39:00.1: Class 0x00020000, Vendor 0x10EC, Device 0x8168, Revision 0x12 +## GPIO ## +300 Series PCH +GPP_A0 = 0x44000702 0x00000018 0x00000010 0x00000000 +GPP_A1 = 0x44000702 0x00003c19 0x00000010 0x00000000 +GPP_A2 = 0x44000702 0x00003c1a 0x00000010 0x00000000 +GPP_A3 = 0x44000702 0x00003c1b 0x00000010 0x00000000 +GPP_A4 = 0x44000702 0x00003c1c 0x00000010 0x00000000 +GPP_A5 = 0x44000700 0x0000001d 0x00000010 0x00000000 +GPP_A6 = 0x44000702 0x0000001e 0x00000010 0x00000000 +GPP_A7 = 0x44000102 0x0000001f 0x00000010 0x00000000 +GPP_A8 = 0x44000700 0x00000020 0x00000010 0x00000000 +GPP_A9 = 0x44000700 0x00001021 0x00000010 0x00000000 +GPP_A10 = 0x44000500 0x00001022 0x00000010 0x00000000 +GPP_A11 = 0x44000102 0x00003023 0x00000010 0x00000000 +GPP_A12 = 0x44000102 0x00000024 0x00000010 0x00000000 +GPP_A13 = 0x44000700 0x00000025 0x00000010 0x00000000 +GPP_A14 = 0x44000700 0x00000026 0x00000010 0x00000000 +GPP_A15 = 0x44000702 0x00003027 0x00000010 0x00000000 +GPP_A16 = 0x44000102 0x00000028 0x00000010 0x00000000 +GPP_A17 = 0x44000102 0x00000029 0x00000010 0x00000000 +GPP_A18 = 0x44000102 0x0000002a 0x00000010 0x00000000 +GPP_A19 = 0x44000102 0x0000002b 0x00000010 0x00000000 +GPP_A20 = 0x44000102 0x0000002c 0x00000010 0x00000000 +GPP_A21 = 0x44000102 0x0000002d 0x00000010 0x00000000 +GPP_A22 = 0x44000200 0x0000002e 0x00000010 0x00000000 +GPP_A23 = 0x44000102 0x0000002f 0x00000010 0x00000000 +GPP_B0 = 0x44000700 0x00000000 0x00000000 0x00000000 +GPP_B1 = 0x44000102 0x00000030 0x00000010 0x00000000 +GPP_B2 = 0x44000102 0x00000031 0x00000010 0x00000000 +GPP_B3 = 0x44000102 0x00000032 0x00000010 0x00000000 +GPP_B4 = 0x44000102 0x00000033 0x00000010 0x00000000 +GPP_B5 = 0x44000102 0x00000034 0x00000010 0x00000000 +GPP_B6 = 0x44000102 0x00000035 0x00000010 0x00000000 +GPP_B7 = 0x44000102 0x00000036 0x00000010 0x00000000 +GPP_B8 = 0x44000702 0x00000037 0x00000010 0x00000000 +GPP_B9 = 0x44000700 0x00000038 0x00000010 0x00000000 +GPP_B10 = 0x44000702 0x00000039 0x00000010 0x00000000 +GPP_B11 = 0x44000702 0x0000003a 0x00000010 0x00000000 +GPP_B12 = 0x44000102 0x0000003b 0x00000010 0x00000000 +GPP_B13 = 0x44000700 0x0000003c 0x00000010 0x00000000 +GPP_B14 = 0x44000700 0x0000003d 0x00000010 0x00000000 +GPP_B15 = 0x44000600 0x0000003e 0x00000010 0x00000000 +GPP_B16 = 0x44000102 0x0000003f 0x00000010 0x00000000 +GPP_B17 = 0x44000102 0x00000040 0x00000010 0x00000000 +GPP_B18 = 0x44000102 0x00000041 0x00000010 0x00000000 +GPP_B19 = 0x44000102 0x00000042 0x00000010 0x00000000 +GPP_B20 = 0x44000102 0x00000043 0x00000010 0x00000000 +GPP_B21 = 0x44000102 0x00000044 0x00000010 0x00000000 +GPP_B22 = 0x44000102 0x00000045 0x00000010 0x00000000 +GPP_B23 = 0x44000102 0x00000046 0x00000010 0x00000000 +GPP_G0 = 0x44000102 0x00000047 0x00000010 0x00000000 +GPP_G1 = 0x44000700 0x00000000 0x00000000 0x00000000 +GPP_G2 = 0x44000700 0x00000000 0x00000000 0x00000000 +GPP_G3 = 0x44000102 0x0000006c 0x00000010 0x00000000 +GPP_G4 = 0x44000102 0x0000006d 0x00000010 0x00000000 +GPP_G5 = 0x44000102 0x0000006e 0x00000010 0x00000000 +GPP_G6 = 0x44000102 0x0000006f 0x00000010 0x00000000 +GPP_G7 = 0x44000102 0x00000070 0x00000010 0x00000000 +GPP_D0 = 0x44000102 0x00000060 0x00000010 0x00000000 +GPP_D1 = 0x44000102 0x00000061 0x00000010 0x00000000 +GPP_D2 = 0x44000102 0x00000062 0x00000010 0x00000000 +GPP_D3 = 0x44000102 0x00000063 0x00000010 0x00000000 +GPP_D4 = 0x44000102 0x00000064 0x00000010 0x00000000 +GPP_D5 = 0x44000102 0x00000065 0x00000010 0x00000000 +GPP_D6 = 0x44000102 0x00000066 0x00000010 0x00000000 +GPP_D7 = 0x44000102 0x00000067 0x00000010 0x00000000 +GPP_D8 = 0x44000201 0x00000068 0x00000010 0x00000000 +GPP_D9 = 0x40880102 0x00000069 0x00000010 0x00000000 +GPP_D10 = 0x44000102 0x0000006a 0x00000010 0x00000000 +GPP_D11 = 0x40880102 0x0000306b 0x00000010 0x00000000 +GPP_D12 = 0x44000102 0x0000006c 0x00000810 0x00000000 +GPP_D13 = 0x44000102 0x0000006d 0x00000010 0x00000000 +GPP_D14 = 0x44000102 0x0000006e 0x00000010 0x00000000 +GPP_D15 = 0x44000102 0x0000006f 0x00000010 0x00000000 +GPP_D16 = 0x04000201 0x00000070 0x00000010 0x00000000 +GPP_D17 = 0x44000102 0x00000071 0x00000010 0x00000000 +GPP_D18 = 0x44000102 0x00000072 0x00000010 0x00000000 +GPP_D19 = 0x44000500 0x00000073 0x00000010 0x00000000 +GPP_D20 = 0x44000500 0x00000074 0x00000010 0x00000000 +GPP_D21 = 0x44000102 0x00000075 0x00000010 0x00000000 +GPP_D22 = 0x44000100 0x00000076 0x00000010 0x00000000 +GPP_D23 = 0x44000102 0x00000077 0x00000010 0x00000000 +GPP_F0 = 0x44000700 0x00000000 0x00000000 0x00000000 +GPP_F1 = 0x44000700 0x00000030 0x00000010 0x00000000 +GPP_F2 = 0x44000100 0x00000031 0x00000010 0x00000000 +GPP_F3 = 0x44000100 0x00000032 0x00000010 0x00000000 +GPP_F4 = 0x44000100 0x00000033 0x00000010 0x00000000 +GPP_F5 = 0x44000700 0x00000034 0x00000010 0x00000000 +GPP_F6 = 0x44000702 0x00003035 0x00000010 0x00000000 +GPP_F7 = 0x44000700 0x00000036 0x00000010 0x00000000 +GPP_F8 = 0x44000702 0x00003037 0x00000010 0x00000000 +GPP_F9 = 0x44000700 0x00000038 0x00000010 0x00000000 +GPP_F10 = 0x44000700 0x00000039 0x00000010 0x00000000 +GPP_F11 = 0x44000100 0x0000003a 0x00000010 0x00000000 +GPP_F12 = 0x44000100 0x0000003b 0x00000010 0x00000000 +GPP_F13 = 0x44000100 0x0000003c 0x00000010 0x00000000 +GPP_F14 = 0x44000100 0x0000003d 0x00000010 0x00000000 +GPP_F15 = 0x44000100 0x0000003e 0x00000010 0x00000000 +GPP_F16 = 0x44000100 0x0000003f 0x00000010 0x00000000 +GPP_F17 = 0x44000100 0x00000040 0x00000010 0x00000000 +GPP_F18 = 0x44000100 0x00000041 0x00000010 0x00000000 +GPP_F19 = 0x44000100 0x00000042 0x00000010 0x00000000 +GPP_F20 = 0x44000100 0x00000043 0x00000010 0x00000000 +GPP_F21 = 0x44000100 0x00000044 0x00000010 0x00000000 +GPP_F22 = 0x44000100 0x00000045 0x00000010 0x00000000 +GPP_F23 = 0x44000100 0x00000046 0x00000010 0x00000000 +GPP_H0 = 0x44000100 0x00001047 0x00000010 0x00000000 +GPP_H1 = 0x44000102 0x00000048 0x00000010 0x00000000 +GPP_H2 = 0x44000f00 0x00000049 0x00000010 0x00000000 +GPP_H3 = 0x44000f00 0x0000004a 0x00000010 0x00000000 +GPP_H4 = 0x44000102 0x0000004b 0x00000010 0x00000000 +GPP_H5 = 0x44000102 0x0000004c 0x00000010 0x00000000 +GPP_H6 = 0x44000102 0x0000004d 0x00000010 0x00000000 +GPP_H7 = 0x44000102 0x0000004e 0x00000010 0x00000000 +GPP_H8 = 0x44000102 0x0000004f 0x00000010 0x00000000 +GPP_H9 = 0x44000102 0x00000050 0x00000010 0x00000000 +GPP_H10 = 0x44000102 0x00000051 0x00000010 0x00000000 +GPP_H11 = 0x44000102 0x00000052 0x00000010 0x00000000 +GPP_H12 = 0x44000102 0x00000053 0x00000010 0x00000000 +GPP_H13 = 0x44000102 0x00000054 0x00000010 0x00000000 +GPP_H14 = 0x44000102 0x00000055 0x00000010 0x00000000 +GPP_H15 = 0x44000102 0x00000056 0x00000010 0x00000000 +GPP_H16 = 0x44000102 0x00000057 0x00000010 0x00000000 +GPP_H17 = 0x44000102 0x00000058 0x00000010 0x00000000 +GPP_H18 = 0x44000102 0x00000059 0x00000010 0x00000000 +GPP_H19 = 0x44000500 0x0000005a 0x00000010 0x00000000 +GPP_H20 = 0x44000102 0x0000005b 0x00000010 0x00000000 +GPP_H21 = 0x44000102 0x0000005c 0x00000010 0x00000000 +GPP_H22 = 0x44000102 0x0000005d 0x00000810 0x00000000 +GPP_H23 = 0x84000201 0x0000005e 0x00000010 0x00000000 +GPD0 = 0x04000102 0x00000060 0x00000010 0x00000000 +GPD1 = 0x44000700 0x00003c61 0x00000010 0x00000000 +GPD2 = 0x04000102 0x00003c62 0x00000010 0x00000000 +GPD3 = 0x44000702 0x00003063 0x00000010 0x00000000 +GPD4 = 0x44000600 0x00000064 0x00000010 0x00000000 +GPD5 = 0x44000600 0x00000065 0x00000010 0x00000000 +GPD6 = 0x44000600 0x00000066 0x00000010 0x00000000 +GPD7 = 0x04000102 0x00000067 0x00000810 0x00000000 +GPD8 = 0x44000700 0x00000068 0x00000010 0x00000000 +GPD9 = 0x04000102 0x00000069 0x00000010 0x00000000 +GPD10 = 0x44000600 0x0000006a 0x00000010 0x00000000 +GPD11 = 0x04000102 0x0000006b 0x00000010 0x00000000 +GPP_C0 = 0x44000702 0x00000048 0x00000010 0x00000000 +GPP_C1 = 0x44000702 0x00000049 0x00000010 0x00000000 +GPP_C2 = 0x44000102 0x0000004a 0x00000810 0x00000000 +GPP_C3 = 0x44000102 0x0000004b 0x00000010 0x00000000 +GPP_C4 = 0x44000102 0x0000004c 0x00000010 0x00000000 +GPP_C5 = 0x44000102 0x0000004d 0x00000010 0x00000000 +GPP_C6 = 0x44000102 0x0000004e 0x00000010 0x00000000 +GPP_C7 = 0x44000102 0x0000004f 0x00000010 0x00000000 +GPP_C8 = 0x44000102 0x00000050 0x00000010 0x00000000 +GPP_C9 = 0x84800102 0x00003051 0x00000010 0x00000000 +GPP_C10 = 0x84000200 0x00000052 0x00000010 0x00000000 +GPP_C11 = 0x44000102 0x00000053 0x00000010 0x00000000 +GPP_C12 = 0x84000201 0x00000054 0x00000010 0x00000000 +GPP_C13 = 0x84000201 0x00000055 0x00000010 0x00000000 +GPP_C14 = 0x84000200 0x00000056 0x00000010 0x00000000 +GPP_C15 = 0x84000201 0x00003057 0x00000010 0x00000000 +GPP_C16 = 0x44000702 0x00000058 0x00000010 0x00000000 +GPP_C17 = 0x44000702 0x00000059 0x00000010 0x00000000 +GPP_C18 = 0x44000102 0x0000005a 0x00000010 0x00000000 +GPP_C19 = 0x44000102 0x0000005b 0x00000010 0x00000000 +GPP_C20 = 0x44000102 0x0000005c 0x00000010 0x00000000 +GPP_C21 = 0x44000102 0x0000005d 0x00000010 0x00000000 +GPP_C22 = 0x44000102 0x0000005e 0x00000010 0x00000000 +GPP_C23 = 0x80100102 0x0000005f 0x00000010 0x00000000 +GPP_E0 = 0x44000102 0x00000018 0x00000010 0x00000000 +GPP_E1 = 0x44000102 0x00000019 0x00000010 0x00000000 +GPP_E2 = 0x44000700 0x0000301a 0x00000010 0x00000000 +GPP_E3 = 0x44000102 0x0000001b 0x00000010 0x00000000 +GPP_E4 = 0x44000102 0x0000001c 0x00000010 0x00000000 +GPP_E5 = 0x44000102 0x0000001d 0x00000010 0x00000000 +GPP_E6 = 0x44000700 0x0000001e 0x00000010 0x00000000 +GPP_E7 = 0x44000102 0x0000001f 0x00000010 0x00000000 +GPP_E8 = 0x44000700 0x00000020 0x00000010 0x00000000 +GPP_E9 = 0x44000102 0x00000021 0x00000810 0x00000000 +GPP_E10 = 0x44000102 0x00000022 0x00000810 0x00000000 +GPP_E11 = 0x44000102 0x00000023 0x00000810 0x00000000 +GPP_E12 = 0x44000102 0x00000024 0x00000010 0x00000000 +GPP_E13 = 0x44000700 0x00000025 0x00000010 0x00000000 +GPP_E14 = 0x44000700 0x00000026 0x00000010 0x00000000 +GPP_E15 = 0x44000102 0x00000027 0x00000010 0x00000000 +GPP_E16 = 0x80880102 0x00000028 0x00000010 0x00000000 +GPP_E17 = 0x44000702 0x00000029 0x00000010 0x00000000 +GPP_E18 = 0x44000702 0x0000002a 0x00000010 0x00000000 +GPP_E19 = 0x44000602 0x0000002b 0x00000810 0x00000000 +GPP_E20 = 0x44000702 0x0000002c 0x00000010 0x00000000 +GPP_E21 = 0x44000602 0x0000002d 0x00000810 0x00000000 +GPP_E22 = 0x44000102 0x0000002e 0x00000010 0x00000000 +GPP_E23 = 0x44000102 0x0000002f 0x00000010 0x00000000 +## HDAUDIO ## +hdaudioC0D0 + vendor_name: Realtek + chip_name: ALC293 + vendor_id: 0x10ec0293 + subsystem_id: 0x15581325 + revision_id: 0x100003 + 0x12: 0x90a60140 + 0x13: 0x40000000 + 0x14: 0x90170110 + 0x15: 0x02211020 + 0x16: 0x411111f0 + 0x18: 0x02a11050 + 0x19: 0x411111f0 + 0x1a: 0x411111f0 + 0x1b: 0x411111f0 + 0x1d: 0x41738205 + 0x1e: 0x02451130 +hdaudioC0D2 + vendor_name: Intel + chip_name: Kabylake HDMI + vendor_id: 0x8086280b + subsystem_id: 0x80860101 + revision_id: 0x100000 + 0x05: 0x18560010 + 0x06: 0x18560010 + 0x07: 0x18560010 diff --git a/system76/darp5/descriptor b/system76/darp5/descriptor new file mode 100644 index 0000000000..a906165cea Binary files /dev/null and b/system76/darp5/descriptor differ diff --git a/system76/darp5/flashrom b/system76/darp5/flashrom new file mode 100755 index 0000000000..75832cba0b Binary files /dev/null and b/system76/darp5/flashrom differ diff --git a/system76/darp5/gpio.h b/system76/darp5/gpio.h new file mode 100644 index 0000000000..87082b3705 --- /dev/null +++ b/system76/darp5/gpio.h @@ -0,0 +1,218 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include +#include + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + _PAD_CFG_STRUCT(GPD0, 0x4000100, 0x0), + _PAD_CFG_STRUCT(GPD1, 0x44000700, 0x3c00), + _PAD_CFG_STRUCT(GPD2, 0x4000100, 0x3c00), + _PAD_CFG_STRUCT(GPD3, 0x44000700, 0x3000), + _PAD_CFG_STRUCT(GPD4, 0x44000600, 0x0), + _PAD_CFG_STRUCT(GPD5, 0x44000600, 0x0), + _PAD_CFG_STRUCT(GPD6, 0x44000600, 0x0), + _PAD_CFG_STRUCT(GPD7, 0x4000100, 0x0), + _PAD_CFG_STRUCT(GPD8, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPD9, 0x4000100, 0x0), + _PAD_CFG_STRUCT(GPD10, 0x44000600, 0x0), + _PAD_CFG_STRUCT(GPD11, 0x4000100, 0x0), + _PAD_CFG_STRUCT(GPP_A0, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x3c00), + _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x3c00), + _PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x3c00), + _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x3c00), + _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_A7, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), + _PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x1000), + _PAD_CFG_STRUCT(GPP_A11, 0x44000100, 0x3000), + _PAD_CFG_STRUCT(GPP_A12, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x3000), + _PAD_CFG_STRUCT(GPP_A16, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_A17, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_A18, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_A19, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_A20, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_A21, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_A22, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B1, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B2, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B3, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B4, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B5, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B6, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B7, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B8, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B10, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B12, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B14, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B15, 0x44000600, 0x0), + _PAD_CFG_STRUCT(GPP_B16, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B17, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B18, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B19, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B20, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B21, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B22, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B23, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C0, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C1, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C2, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C3, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C4, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C5, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C6, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C7, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C8, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C9, 0x84800100, 0x3000), + _PAD_CFG_STRUCT(GPP_C10, 0x84000200, 0x0), + _PAD_CFG_STRUCT(GPP_C11, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C12, 0x84000201, 0x0), + _PAD_CFG_STRUCT(GPP_C13, 0x84000201, 0x0), + _PAD_CFG_STRUCT(GPP_C14, 0x84000200, 0x0), + _PAD_CFG_STRUCT(GPP_C15, 0x84000201, 0x3000), + _PAD_CFG_STRUCT(GPP_C16, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C17, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C18, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C19, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C20, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C21, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C22, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C23, 0x80100100, 0x0), + _PAD_CFG_STRUCT(GPP_D0, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D1, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D2, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D3, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D4, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D5, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D6, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D7, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D8, 0x44000201, 0x0), + _PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0), + _PAD_CFG_STRUCT(GPP_D10, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000), + _PAD_CFG_STRUCT(GPP_D12, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D13, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D14, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D15, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D16, 0x4000201, 0x0), + _PAD_CFG_STRUCT(GPP_D17, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D18, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D19, 0x44000500, 0x0), + _PAD_CFG_STRUCT(GPP_D20, 0x44000500, 0x0), + _PAD_CFG_STRUCT(GPP_D21, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D22, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D23, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E0, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E1, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E2, 0x44000700, 0x3000), + _PAD_CFG_STRUCT(GPP_E3, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E4, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E5, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E6, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E7, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E9, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E10, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E11, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E12, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E15, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0), + _PAD_CFG_STRUCT(GPP_E17, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E19, 0x44000600, 0x0), + _PAD_CFG_STRUCT(GPP_E20, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E21, 0x44000600, 0x0), + _PAD_CFG_STRUCT(GPP_E22, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E23, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F2, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F3, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F4, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F5, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F6, 0x44000700, 0x3000), + _PAD_CFG_STRUCT(GPP_F7, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F8, 0x44000700, 0x3000), + _PAD_CFG_STRUCT(GPP_F9, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F11, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F12, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F13, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F14, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F15, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F16, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F17, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F18, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F19, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F20, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F21, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F22, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F23, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_G1, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_G3, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_G4, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_G5, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_G6, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_G7, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H0, 0x44000100, 0x1000), + _PAD_CFG_STRUCT(GPP_H1, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H2, 0x44000f00, 0x0), + _PAD_CFG_STRUCT(GPP_H3, 0x44000f00, 0x0), + _PAD_CFG_STRUCT(GPP_H4, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H5, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H6, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H7, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H8, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H9, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H10, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H11, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H12, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H13, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H14, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H15, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H16, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H17, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H18, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H19, 0x44000500, 0x0), + _PAD_CFG_STRUCT(GPP_H20, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H21, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H22, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x0), +}; + +#endif + +#endif diff --git a/system76/darp5/hda_verb.c b/system76/darp5/hda_verb.c new file mode 100644 index 0000000000..ce9aed8ae5 --- /dev/null +++ b/system76/darp5/hda_verb.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC293 */ + 0x10ec0293, /* Vendor ID */ + 0x15581325, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15581325), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x02211020), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x02a11050), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x41738205), + AZALIA_PIN_CFG(0, 0x1e, 0x02451130), + /* Intel, KabylakeHDMI */ + 0x8086280b, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/system76/darp5/me b/system76/darp5/me new file mode 100644 index 0000000000..5657f3a7b3 Binary files /dev/null and b/system76/darp5/me differ diff --git a/system76/darp5/microcode b/system76/darp5/microcode new file mode 100644 index 0000000000..474ff6f815 Binary files /dev/null and b/system76/darp5/microcode differ diff --git a/system76/darp5/pxe b/system76/darp5/pxe new file mode 100644 index 0000000000..46e67afcf8 Binary files /dev/null and b/system76/darp5/pxe differ diff --git a/system76/darp5/vbt b/system76/darp5/vbt new file mode 100644 index 0000000000..df819a1076 Binary files /dev/null and b/system76/darp5/vbt differ diff --git a/system76/darp5/vga b/system76/darp5/vga new file mode 100644 index 0000000000..2306fd7a92 Binary files /dev/null and b/system76/darp5/vga differ diff --git a/system76/ec_query b/system76/ec_query new file mode 100644 index 0000000000..10b2fb3594 --- /dev/null +++ b/system76/ec_query @@ -0,0 +1,14 @@ +0x0a - touchpad toggle +0x0b - screen toggle +0x0c - mute +0x0e - volume down +0x0f - volume up +0x11 - brightness down +0x12 - brightness up +0x13 - camera toggle +0x14 - airplane mode +0x15 - suspend +0x16 - ac detect +0x1b - lid close +0x1c - thermal trip point +0x50 - WMI diff --git a/system76/ecflash b/system76/ecflash new file mode 100755 index 0000000000..bdc5853a60 Binary files /dev/null and b/system76/ecflash differ diff --git a/system76/ecflash.sh b/system76/ecflash.sh new file mode 100755 index 0000000000..c66fffec75 --- /dev/null +++ b/system76/ecflash.sh @@ -0,0 +1,18 @@ +#!/usr/bin/env bash + +set -ex + +D="$(dirname "$(realpath "$0")")" + +for N in "$@" +do + P="$D/$N" + if [ ! -d "$P" ] + then + echo "$0 [model]" + exit 1 + fi + + sudo "$D/ecflash" \ + "$P/ec" +done diff --git a/system76/flash.sh b/system76/flash.sh new file mode 100755 index 0000000000..1632843d31 --- /dev/null +++ b/system76/flash.sh @@ -0,0 +1,19 @@ +#!/usr/bin/env bash + +set -ex + +D="$(dirname "$(realpath "$0")")" + +for N in "$@" +do + P="$D/$N" + if [ ! -d "$P" ] + then + echo "$0 [model]" + exit 1 + fi + + sudo "$P/flashrom" \ + -p internal:laptop=force_I_want_a_brick \ + -w "$P/coreboot" +done diff --git a/system76/galp2/config b/system76/galp2/config new file mode 100644 index 0000000000..bd9af9fa5c --- /dev/null +++ b/system76/galp2/config @@ -0,0 +1,862 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +CONFIG_CCACHE=y +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +# CONFIG_NO_RELOCATABLE_RAMSTAGE is not set +CONFIG_RELOCATABLE_RAMSTAGE=y +CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM=y +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_ELMEX is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SCALEWAY is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_SUPERMICRO is not set +CONFIG_VENDOR_SYSTEM76=y +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="system76/kbl-u" +CONFIG_MAINBOARD_PART_NUMBER="galp2" +CONFIG_MAX_CPUS=8 +CONFIG_CBFS_SIZE=0x600000 +CONFIG_UART_FOR_CONSOLE=2 +CONFIG_PAYLOAD_CONFIGFILE="" +CONFIG_MAINBOARD_VENDOR="System76" +CONFIG_VGA_BIOS_ID="8086,5916" +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_DIMM_SPD_SIZE=512 +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_VGA_BIOS_FILE="system76/$(VARIANT_DIR)/vga" +CONFIG_C_ENV_BOOTBLOCK_SIZE=0xC000 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1558 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1303 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="System76" +CONFIG_VARIANT_DIR="galp2" +CONFIG_DEVICETREE="devicetree.cb" +CONFIG_INTEL_GMA_VBT_FILE="system76/$(VARIANT_DIR)/vbt" +CONFIG_POST_IO=y +CONFIG_DCACHE_RAM_BASE=0xfef00000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_OVERRIDE_DEVICETREE="" +CONFIG_ME_CLEANER_ARGS="-S" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 +CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 +CONFIG_HAVE_INTEL_FIRMWARE=y +# CONFIG_POST_DEVICE is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_VBOOT is not set +CONFIG_DIMM_MAX=2 +CONFIG_TPM_PIRQ=0x0 +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_TTYS0_LCS=3 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Galago Pro" +CONFIG_IFD_BIN_PATH="system76/$(VARIANT_DIR)/descriptor" +CONFIG_ME_BIN_PATH="system76/$(VARIANT_DIR)/me" +CONFIG_HAVE_IFD_BIN=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_M_FILE="$(obj)/Fsp_M.fd" +CONFIG_FSP_S_FILE="$(obj)/Fsp_S.fd" +CONFIG_FSP_S_CBFS="fsps.bin" +CONFIG_FSP_M_CBFS="fspm.bin" +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_MAINBOARD_VERSION="galp2" +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_SMBIOS_ENCLOSURE_TYPE=0x09 +CONFIG_BOARD_SYSTEM76_GALP2=y +# CONFIG_BOARD_SYSTEM76_GALP3 is not set +# CONFIG_BOARD_SYSTEM76_GALP3_B is not set +# CONFIG_BOARD_SYSTEM76_GALP3_C is not set +# CONFIG_BOARD_SYSTEM76_DARP5 is not set +CONFIG_CONSOLE_POST=y +CONFIG_PXE_ROM_ID="10ec,8168" +CONFIG_FSP_M_XIP=y +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y +# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set +CONFIG_POWER_STATE_ON_AFTER_FAILURE=y +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=1 +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_SYSTEM_TYPE_TABLET is not set +# CONFIG_SYSTEM_TYPE_DETACHABLE is not set +# CONFIG_SYSTEM_TYPE_CONVERTIBLE is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +CONFIG_CPU_SPECIFIC_OPTIONS=y +CONFIG_HEAP_SIZE=0x80000 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x200000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" +CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120 +# CONFIG_SOC_CAVIUM_CN81XX is not set +CONFIG_ARCH_ARMV8_EXTENSION=0 +CONFIG_STACK_SIZE=0x1000 +# CONFIG_SOC_CAVIUM_COMMON is not set +# CONFIG_SOC_INTEL_GLK is not set +CONFIG_PCR_BASE_ADDRESS=0xfd000000 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/" +CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" +# CONFIG_NHLT_MAX98357 is not set +# CONFIG_NHLT_DA7219 is not set +# CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS is not set +CONFIG_IFD_CHIPSET="sklkbl" +CONFIG_CPU_BCLK_MHZ=100 +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30 +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2 +CONFIG_SOC_INTEL_I2C_DEV_MAX=6 +# CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE is not set +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_TTYS0_BASE=0x3e8 +# CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE is not set +# CONFIG_SOC_INTEL_COFFEELAKE is not set +# CONFIG_SOC_INTEL_WHISKEYLAKE is not set +# CONFIG_SOC_INTEL_CANNONLAKE_PCH_H is not set +# CONFIG_NHLT_MAX98373 is not set +CONFIG_MAX_ROOT_PORTS=24 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_SOC_INTEL_SKYLAKE=y +CONFIG_SOC_INTEL_KABYLAKE=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10 +CONFIG_MAINBOARD_USES_FSP2_0=y +CONFIG_USE_FSP2_0_DRIVER=y +# CONFIG_EXCLUDE_NATIVE_SD_INTERFACE is not set +# CONFIG_SKYLAKE_SOC_PCH_H is not set +# CONFIG_NHLT_DMIC_2CH is not set +# CONFIG_NHLT_DMIC_4CH is not set +# CONFIG_NHLT_NAU88L25 is not set +# CONFIG_NHLT_SSM4567 is not set +# CONFIG_NHLT_RT5514 is not set +# CONFIG_NHLT_RT5663 is not set +# CONFIG_NHLT_MAX98927 is not set +# CONFIG_NO_FADT_8042 is not set +CONFIG_SOC_INTEL_COMMON=y + +# +# Intel SoC Common Code +# +CONFIG_SOC_INTEL_COMMON_BLOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y +# CONFIG_INTEL_CAR_NEM is not set +# CONFIG_INTEL_CAR_CQOS is not set +CONFIG_INTEL_CAR_NEM_ENHANCED=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y +CONFIG_SOC_INTEL_COMMON_BLOCK_EBDA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y +CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y +# CONFIG_PMC_INVALID_READ_AFTER_WRITE is not set +CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0 +CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y +CONFIG_SA_PCIEX_LENGTH=0x4000000 +CONFIG_PCIEX_LENGTH_64MB=y +# CONFIG_SA_ENABLE_IMR is not set +CONFIG_SA_ENABLE_DPR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y +CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_VMX is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y + +# +# Intel SoC Common PCH Code +# +CONFIG_SOC_INTEL_COMMON_PCH_BASE=y +CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y +CONFIG_PCH_SPECIFIC_OPTIONS=y + +# +# Intel SoC Common coreboot stages +# +# CONFIG_DISPLAY_SMM_MEMORY_MAP is not set +CONFIG_SOC_INTEL_COMMON_RESET=y +CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y +# CONFIG_ACPI_CONSOLE is not set +# CONFIG_MMA is not set +# CONFIG_SOC_INTEL_COMMON_ACPI is not set +# CONFIG_SOC_INTEL_COMMON_ACPI_EC_PTS_WAK is not set +CONFIG_SOC_INTEL_COMMON_NHLT=y +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_MEDIATEK_MT8183 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_QUALCOMM_SDM845 is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_SSE2=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_MICROCODE_UPDATE_PRE_RAM=y +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +CONFIG_PARALLEL_MP=y +CONFIG_PARALLEL_MP_AP_WORK=y +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_CONSTANT_RATE=y +CONFIG_TSC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_NO_FIXED_XIP_ROM_SIZE=y +CONFIG_LOGICAL_CPUS=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_MODULE_HEAP_SIZE=0x4000 +CONFIG_SMM_STUB_STACK_SIZE=0x400 +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_NO_CAR_GLOBAL_MIGRATION=y +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set + +# +# Super I/O +# +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +# CONFIG_EC_GOOGLE_WILCO is not set +CONFIG_EC_BASE_ACPI_DATA=0x930 +CONFIG_EC_BASE_ACPI_COMMAND=0x934 +CONFIG_EC_BASE_HOST_DATA=0x940 +CONFIG_EC_BASE_HOST_COMMAND=0x944 +CONFIG_EC_BASE_PACKET=0x950 +CONFIG_SEABIOS_PS2_TIMEOUT=0 + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +CONFIG_CHECK_ME=y +CONFIG_USE_ME_CLEANER=y + +# +# Please test the modified ME/TXE firmware and coreboot in two steps +# +# CONFIG_MAINBOARD_USES_IFD_GBE_REGION is not set +# CONFIG_MAINBOARD_USES_IFD_EC_REGION is not set +# CONFIG_CAVIUM_BDK is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set +# CONFIG_UEFI_2_4_BINDING is not set +CONFIG_UDK_2015_BINDING=y +# CONFIG_UDK_2017_BINDING is not set +CONFIG_UDK_2013_VERSION=2013 +CONFIG_UDK_2015_VERSION=2015 +CONFIG_UDK_2017_VERSION=2017 +CONFIG_UDK_VERSION=2015 +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_USE_ARCH_TIMER is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_PPC64 is not set +# CONFIG_ARCH_BOOTBLOCK_PPC64 is not set +# CONFIG_ARCH_VERSTAGE_PPC64 is not set +# CONFIG_ARCH_ROMSTAGE_PPC64 is not set +# CONFIG_ARCH_RAMSTAGE_PPC64 is not set +# CONFIG_ARCH_RISCV is not set +CONFIG_ARCH_RISCV_M=y +# CONFIG_ARCH_RISCV_S is not set +# CONFIG_ARCH_RISCV_U is not set +# CONFIG_ARCH_RISCV_RV64 is not set +# CONFIG_ARCH_RISCV_RV32 is not set +# CONFIG_ARCH_RISCV_PMP is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +# CONFIG_RISCV_USE_ARCH_TIMER is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_POSTCAR_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_RAMBASE=0xe00000 +CONFIG_RAMTOP=0x1000000 +# CONFIG_CBMEM_TOP_BACKUP is not set +CONFIG_EARLY_EBDA_INIT=y +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_HPET_ADDRESS_OVERRIDE is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POSTCAR_STAGE=y +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +# CONFIG_PAGING_IN_CACHE_AS_RAM is not set +# CONFIG_IDT_IN_EVERY_STAGE is not set +CONFIG_HAVE_CF9_RESET=y + +# +# Devices +# +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_HAVE_FSP_GOP=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +# CONFIG_VGA_ROM_RUN is not set +CONFIG_RUN_FSP_GOP=y +# CONFIG_NO_GFX_INIT is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +CONFIG_PCI=y +# CONFIG_NO_MMCONF_SUPPORT is not set +CONFIG_MMCONF_SUPPORT=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_ELOG is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +CONFIG_CACHE_MRC_SETTINGS=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_MRC_SETTINGS_PROTECT=y +# CONFIG_HAS_RECOVERY_MRC_CACHE is not set +# CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN is not set +# CONFIG_MRC_SETTINGS_VARIABLE_DATA is not set +# CONFIG_MRC_WRITE_NV_LATE is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +# CONFIG_SMMSTORE is not set +# CONFIG_SMMSTORE_IN_CBFS is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_TPM_INIT=y +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +# CONFIG_HAVE_USBDEBUG is not set +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_AMD_PI is not set +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +CONFIG_DRIVERS_I2C_DESIGNWARE=y +# CONFIG_DRIVERS_I2C_DESIGNWARE_DEBUG is not set +# CONFIG_DRIVERS_I2C_MAX98373 is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCA9538 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_DRIVERS_I2C_SX9310 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set +# CONFIG_DISPLAY_HOBS is not set +# CONFIG_DISPLAY_UPD_DATA is not set +CONFIG_PLATFORM_USES_FSP2_0=y +# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set +# CONFIG_DISPLAY_FSP_HEADER is not set +CONFIG_FSP_USE_REPO=y +# CONFIG_FSP_CAR is not set +# CONFIG_FSP_T_XIP is not set +# CONFIG_FSP_USES_CB_STACK is not set +# CONFIG_VERIFY_HOBS is not set +# CONFIG_DISPLAY_FSP_VERSION_INFO is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set +# CONFIG_INTEL_GMA_SWSMISCI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_LPC_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +CONFIG_MAINBOARD_HAS_LPC_TPM=y +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_USB_ACPI is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# + +# +# Trusted Platform Module +# +CONFIG_TPM2=y +CONFIG_MAINBOARD_HAS_TPM2=y +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3e8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +# CONFIG_HAVE_OPTION_TABLE is not set +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_COMMON_FADT=y +CONFIG_ACPI_NHLT=y + +# +# System tables +# +# CONFIG_GENERATE_MP_TABLE is not set +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_BAYOU is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_LINUXBOOT is not set +CONFIG_PAYLOAD_SEABIOS=y +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_YABITS is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf" +CONFIG_SEABIOS_STABLE=y +# CONFIG_SEABIOS_MASTER is not set +# CONFIG_SEABIOS_REVISION is not set +CONFIG_SEABIOS_THREAD_OPTIONROMS=y +CONFIG_SEABIOS_VGA_COREBOOT=y +CONFIG_SEABIOS_BOOTORDER_FILE="" +# CONFIG_SEABIOS_ADD_SERCON_PORT_FILE is not set +CONFIG_PAYLOAD_VGABIOS_FILE="payloads/external/SeaBIOS/seabios/out/vgabios.bin" +CONFIG_SEABIOS_DEBUG_LEVEL=-1 + +# +# Using default SeaBIOS log level +# +CONFIG_PAYLOAD_OPTIONS="" +CONFIG_PXE=y + +# +# PXE Options +# +CONFIG_PXE_ROM=y +# CONFIG_BUILD_IPXE is not set +CONFIG_PXE_ROM_FILE="system76/$(VARIANT_DIR)/pxe" +CONFIG_PXE_SERIAL_CONSOLE=y +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +# CONFIG_PAYLOAD_FIT_SUPPORT is not set +CONFIG_COMPRESS_SECONDARY_PAYLOAD=y + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# + +# +# CPU Debug Settings +# +CONFIG_HAVE_DISPLAY_MTRRS=y +# CONFIG_DISPLAY_MTRRS is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +CONFIG_HAVE_DEBUG_GPIO=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_CBFS is not set +# CONFIG_HAVE_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +CONFIG_NO_EDID_FILL_FB=y +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +CONFIG_REG_SCRIPT=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_GENERIC_GPIO_LIB=y +CONFIG_C_ENVIRONMENT_BOOTBLOCK=y diff --git a/system76/galp2/coreboot b/system76/galp2/coreboot new file mode 100644 index 0000000000..a5a0e62960 Binary files /dev/null and b/system76/galp2/coreboot differ diff --git a/system76/galp2/coreboot-collector b/system76/galp2/coreboot-collector new file mode 100644 index 0000000000..9da7ed7df4 --- /dev/null +++ b/system76/galp2/coreboot-collector @@ -0,0 +1,211 @@ +## PCI ## +PCI Device: 0000:00:00.0: Class 0x00060000, Vendor 0x8086, Device 0x5904, Revision 0x02 +PCI Device: 0000:00:02.0: Class 0x00030000, Vendor 0x8086, Device 0x5916, Revision 0x02 +PCI Device: 0000:00:08.0: Class 0x00088000, Vendor 0x8086, Device 0x1911, Revision 0x00 +PCI Device: 0000:00:14.0: Class 0x000C0330, Vendor 0x8086, Device 0x9D2F, Revision 0x21 +PCI Device: 0000:00:14.2: Class 0x00118000, Vendor 0x8086, Device 0x9D31, Revision 0x21 +PCI Device: 0000:00:17.0: Class 0x00010601, Vendor 0x8086, Device 0x9D03, Revision 0x21 +PCI Device: 0000:00:1c.0: Class 0x00060400, Vendor 0x8086, Device 0x9D10, Revision 0xF1 +PCI Device: 0000:00:1c.4: Class 0x00060400, Vendor 0x8086, Device 0x9D14, Revision 0xF1 +PCI Device: 0000:00:1c.5: Class 0x00060400, Vendor 0x8086, Device 0x9D15, Revision 0xF1 +PCI Device: 0000:00:1d.0: Class 0x00060400, Vendor 0x8086, Device 0x9D18, Revision 0xF1 +PCI Device: 0000:00:1f.0: Class 0x00060100, Vendor 0x8086, Device 0x9D4E, Revision 0x21 +PCI Device: 0000:00:1f.2: Class 0x00058000, Vendor 0x8086, Device 0x9D21, Revision 0x21 +PCI Device: 0000:00:1f.3: Class 0x00040300, Vendor 0x8086, Device 0x9D71, Revision 0x21 +PCI Device: 0000:00:1f.4: Class 0x000C0500, Vendor 0x8086, Device 0x9D23, Revision 0x21 +PCI Device: 0000:3a:00.0: Class 0x00FF0000, Vendor 0x10EC, Device 0x5287, Revision 0x01 +PCI Device: 0000:3a:00.1: Class 0x00020000, Vendor 0x10EC, Device 0x8168, Revision 0x12 +PCI Device: 0000:3b:00.0: Class 0x00028000, Vendor 0x8086, Device 0x24FB, Revision 0x10 +PCI Device: 0000:3c:00.0: Class 0x00010802, Vendor 0x1B85, Device 0x6018, Revision 0x01 +## GPIO ## +100 Series PCH-LP +GPP_A0 = 0x44000502 0x00000018 +GPP_A1 = 0x44000402 0x00000019 +GPP_A2 = 0x44000402 0x0000001a +GPP_A3 = 0x44000402 0x0000001b +GPP_A4 = 0x44000402 0x0000001c +GPP_A5 = 0x44000600 0x0000001d +GPP_A6 = 0x44000402 0x0000001e +GPP_A7 = 0x44000102 0x0000001f +GPP_A8 = 0x44000700 0x00000020 +GPP_A9 = 0x44000600 0x00000021 +GPP_A10 = 0x44000600 0x00001022 +GPP_A11 = 0x44000200 0x00000023 +GPP_A12 = 0x44000200 0x00000024 +GPP_A13 = 0x44000200 0x00000025 +GPP_A14 = 0x44000600 0x00000026 +GPP_A15 = 0x44000502 0x00000027 +GPP_A16 = 0x44000200 0x00000028 +GPP_A17 = 0x44000200 0x00000029 +GPP_A18 = 0x44000201 0x0000002a +GPP_A19 = 0x44000603 0x0000002b +GPP_A20 = 0x44000200 0x0000002c +GPP_A21 = 0x84000200 0x0000102d +GPP_A22 = 0x04000200 0x0000002e +GPP_A23 = 0x04000200 0x0000002f +GPP_B0 = 0x44000700 0x00000030 +GPP_B1 = 0x44000700 0x00000031 +GPP_B2 = 0x44000200 0x00000032 +GPP_B3 = 0x44000200 0x00000033 +GPP_B4 = 0x44000200 0x00000034 +GPP_B5 = 0x44000200 0x00000035 +GPP_B6 = 0x44000200 0x00000036 +GPP_B7 = 0x44000702 0x00000037 +GPP_B8 = 0x44000700 0x00000038 +GPP_B9 = 0x44000702 0x00000039 +GPP_B10 = 0x44000700 0x0000003a +GPP_B11 = 0x44000700 0x0000003b +GPP_B12 = 0x44000200 0x0000003c +GPP_B13 = 0x44000700 0x0000003d +GPP_B14 = 0x44000600 0x0000103e +GPP_B15 = 0x44000200 0x0000003f +GPP_B16 = 0x44000200 0x00000040 +GPP_B17 = 0x44000200 0x00000041 +GPP_B18 = 0x44000600 0x00003042 +GPP_B19 = 0x44000200 0x00000043 +GPP_B20 = 0x44000200 0x00000044 +GPP_B21 = 0x44000200 0x00000045 +GPP_B22 = 0x44000700 0x00001046 +GPP_B23 = 0x44000200 0x00000047 +GPP_C0 = 0x44000702 0x00000048 +GPP_C1 = 0x44000702 0x00001049 +GPP_C2 = 0x44000201 0x0000104a +GPP_C3 = 0x44000200 0x0000004b +GPP_C4 = 0x44000200 0x0000004c +GPP_C5 = 0x44000200 0x0000004d +GPP_C6 = 0xffffffff 0xffffffff +GPP_C7 = 0xffffffff 0xffffffff +GPP_C8 = 0x44000702 0x00000050 +GPP_C9 = 0x44000700 0x00000051 +GPP_C10 = 0x44000700 0x00000052 +GPP_C11 = 0x44000702 0x00000053 +GPP_C12 = 0x44000702 0x00000054 +GPP_C13 = 0x82880102 0x00000055 +GPP_C14 = 0x44000700 0x00000056 +GPP_C15 = 0x44000702 0x00000057 +GPP_C16 = 0x44000200 0x00000058 +GPP_C17 = 0x44000200 0x00000059 +GPP_C18 = 0x44000200 0x0000005a +GPP_C19 = 0x40880102 0x0000005b +GPP_C20 = 0x44000702 0x0000005c +GPP_C21 = 0x44000700 0x0000005d +GPP_C22 = 0x44000700 0x0000005e +GPP_C23 = 0x44000702 0x0000005f +GPP_D0 = 0x44000200 0x00000060 +GPP_D1 = 0x44000200 0x00000061 +GPP_D2 = 0x44000200 0x00000062 +GPP_D3 = 0x44000200 0x00000063 +GPP_D4 = 0x44000200 0x00000064 +GPP_D5 = 0x44000702 0x00000065 +GPP_D6 = 0x44000702 0x00000066 +GPP_D7 = 0x44000700 0x00000067 +GPP_D8 = 0x44000201 0x00000068 +GPP_D9 = 0x44000200 0x00000069 +GPP_D10 = 0x44000200 0x0000006a +GPP_D11 = 0x44000200 0x0000006b +GPP_D12 = 0x44000200 0x0000006c +GPP_D13 = 0x44000200 0x0000006d +GPP_D14 = 0x44000200 0x0000006e +GPP_D15 = 0x44000700 0x0000006f +GPP_D16 = 0x44000702 0x00000070 +GPP_D17 = 0x44000700 0x00000071 +GPP_D18 = 0x44000700 0x00000072 +GPP_D19 = 0x44000700 0x00000073 +GPP_D20 = 0x44000700 0x00000074 +GPP_D21 = 0x44000100 0x00000075 +GPP_D22 = 0x44000700 0x00000076 +GPP_D23 = 0x44000700 0x00000077 +GPP_E0 = 0x42100100 0x00001018 +GPP_E1 = 0x44000702 0x00000019 +GPP_E2 = 0x44000502 0x0000001a +GPP_E3 = 0x40000000 0x0000001b +GPP_E4 = 0x04000700 0x0000001c +GPP_E5 = 0x04000700 0x0000001d +GPP_E6 = 0x44000200 0x0000001e +GPP_E7 = 0x44000100 0x0000001f +GPP_E8 = 0x44000700 0x00000020 +GPP_E9 = 0x44000200 0x00000021 +GPP_E10 = 0x44000200 0x00000022 +GPP_E11 = 0x44000200 0x00000023 +GPP_E12 = 0x44000200 0x00000024 +GPP_E13 = 0x44000700 0x00000025 +GPP_E14 = 0x44000700 0x00000026 +GPP_E15 = 0x42840102 0x00000027 +GPP_E16 = 0x80880102 0x00000028 +GPP_E17 = 0x44000702 0x00000029 +GPP_E18 = 0x44000702 0x0000002a +GPP_E19 = 0x44000702 0x0000102b +GPP_E20 = 0x44000702 0x0000002c +GPP_E21 = 0x44000702 0x0000102d +GPP_E22 = 0x40100000 0x0000002e +GPP_E23 = 0x44000201 0x0000102f +GPD0 = 0x04000702 0x00000050 +GPD1 = 0x04000702 0x00000051 +GPD2 = 0x00880502 0x00000052 +GPD3 = 0x04000702 0x00003053 +GPD4 = 0x04000700 0x00000054 +GPD5 = 0x04000700 0x00000055 +GPD6 = 0x04000700 0x00000056 +GPD7 = 0x04000301 0x00000057 +GPD8 = 0x04000700 0x00000058 +GPD9 = 0x04000700 0x00000059 +GPD10 = 0x04000700 0x0000005a +GPD11 = 0x04000500 0x0000005b +GPP_F0 = 0x44000700 0x00000030 +GPP_F1 = 0x44000702 0x00000031 +GPP_F2 = 0x44000700 0x00000032 +GPP_F3 = 0x44000700 0x00000033 +GPP_F4 = 0x44000702 0x02000034 +GPP_F5 = 0x44000702 0x02000035 +GPP_F6 = 0x44000702 0x02000036 +GPP_F7 = 0x44000702 0x02000037 +GPP_F8 = 0x44000702 0x02000038 +GPP_F9 = 0x44000702 0x02000039 +GPP_F10 = 0x44000b02 0x0200003a +GPP_F11 = 0x44000b02 0x0200003b +GPP_F12 = 0x44000702 0x0000003c +GPP_F13 = 0x44000702 0x0000003d +GPP_F14 = 0x44000702 0x0000003e +GPP_F15 = 0x44000702 0x0000003f +GPP_F16 = 0x44000702 0x00000040 +GPP_F17 = 0x44000700 0x00000041 +GPP_F18 = 0x44000700 0x00000042 +GPP_F19 = 0x44000702 0x00000043 +GPP_F20 = 0x44000700 0x00000044 +GPP_F21 = 0x44000700 0x00000045 +GPP_F22 = 0x44000700 0x00000046 +GPP_F23 = 0x40100102 0x00000047 +GPP_G0 = 0x44000700 0x00000048 +GPP_G1 = 0x44000102 0x00000049 +GPP_G2 = 0x44000700 0x0000004a +GPP_G3 = 0x44000700 0x0000004b +GPP_G4 = 0x44000700 0x0000004c +GPP_G5 = 0x44000702 0x0000004d +GPP_G6 = 0x44000700 0x0000004e +GPP_G7 = 0x44000702 0x0000004f +## HDAUDIO ## +hdaudioC0D0 + vendor_name: Realtek + chip_name: ALC269VC + vendor_id: 0x10ec0269 + subsystem_id: 0x15581303 + revision_id: 0x100202 + 0x12: 0x90a60140 + 0x14: 0x90170120 + 0x15: 0x02211010 + 0x17: 0x40000000 + 0x18: 0x02a11030 + 0x19: 0x411111f0 + 0x1a: 0x411111f0 + 0x1b: 0x411111f0 + 0x1d: 0x40f4a205 + 0x1e: 0x411111f0 +hdaudioC0D2 + vendor_name: Intel + chip_name: Kabylake HDMI + vendor_id: 0x8086280b + subsystem_id: 0x80860101 + revision_id: 0x100000 + 0x05: 0x18560010 + 0x06: 0x18560010 + 0x07: 0x18560010 diff --git a/system76/galp2/descriptor b/system76/galp2/descriptor new file mode 100644 index 0000000000..91d587336e Binary files /dev/null and b/system76/galp2/descriptor differ diff --git a/system76/galp2/flashrom b/system76/galp2/flashrom new file mode 100755 index 0000000000..46d0c94f75 Binary files /dev/null and b/system76/galp2/flashrom differ diff --git a/system76/galp2/gpio.h b/system76/galp2/gpio.h new file mode 100644 index 0000000000..ea1dc6e2af --- /dev/null +++ b/system76/galp2/gpio.h @@ -0,0 +1,194 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include +#include + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + _PAD_CFG_STRUCT(GPD0, 0x4000700, 0x0), + _PAD_CFG_STRUCT(GPD1, 0x4000700, 0x0), + _PAD_CFG_STRUCT(GPD2, 0x880500, 0x0), + _PAD_CFG_STRUCT(GPD3, 0x4000700, 0x3000), + _PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), + _PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), + _PAD_CFG_STRUCT(GPD6, 0x4000700, 0x0), + _PAD_CFG_STRUCT(GPD7, 0x4000301, 0x0), + _PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), + _PAD_CFG_STRUCT(GPD9, 0x4000700, 0x0), + _PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0), + _PAD_CFG_STRUCT(GPD11, 0x4000500, 0x0), + _PAD_CFG_STRUCT(GPP_A0, 0x44000500, 0x0), + _PAD_CFG_STRUCT(GPP_A1, 0x44000400, 0x0), + _PAD_CFG_STRUCT(GPP_A2, 0x44000400, 0x0), + _PAD_CFG_STRUCT(GPP_A3, 0x44000400, 0x0), + _PAD_CFG_STRUCT(GPP_A4, 0x44000400, 0x0), + _PAD_CFG_STRUCT(GPP_A5, 0x44000600, 0x0), + _PAD_CFG_STRUCT(GPP_A6, 0x44000400, 0x0), + _PAD_CFG_STRUCT(GPP_A7, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_A9, 0x44000600, 0x0), + _PAD_CFG_STRUCT(GPP_A10, 0x44000600, 0x1000), + _PAD_CFG_STRUCT(GPP_A11, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_A12, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_A13, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_A14, 0x44000600, 0x0), + _PAD_CFG_STRUCT(GPP_A15, 0x44000500, 0x0), + _PAD_CFG_STRUCT(GPP_A16, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_A17, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_A18, 0x44000201, 0x0), + _PAD_CFG_STRUCT(GPP_A19, 0x44000601, 0x0), + _PAD_CFG_STRUCT(GPP_A20, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_A21, 0x84000200, 0x1000), + _PAD_CFG_STRUCT(GPP_A22, 0x4000200, 0x0), + _PAD_CFG_STRUCT(GPP_A23, 0x4000200, 0x0), + _PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B2, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B3, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B4, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B5, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B6, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B7, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B8, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B10, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B12, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B14, 0x44000600, 0x1000), + _PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B16, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B17, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B18, 0x44000600, 0x3000), + _PAD_CFG_STRUCT(GPP_B19, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B20, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B21, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), + _PAD_CFG_STRUCT(GPP_B23, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_C0, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C1, 0x44000700, 0x1000), + _PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), + _PAD_CFG_STRUCT(GPP_C3, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_C4, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_C5, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_C6, 0xfffffffd, 0xffffff00), + _PAD_CFG_STRUCT(GPP_C7, 0xfffffffd, 0xffffff00), + _PAD_CFG_STRUCT(GPP_C8, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C11, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C12, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C13, 0x82880100, 0x0), + _PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C15, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C16, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_C17, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_C18, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_C19, 0x40880100, 0x0), + _PAD_CFG_STRUCT(GPP_C20, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C23, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_D0, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_D1, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_D2, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_D3, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_D4, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_D5, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_D6, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_D7, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_D8, 0x44000201, 0x0), + _PAD_CFG_STRUCT(GPP_D9, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_D10, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_D11, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_D12, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_D13, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_D14, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_D16, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_D21, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E0, 0x42100100, 0x1000), + _PAD_CFG_STRUCT(GPP_E1, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E2, 0x44000500, 0x0), + _PAD_CFG_STRUCT(GPP_E3, 0x40000000, 0x0), + _PAD_CFG_STRUCT(GPP_E4, 0x4000700, 0x0), + _PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0), + _PAD_CFG_STRUCT(GPP_E6, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_E7, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E9, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_E10, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_E11, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_E12, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0), + _PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0), + _PAD_CFG_STRUCT(GPP_E17, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), + _PAD_CFG_STRUCT(GPP_E20, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E21, 0x44000700, 0x1000), + _PAD_CFG_STRUCT(GPP_E22, 0x40100000, 0x0), + _PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), + _PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F4, 0x44000700, 0x2000000), + _PAD_CFG_STRUCT(GPP_F5, 0x44000700, 0x2000000), + _PAD_CFG_STRUCT(GPP_F6, 0x44000700, 0x2000000), + _PAD_CFG_STRUCT(GPP_F7, 0x44000700, 0x2000000), + _PAD_CFG_STRUCT(GPP_F8, 0x44000700, 0x2000000), + _PAD_CFG_STRUCT(GPP_F9, 0x44000700, 0x2000000), + _PAD_CFG_STRUCT(GPP_F10, 0x44000b00, 0x2000000), + _PAD_CFG_STRUCT(GPP_F11, 0x44000b00, 0x2000000), + _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F14, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F17, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F18, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0), + _PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_G5, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_G7, 0x44000700, 0x0), +}; + +#endif + +#endif diff --git a/system76/galp2/hda_verb.c b/system76/galp2/hda_verb.c new file mode 100644 index 0000000000..23ce3e9f0e --- /dev/null +++ b/system76/galp2/hda_verb.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC269VC */ + 0x10ec0269, /* Vendor ID */ + 0x15581303, /* Subsystem ID */ + 11, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15581303), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x14, 0x90170120), + AZALIA_PIN_CFG(0, 0x15, 0x02211010), + AZALIA_PIN_CFG(0, 0x17, 0x40000000), + AZALIA_PIN_CFG(0, 0x18, 0x02a11030), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40f4a205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + /* Intel, KabylakeHDMI */ + 0x8086280b, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/system76/galp2/me b/system76/galp2/me new file mode 100644 index 0000000000..1d0148cb73 Binary files /dev/null and b/system76/galp2/me differ diff --git a/system76/galp2/pxe b/system76/galp2/pxe new file mode 100644 index 0000000000..46e67afcf8 Binary files /dev/null and b/system76/galp2/pxe differ diff --git a/system76/galp2/vbt b/system76/galp2/vbt new file mode 100644 index 0000000000..b7d91b19ea Binary files /dev/null and b/system76/galp2/vbt differ diff --git a/system76/galp2/vga b/system76/galp2/vga new file mode 100644 index 0000000000..7ea06f4a85 Binary files /dev/null and b/system76/galp2/vga differ diff --git a/system76/galp3-b/chip b/system76/galp3-b/chip new file mode 100644 index 0000000000..de2966cbad --- /dev/null +++ b/system76/galp3-b/chip @@ -0,0 +1 @@ +MX25L6405D diff --git a/system76/galp3-b/config b/system76/galp3-b/config new file mode 100644 index 0000000000..2a7ac33668 --- /dev/null +++ b/system76/galp3-b/config @@ -0,0 +1,862 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +CONFIG_CCACHE=y +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +# CONFIG_NO_RELOCATABLE_RAMSTAGE is not set +CONFIG_RELOCATABLE_RAMSTAGE=y +CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM=y +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_ELMEX is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SCALEWAY is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_SUPERMICRO is not set +CONFIG_VENDOR_SYSTEM76=y +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="system76/kbl-u" +CONFIG_MAINBOARD_PART_NUMBER="galp3-b" +CONFIG_MAX_CPUS=8 +CONFIG_CBFS_SIZE=0x600000 +CONFIG_UART_FOR_CONSOLE=2 +CONFIG_PAYLOAD_CONFIGFILE="" +CONFIG_MAINBOARD_VENDOR="System76" +CONFIG_VGA_BIOS_ID="8086,5917" +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_DIMM_SPD_SIZE=512 +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_VGA_BIOS_FILE="system76/$(VARIANT_DIR)/vga" +CONFIG_C_ENV_BOOTBLOCK_SIZE=0xC000 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1558 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1413 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="System76" +CONFIG_VARIANT_DIR="galp3-b" +CONFIG_DEVICETREE="devicetree.cb" +CONFIG_INTEL_GMA_VBT_FILE="system76/$(VARIANT_DIR)/vbt" +CONFIG_POST_IO=y +CONFIG_DCACHE_RAM_BASE=0xfef00000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_OVERRIDE_DEVICETREE="" +CONFIG_ME_CLEANER_ARGS="-S" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 +CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 +CONFIG_HAVE_INTEL_FIRMWARE=y +# CONFIG_POST_DEVICE is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_VBOOT is not set +CONFIG_DIMM_MAX=2 +CONFIG_TPM_PIRQ=0x0 +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_TTYS0_LCS=3 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Galago Pro" +CONFIG_IFD_BIN_PATH="system76/$(VARIANT_DIR)/descriptor" +CONFIG_ME_BIN_PATH="system76/$(VARIANT_DIR)/me" +CONFIG_HAVE_IFD_BIN=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_M_FILE="$(obj)/Fsp_M.fd" +CONFIG_FSP_S_FILE="$(obj)/Fsp_S.fd" +CONFIG_FSP_S_CBFS="fsps.bin" +CONFIG_FSP_M_CBFS="fspm.bin" +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_MAINBOARD_VERSION="galp3-b" +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_SMBIOS_ENCLOSURE_TYPE=0x09 +# CONFIG_BOARD_SYSTEM76_GALP2 is not set +# CONFIG_BOARD_SYSTEM76_GALP3 is not set +CONFIG_BOARD_SYSTEM76_GALP3_B=y +# CONFIG_BOARD_SYSTEM76_GALP3_C is not set +# CONFIG_BOARD_SYSTEM76_DARP5 is not set +CONFIG_CONSOLE_POST=y +CONFIG_PXE_ROM_ID="10ec,8168" +CONFIG_FSP_M_XIP=y +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y +# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set +CONFIG_POWER_STATE_ON_AFTER_FAILURE=y +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=1 +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_SYSTEM_TYPE_TABLET is not set +# CONFIG_SYSTEM_TYPE_DETACHABLE is not set +# CONFIG_SYSTEM_TYPE_CONVERTIBLE is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +CONFIG_CPU_SPECIFIC_OPTIONS=y +CONFIG_HEAP_SIZE=0x80000 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x200000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" +CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120 +# CONFIG_SOC_CAVIUM_CN81XX is not set +CONFIG_ARCH_ARMV8_EXTENSION=0 +CONFIG_STACK_SIZE=0x1000 +# CONFIG_SOC_CAVIUM_COMMON is not set +# CONFIG_SOC_INTEL_GLK is not set +CONFIG_PCR_BASE_ADDRESS=0xfd000000 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/" +CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" +# CONFIG_NHLT_MAX98357 is not set +# CONFIG_NHLT_DA7219 is not set +# CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS is not set +CONFIG_IFD_CHIPSET="sklkbl" +CONFIG_CPU_BCLK_MHZ=100 +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30 +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2 +CONFIG_SOC_INTEL_I2C_DEV_MAX=6 +# CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE is not set +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_TTYS0_BASE=0x3e8 +# CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE is not set +# CONFIG_SOC_INTEL_COFFEELAKE is not set +# CONFIG_SOC_INTEL_WHISKEYLAKE is not set +# CONFIG_SOC_INTEL_CANNONLAKE_PCH_H is not set +# CONFIG_NHLT_MAX98373 is not set +CONFIG_MAX_ROOT_PORTS=24 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_SOC_INTEL_SKYLAKE=y +CONFIG_SOC_INTEL_KABYLAKE=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10 +CONFIG_MAINBOARD_USES_FSP2_0=y +CONFIG_USE_FSP2_0_DRIVER=y +# CONFIG_EXCLUDE_NATIVE_SD_INTERFACE is not set +# CONFIG_SKYLAKE_SOC_PCH_H is not set +# CONFIG_NHLT_DMIC_2CH is not set +# CONFIG_NHLT_DMIC_4CH is not set +# CONFIG_NHLT_NAU88L25 is not set +# CONFIG_NHLT_SSM4567 is not set +# CONFIG_NHLT_RT5514 is not set +# CONFIG_NHLT_RT5663 is not set +# CONFIG_NHLT_MAX98927 is not set +# CONFIG_NO_FADT_8042 is not set +CONFIG_SOC_INTEL_COMMON=y + +# +# Intel SoC Common Code +# +CONFIG_SOC_INTEL_COMMON_BLOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y +# CONFIG_INTEL_CAR_NEM is not set +# CONFIG_INTEL_CAR_CQOS is not set +CONFIG_INTEL_CAR_NEM_ENHANCED=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y +CONFIG_SOC_INTEL_COMMON_BLOCK_EBDA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y +CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y +# CONFIG_PMC_INVALID_READ_AFTER_WRITE is not set +CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0 +CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y +CONFIG_SA_PCIEX_LENGTH=0x4000000 +CONFIG_PCIEX_LENGTH_64MB=y +# CONFIG_SA_ENABLE_IMR is not set +CONFIG_SA_ENABLE_DPR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y +CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_VMX is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y + +# +# Intel SoC Common PCH Code +# +CONFIG_SOC_INTEL_COMMON_PCH_BASE=y +CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y +CONFIG_PCH_SPECIFIC_OPTIONS=y + +# +# Intel SoC Common coreboot stages +# +# CONFIG_DISPLAY_SMM_MEMORY_MAP is not set +CONFIG_SOC_INTEL_COMMON_RESET=y +CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y +# CONFIG_ACPI_CONSOLE is not set +# CONFIG_MMA is not set +# CONFIG_SOC_INTEL_COMMON_ACPI is not set +# CONFIG_SOC_INTEL_COMMON_ACPI_EC_PTS_WAK is not set +CONFIG_SOC_INTEL_COMMON_NHLT=y +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_MEDIATEK_MT8183 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_QUALCOMM_SDM845 is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_SSE2=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_MICROCODE_UPDATE_PRE_RAM=y +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +CONFIG_PARALLEL_MP=y +CONFIG_PARALLEL_MP_AP_WORK=y +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_CONSTANT_RATE=y +CONFIG_TSC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_NO_FIXED_XIP_ROM_SIZE=y +CONFIG_LOGICAL_CPUS=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_MODULE_HEAP_SIZE=0x4000 +CONFIG_SMM_STUB_STACK_SIZE=0x400 +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_NO_CAR_GLOBAL_MIGRATION=y +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set + +# +# Super I/O +# +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +# CONFIG_EC_GOOGLE_WILCO is not set +CONFIG_EC_BASE_ACPI_DATA=0x930 +CONFIG_EC_BASE_ACPI_COMMAND=0x934 +CONFIG_EC_BASE_HOST_DATA=0x940 +CONFIG_EC_BASE_HOST_COMMAND=0x944 +CONFIG_EC_BASE_PACKET=0x950 +CONFIG_SEABIOS_PS2_TIMEOUT=0 + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +CONFIG_CHECK_ME=y +CONFIG_USE_ME_CLEANER=y + +# +# Please test the modified ME/TXE firmware and coreboot in two steps +# +# CONFIG_MAINBOARD_USES_IFD_GBE_REGION is not set +# CONFIG_MAINBOARD_USES_IFD_EC_REGION is not set +# CONFIG_CAVIUM_BDK is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set +# CONFIG_UEFI_2_4_BINDING is not set +CONFIG_UDK_2015_BINDING=y +# CONFIG_UDK_2017_BINDING is not set +CONFIG_UDK_2013_VERSION=2013 +CONFIG_UDK_2015_VERSION=2015 +CONFIG_UDK_2017_VERSION=2017 +CONFIG_UDK_VERSION=2015 +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_USE_ARCH_TIMER is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_PPC64 is not set +# CONFIG_ARCH_BOOTBLOCK_PPC64 is not set +# CONFIG_ARCH_VERSTAGE_PPC64 is not set +# CONFIG_ARCH_ROMSTAGE_PPC64 is not set +# CONFIG_ARCH_RAMSTAGE_PPC64 is not set +# CONFIG_ARCH_RISCV is not set +CONFIG_ARCH_RISCV_M=y +# CONFIG_ARCH_RISCV_S is not set +# CONFIG_ARCH_RISCV_U is not set +# CONFIG_ARCH_RISCV_RV64 is not set +# CONFIG_ARCH_RISCV_RV32 is not set +# CONFIG_ARCH_RISCV_PMP is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +# CONFIG_RISCV_USE_ARCH_TIMER is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_POSTCAR_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_RAMBASE=0xe00000 +CONFIG_RAMTOP=0x1000000 +# CONFIG_CBMEM_TOP_BACKUP is not set +CONFIG_EARLY_EBDA_INIT=y +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_HPET_ADDRESS_OVERRIDE is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POSTCAR_STAGE=y +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +# CONFIG_PAGING_IN_CACHE_AS_RAM is not set +# CONFIG_IDT_IN_EVERY_STAGE is not set +CONFIG_HAVE_CF9_RESET=y + +# +# Devices +# +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_HAVE_FSP_GOP=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +# CONFIG_VGA_ROM_RUN is not set +CONFIG_RUN_FSP_GOP=y +# CONFIG_NO_GFX_INIT is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +CONFIG_PCI=y +# CONFIG_NO_MMCONF_SUPPORT is not set +CONFIG_MMCONF_SUPPORT=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_ELOG is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +CONFIG_CACHE_MRC_SETTINGS=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_MRC_SETTINGS_PROTECT=y +# CONFIG_HAS_RECOVERY_MRC_CACHE is not set +# CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN is not set +# CONFIG_MRC_SETTINGS_VARIABLE_DATA is not set +# CONFIG_MRC_WRITE_NV_LATE is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +# CONFIG_SMMSTORE is not set +# CONFIG_SMMSTORE_IN_CBFS is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_TPM_INIT=y +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +# CONFIG_HAVE_USBDEBUG is not set +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_AMD_PI is not set +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +CONFIG_DRIVERS_I2C_DESIGNWARE=y +# CONFIG_DRIVERS_I2C_DESIGNWARE_DEBUG is not set +# CONFIG_DRIVERS_I2C_MAX98373 is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCA9538 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_DRIVERS_I2C_SX9310 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set +# CONFIG_DISPLAY_HOBS is not set +# CONFIG_DISPLAY_UPD_DATA is not set +CONFIG_PLATFORM_USES_FSP2_0=y +# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set +# CONFIG_DISPLAY_FSP_HEADER is not set +CONFIG_FSP_USE_REPO=y +# CONFIG_FSP_CAR is not set +# CONFIG_FSP_T_XIP is not set +# CONFIG_FSP_USES_CB_STACK is not set +# CONFIG_VERIFY_HOBS is not set +# CONFIG_DISPLAY_FSP_VERSION_INFO is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set +# CONFIG_INTEL_GMA_SWSMISCI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_LPC_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +CONFIG_MAINBOARD_HAS_LPC_TPM=y +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_USB_ACPI is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# + +# +# Trusted Platform Module +# +CONFIG_TPM2=y +CONFIG_MAINBOARD_HAS_TPM2=y +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3e8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +# CONFIG_HAVE_OPTION_TABLE is not set +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_COMMON_FADT=y +CONFIG_ACPI_NHLT=y + +# +# System tables +# +# CONFIG_GENERATE_MP_TABLE is not set +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_BAYOU is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_LINUXBOOT is not set +CONFIG_PAYLOAD_SEABIOS=y +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_YABITS is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf" +CONFIG_SEABIOS_STABLE=y +# CONFIG_SEABIOS_MASTER is not set +# CONFIG_SEABIOS_REVISION is not set +CONFIG_SEABIOS_THREAD_OPTIONROMS=y +CONFIG_SEABIOS_VGA_COREBOOT=y +CONFIG_SEABIOS_BOOTORDER_FILE="" +# CONFIG_SEABIOS_ADD_SERCON_PORT_FILE is not set +CONFIG_PAYLOAD_VGABIOS_FILE="payloads/external/SeaBIOS/seabios/out/vgabios.bin" +CONFIG_SEABIOS_DEBUG_LEVEL=-1 + +# +# Using default SeaBIOS log level +# +CONFIG_PAYLOAD_OPTIONS="" +CONFIG_PXE=y + +# +# PXE Options +# +CONFIG_PXE_ROM=y +# CONFIG_BUILD_IPXE is not set +CONFIG_PXE_ROM_FILE="system76/$(VARIANT_DIR)/pxe" +CONFIG_PXE_SERIAL_CONSOLE=y +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +# CONFIG_PAYLOAD_FIT_SUPPORT is not set +CONFIG_COMPRESS_SECONDARY_PAYLOAD=y + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# + +# +# CPU Debug Settings +# +CONFIG_HAVE_DISPLAY_MTRRS=y +# CONFIG_DISPLAY_MTRRS is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +CONFIG_HAVE_DEBUG_GPIO=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_CBFS is not set +# CONFIG_HAVE_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +CONFIG_NO_EDID_FILL_FB=y +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +CONFIG_REG_SCRIPT=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_GENERIC_GPIO_LIB=y +CONFIG_C_ENVIRONMENT_BOOTBLOCK=y diff --git a/system76/galp3-b/coreboot b/system76/galp3-b/coreboot new file mode 100644 index 0000000000..250ffd4a45 Binary files /dev/null and b/system76/galp3-b/coreboot differ diff --git a/system76/galp3-b/coreboot-collector b/system76/galp3-b/coreboot-collector new file mode 100644 index 0000000000..9bde70d6f8 --- /dev/null +++ b/system76/galp3-b/coreboot-collector @@ -0,0 +1,209 @@ +## PCI ## +PCI Device: 0000:00:00.0: Class 0x00060000, Vendor 0x8086, Device 0x5914, Revision 0x08 +PCI Device: 0000:00:02.0: Class 0x00030000, Vendor 0x8086, Device 0x5917, Revision 0x07 +PCI Device: 0000:00:14.0: Class 0x000C0330, Vendor 0x8086, Device 0x9D2F, Revision 0x21 +PCI Device: 0000:00:14.2: Class 0x00118000, Vendor 0x8086, Device 0x9D31, Revision 0x21 +PCI Device: 0000:00:16.0: Class 0x00078000, Vendor 0x8086, Device 0x9D3A, Revision 0x21 +PCI Device: 0000:00:17.0: Class 0x00010601, Vendor 0x8086, Device 0x9D03, Revision 0x21 +PCI Device: 0000:00:1c.0: Class 0x00060400, Vendor 0x8086, Device 0x9D10, Revision 0xF1 +PCI Device: 0000:00:1c.4: Class 0x00060400, Vendor 0x8086, Device 0x9D14, Revision 0xF1 +PCI Device: 0000:00:1c.5: Class 0x00060400, Vendor 0x8086, Device 0x9D15, Revision 0xF1 +PCI Device: 0000:00:1f.0: Class 0x00060100, Vendor 0x8086, Device 0x9D4E, Revision 0x21 +PCI Device: 0000:00:1f.2: Class 0x00058000, Vendor 0x8086, Device 0x9D21, Revision 0x21 +PCI Device: 0000:00:1f.3: Class 0x00040300, Vendor 0x8086, Device 0x9D71, Revision 0x21 +PCI Device: 0000:00:1f.4: Class 0x000C0500, Vendor 0x8086, Device 0x9D23, Revision 0x21 +PCI Device: 0000:3a:00.0: Class 0x00FF0000, Vendor 0x10EC, Device 0x5287, Revision 0x01 +PCI Device: 0000:3a:00.1: Class 0x00020000, Vendor 0x10EC, Device 0x8168, Revision 0x12 +PCI Device: 0000:3b:00.0: Class 0x00028000, Vendor 0x8086, Device 0x24FB, Revision 0x10 +## GPIO ## +100 Series PCH-LP +GPP_A0 = 0x44000502 0x00000018 +GPP_A1 = 0x44000402 0x00000019 +GPP_A2 = 0x44000402 0x0000001a +GPP_A3 = 0x44000402 0x0000001b +GPP_A4 = 0x44000402 0x0000001c +GPP_A5 = 0x44000600 0x0000001d +GPP_A6 = 0x44000402 0x0000001e +GPP_A7 = 0x44000102 0x0000001f +GPP_A8 = 0x44000700 0x00000020 +GPP_A9 = 0x44000600 0x00000021 +GPP_A10 = 0x44000600 0x00001022 +GPP_A11 = 0x44000200 0x00000023 +GPP_A12 = 0x44000200 0x00000024 +GPP_A13 = 0x44000200 0x00000025 +GPP_A14 = 0x44000600 0x00000026 +GPP_A15 = 0x44000502 0x00000027 +GPP_A16 = 0x44000200 0x00000028 +GPP_A17 = 0x44000200 0x00000029 +GPP_A18 = 0x44000201 0x0000002a +GPP_A19 = 0x44000603 0x0000002b +GPP_A20 = 0x44000200 0x0000002c +GPP_A21 = 0x84000200 0x0000102d +GPP_A22 = 0x04000200 0x0000002e +GPP_A23 = 0x04000200 0x0000002f +GPP_B0 = 0x44000700 0x00000030 +GPP_B1 = 0x44000700 0x00000031 +GPP_B2 = 0x44000200 0x00000032 +GPP_B3 = 0x44000200 0x00000033 +GPP_B4 = 0x44000200 0x00000034 +GPP_B5 = 0x44000200 0x00000035 +GPP_B6 = 0x44000200 0x00000036 +GPP_B7 = 0x44000702 0x00000037 +GPP_B8 = 0x44000700 0x00000038 +GPP_B9 = 0x44000702 0x00000039 +GPP_B10 = 0x44000702 0x0000003a +GPP_B11 = 0x44000700 0x0000003b +GPP_B12 = 0x44000200 0x0000003c +GPP_B13 = 0x44000700 0x0000003d +GPP_B14 = 0x44000600 0x0000103e +GPP_B15 = 0x44000200 0x0000003f +GPP_B16 = 0x44000200 0x00000040 +GPP_B17 = 0x44000200 0x00000041 +GPP_B18 = 0x44000600 0x00003042 +GPP_B19 = 0x44000200 0x00000043 +GPP_B20 = 0x44000200 0x00000044 +GPP_B21 = 0x44000200 0x00000045 +GPP_B22 = 0x44000700 0x00001046 +GPP_B23 = 0x44000200 0x00000047 +GPP_C0 = 0x44000702 0x00000048 +GPP_C1 = 0x44000702 0x00001049 +GPP_C2 = 0x44000201 0x0000104a +GPP_C3 = 0x44000200 0x0000004b +GPP_C4 = 0x44000200 0x0000004c +GPP_C5 = 0x44000200 0x0000004d +GPP_C6 = 0xffffffff 0xffffffff +GPP_C7 = 0xffffffff 0xffffffff +GPP_C8 = 0x44000702 0x00000050 +GPP_C9 = 0x44000700 0x00000051 +GPP_C10 = 0x44000700 0x00000052 +GPP_C11 = 0x44000700 0x00000053 +GPP_C12 = 0x44000702 0x00000054 +GPP_C13 = 0x82880102 0x00000055 +GPP_C14 = 0x44000700 0x00000056 +GPP_C15 = 0x44000702 0x00000057 +GPP_C16 = 0x44000200 0x00000058 +GPP_C17 = 0x44000200 0x00000059 +GPP_C18 = 0x44000200 0x0000005a +GPP_C19 = 0x40880102 0x0000005b +GPP_C20 = 0x44000702 0x0000005c +GPP_C21 = 0x44000700 0x0000005d +GPP_C22 = 0x44000700 0x0000005e +GPP_C23 = 0x44000702 0x0000005f +GPP_D0 = 0x44000200 0x00000060 +GPP_D1 = 0x44000200 0x00000061 +GPP_D2 = 0x44000200 0x00000062 +GPP_D3 = 0x44000200 0x00000063 +GPP_D4 = 0x44000200 0x00000064 +GPP_D5 = 0x44000700 0x00000065 +GPP_D6 = 0x44000700 0x00000066 +GPP_D7 = 0x44000700 0x00000067 +GPP_D8 = 0x44000201 0x00000068 +GPP_D9 = 0x44000200 0x00000069 +GPP_D10 = 0x44000200 0x0000006a +GPP_D11 = 0x44000200 0x0000006b +GPP_D12 = 0x44000200 0x0000006c +GPP_D13 = 0x44000200 0x0000006d +GPP_D14 = 0x44000200 0x0000006e +GPP_D15 = 0x44000700 0x0000006f +GPP_D16 = 0x44000700 0x00000070 +GPP_D17 = 0x44000700 0x00000071 +GPP_D18 = 0x44000700 0x00000072 +GPP_D19 = 0x44000700 0x00000073 +GPP_D20 = 0x44000700 0x00000074 +GPP_D21 = 0x44000102 0x00000075 +GPP_D22 = 0x44000700 0x00000076 +GPP_D23 = 0x44000700 0x00000077 +GPP_E0 = 0x42100100 0x00001018 +GPP_E1 = 0x44000702 0x00000019 +GPP_E2 = 0x44000500 0x0000001a +GPP_E3 = 0x40000000 0x0000001b +GPP_E4 = 0x04000700 0x0000001c +GPP_E5 = 0x04000700 0x0000001d +GPP_E6 = 0x44000200 0x0000001e +GPP_E7 = 0x44000100 0x0000001f +GPP_E8 = 0x44000700 0x00000020 +GPP_E9 = 0x44000200 0x00000021 +GPP_E10 = 0x44000200 0x00000022 +GPP_E11 = 0x44000200 0x00000023 +GPP_E12 = 0x44000200 0x00000024 +GPP_E13 = 0x44000702 0x00000025 +GPP_E14 = 0x44000700 0x00000026 +GPP_E15 = 0x42840102 0x00000027 +GPP_E16 = 0x80880102 0x00000028 +GPP_E17 = 0x44000700 0x00000029 +GPP_E18 = 0x44000702 0x0000002a +GPP_E19 = 0x44000702 0x0000102b +GPP_E20 = 0x44000702 0x0000002c +GPP_E21 = 0x44000702 0x0000102d +GPP_E22 = 0x40100000 0x0000002e +GPP_E23 = 0x44000201 0x0000102f +GPD0 = 0x04000702 0x00000050 +GPD1 = 0x04000702 0x00000051 +GPD2 = 0x00880502 0x00000052 +GPD3 = 0x04000702 0x00003053 +GPD4 = 0x04000700 0x00000054 +GPD5 = 0x04000700 0x00000055 +GPD6 = 0x04000700 0x00000056 +GPD7 = 0x04000301 0x00000057 +GPD8 = 0x04000700 0x00000058 +GPD9 = 0x04000700 0x00000059 +GPD10 = 0x04000700 0x0000005a +GPD11 = 0x04000500 0x0000005b +GPP_F0 = 0x44000700 0x00000030 +GPP_F1 = 0x44000700 0x00000031 +GPP_F2 = 0x44000700 0x00000032 +GPP_F3 = 0x44000700 0x00000033 +GPP_F4 = 0x44000702 0x02000034 +GPP_F5 = 0x44000702 0x02000035 +GPP_F6 = 0x44000702 0x02000036 +GPP_F7 = 0x44000702 0x02000037 +GPP_F8 = 0x44000702 0x02000038 +GPP_F9 = 0x44000702 0x02000039 +GPP_F10 = 0x44000b02 0x0200003a +GPP_F11 = 0x44000b02 0x0200003b +GPP_F12 = 0x44000700 0x0000003c +GPP_F13 = 0x44000700 0x0000003d +GPP_F14 = 0x44000700 0x0000003e +GPP_F15 = 0x44000700 0x0000003f +GPP_F16 = 0x44000700 0x00000040 +GPP_F17 = 0x44000700 0x00000041 +GPP_F18 = 0x44000700 0x00000042 +GPP_F19 = 0x44000700 0x00000043 +GPP_F20 = 0x44000700 0x00000044 +GPP_F21 = 0x44000700 0x00000045 +GPP_F22 = 0x44000700 0x00000046 +GPP_F23 = 0x40100100 0x00000047 +GPP_G0 = 0x44000700 0x00000048 +GPP_G1 = 0x44000102 0x00000049 +GPP_G2 = 0x44000700 0x0000004a +GPP_G3 = 0x44000700 0x0000004b +GPP_G4 = 0x44000700 0x0000004c +GPP_G5 = 0x44000702 0x0000004d +GPP_G6 = 0x44000700 0x0000004e +GPP_G7 = 0x44000700 0x0000004f +## HDAUDIO ## +hdaudioC0D0 + vendor_name: Realtek + chip_name: ALC269VC + vendor_id: 0x10ec0269 + subsystem_id: 0x15581414 + revision_id: 0x100202 + 0x12: 0x90a60140 + 0x14: 0x90170120 + 0x15: 0x02211010 + 0x17: 0x40000000 + 0x18: 0x02a11030 + 0x19: 0x411111f0 + 0x1a: 0x411111f0 + 0x1b: 0x411111f0 + 0x1d: 0x40f4a205 + 0x1e: 0x411111f0 +hdaudioC0D2 + vendor_name: Intel + chip_name: Kabylake HDMI + vendor_id: 0x8086280b + subsystem_id: 0x80860101 + revision_id: 0x100000 + 0x05: 0x18560010 + 0x06: 0x18560010 + 0x07: 0x18560010 diff --git a/system76/galp3-b/descriptor b/system76/galp3-b/descriptor new file mode 100644 index 0000000000..91d587336e Binary files /dev/null and b/system76/galp3-b/descriptor differ diff --git a/system76/galp3-b/ec b/system76/galp3-b/ec new file mode 100755 index 0000000000..a8e1b958a2 Binary files /dev/null and b/system76/galp3-b/ec differ diff --git a/system76/galp3-b/flashrom b/system76/galp3-b/flashrom new file mode 100755 index 0000000000..46d0c94f75 Binary files /dev/null and b/system76/galp3-b/flashrom differ diff --git a/system76/galp3-b/gpio.h b/system76/galp3-b/gpio.h new file mode 100644 index 0000000000..ea1dc6e2af --- /dev/null +++ b/system76/galp3-b/gpio.h @@ -0,0 +1,194 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include +#include + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + _PAD_CFG_STRUCT(GPD0, 0x4000700, 0x0), + _PAD_CFG_STRUCT(GPD1, 0x4000700, 0x0), + _PAD_CFG_STRUCT(GPD2, 0x880500, 0x0), + _PAD_CFG_STRUCT(GPD3, 0x4000700, 0x3000), + _PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), + _PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), + _PAD_CFG_STRUCT(GPD6, 0x4000700, 0x0), + _PAD_CFG_STRUCT(GPD7, 0x4000301, 0x0), + _PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), + _PAD_CFG_STRUCT(GPD9, 0x4000700, 0x0), + _PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0), + _PAD_CFG_STRUCT(GPD11, 0x4000500, 0x0), + _PAD_CFG_STRUCT(GPP_A0, 0x44000500, 0x0), + _PAD_CFG_STRUCT(GPP_A1, 0x44000400, 0x0), + _PAD_CFG_STRUCT(GPP_A2, 0x44000400, 0x0), + _PAD_CFG_STRUCT(GPP_A3, 0x44000400, 0x0), + _PAD_CFG_STRUCT(GPP_A4, 0x44000400, 0x0), + _PAD_CFG_STRUCT(GPP_A5, 0x44000600, 0x0), + _PAD_CFG_STRUCT(GPP_A6, 0x44000400, 0x0), + _PAD_CFG_STRUCT(GPP_A7, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_A9, 0x44000600, 0x0), + _PAD_CFG_STRUCT(GPP_A10, 0x44000600, 0x1000), + _PAD_CFG_STRUCT(GPP_A11, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_A12, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_A13, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_A14, 0x44000600, 0x0), + _PAD_CFG_STRUCT(GPP_A15, 0x44000500, 0x0), + _PAD_CFG_STRUCT(GPP_A16, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_A17, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_A18, 0x44000201, 0x0), + _PAD_CFG_STRUCT(GPP_A19, 0x44000601, 0x0), + _PAD_CFG_STRUCT(GPP_A20, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_A21, 0x84000200, 0x1000), + _PAD_CFG_STRUCT(GPP_A22, 0x4000200, 0x0), + _PAD_CFG_STRUCT(GPP_A23, 0x4000200, 0x0), + _PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B2, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B3, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B4, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B5, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B6, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B7, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B8, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B10, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B12, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B14, 0x44000600, 0x1000), + _PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B16, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B17, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B18, 0x44000600, 0x3000), + _PAD_CFG_STRUCT(GPP_B19, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B20, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B21, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), + _PAD_CFG_STRUCT(GPP_B23, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_C0, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C1, 0x44000700, 0x1000), + _PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), + _PAD_CFG_STRUCT(GPP_C3, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_C4, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_C5, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_C6, 0xfffffffd, 0xffffff00), + _PAD_CFG_STRUCT(GPP_C7, 0xfffffffd, 0xffffff00), + _PAD_CFG_STRUCT(GPP_C8, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C11, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C12, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C13, 0x82880100, 0x0), + _PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C15, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C16, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_C17, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_C18, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_C19, 0x40880100, 0x0), + _PAD_CFG_STRUCT(GPP_C20, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C23, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_D0, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_D1, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_D2, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_D3, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_D4, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_D5, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_D6, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_D7, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_D8, 0x44000201, 0x0), + _PAD_CFG_STRUCT(GPP_D9, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_D10, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_D11, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_D12, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_D13, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_D14, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_D16, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_D21, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E0, 0x42100100, 0x1000), + _PAD_CFG_STRUCT(GPP_E1, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E2, 0x44000500, 0x0), + _PAD_CFG_STRUCT(GPP_E3, 0x40000000, 0x0), + _PAD_CFG_STRUCT(GPP_E4, 0x4000700, 0x0), + _PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0), + _PAD_CFG_STRUCT(GPP_E6, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_E7, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E9, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_E10, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_E11, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_E12, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0), + _PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0), + _PAD_CFG_STRUCT(GPP_E17, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), + _PAD_CFG_STRUCT(GPP_E20, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E21, 0x44000700, 0x1000), + _PAD_CFG_STRUCT(GPP_E22, 0x40100000, 0x0), + _PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), + _PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F4, 0x44000700, 0x2000000), + _PAD_CFG_STRUCT(GPP_F5, 0x44000700, 0x2000000), + _PAD_CFG_STRUCT(GPP_F6, 0x44000700, 0x2000000), + _PAD_CFG_STRUCT(GPP_F7, 0x44000700, 0x2000000), + _PAD_CFG_STRUCT(GPP_F8, 0x44000700, 0x2000000), + _PAD_CFG_STRUCT(GPP_F9, 0x44000700, 0x2000000), + _PAD_CFG_STRUCT(GPP_F10, 0x44000b00, 0x2000000), + _PAD_CFG_STRUCT(GPP_F11, 0x44000b00, 0x2000000), + _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F14, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F17, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F18, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0), + _PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_G5, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_G7, 0x44000700, 0x0), +}; + +#endif + +#endif diff --git a/system76/galp3-b/hda_verb.c b/system76/galp3-b/hda_verb.c new file mode 100644 index 0000000000..f346acd917 --- /dev/null +++ b/system76/galp3-b/hda_verb.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC269VC */ + 0x10ec0269, /* Vendor ID */ + 0x15581414, /* Subsystem ID */ + 11, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15581414), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x14, 0x90170120), + AZALIA_PIN_CFG(0, 0x15, 0x02211010), + AZALIA_PIN_CFG(0, 0x17, 0x40000000), + AZALIA_PIN_CFG(0, 0x18, 0x02a11030), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40f4a205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + /* Intel, KabylakeHDMI */ + 0x8086280b, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/system76/galp3-b/me b/system76/galp3-b/me new file mode 100644 index 0000000000..1d0148cb73 Binary files /dev/null and b/system76/galp3-b/me differ diff --git a/system76/galp3-b/pxe b/system76/galp3-b/pxe new file mode 100644 index 0000000000..46e67afcf8 Binary files /dev/null and b/system76/galp3-b/pxe differ diff --git a/system76/galp3-b/vbt b/system76/galp3-b/vbt new file mode 100644 index 0000000000..92bd9813dc Binary files /dev/null and b/system76/galp3-b/vbt differ diff --git a/system76/galp3-b/vga b/system76/galp3-b/vga new file mode 100644 index 0000000000..b6f52fea1d Binary files /dev/null and b/system76/galp3-b/vga differ diff --git a/system76/galp3-c/chip b/system76/galp3-c/chip new file mode 100644 index 0000000000..9f128a8a27 --- /dev/null +++ b/system76/galp3-c/chip @@ -0,0 +1 @@ +MX25L12805D diff --git a/system76/galp3-c/config b/system76/galp3-c/config new file mode 100644 index 0000000000..46fd63c0eb --- /dev/null +++ b/system76/galp3-c/config @@ -0,0 +1,855 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +CONFIG_CCACHE=y +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +# CONFIG_NO_RELOCATABLE_RAMSTAGE is not set +CONFIG_RELOCATABLE_RAMSTAGE=y +CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM=y +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_ELMEX is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SCALEWAY is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_SUPERMICRO is not set +CONFIG_VENDOR_SYSTEM76=y +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="system76/whl-u" +CONFIG_MAINBOARD_PART_NUMBER="galp3-c" +CONFIG_MAX_CPUS=8 +CONFIG_CBFS_SIZE=0xA00000 +CONFIG_UART_FOR_CONSOLE=2 +CONFIG_PAYLOAD_CONFIGFILE="" +CONFIG_MAINBOARD_VENDOR="System76" +CONFIG_VGA_BIOS_ID="8086,3ea0" +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_DIMM_SPD_SIZE=512 +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_VGA_BIOS_FILE="system76/$(VARIANT_DIR)/vga" +CONFIG_C_ENV_BOOTBLOCK_SIZE=0xC000 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1558 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1323 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="System76" +CONFIG_VARIANT_DIR="galp3-c" +CONFIG_DEVICETREE="devicetree.cb" +CONFIG_INTEL_GMA_VBT_FILE="system76/$(VARIANT_DIR)/vbt" +# CONFIG_POST_IO is not set +CONFIG_DCACHE_RAM_BASE=0xfef00000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_OVERRIDE_DEVICETREE="" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 +CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 +CONFIG_HAVE_INTEL_FIRMWARE=y +# CONFIG_POST_DEVICE is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_VBOOT is not set +CONFIG_DIMM_MAX=2 +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_TTYS0_LCS=3 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Galago Pro" +CONFIG_IFD_BIN_PATH="system76/$(VARIANT_DIR)/descriptor" +CONFIG_ME_BIN_PATH="system76/$(VARIANT_DIR)/me" +CONFIG_HAVE_IFD_BIN=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_M_FILE="$(obj)/Fsp_M.fd" +CONFIG_FSP_S_FILE="$(obj)/Fsp_S.fd" +CONFIG_FSP_S_CBFS="fsps.bin" +CONFIG_FSP_M_CBFS="fspm.bin" +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_MAINBOARD_VERSION="galp3-c" +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_CPU_MICROCODE_CBFS_LEN=0x0 +CONFIG_CPU_MICROCODE_CBFS_LOC=0x0 +CONFIG_SMBIOS_ENCLOSURE_TYPE=0x09 +# CONFIG_BOARD_SYSTEM76_GALP2 is not set +# CONFIG_BOARD_SYSTEM76_GALP3 is not set +# CONFIG_BOARD_SYSTEM76_GALP3_B is not set +CONFIG_BOARD_SYSTEM76_GALP3_C=y +# CONFIG_BOARD_SYSTEM76_DARP5 is not set +CONFIG_CONSOLE_POST=y +CONFIG_PXE_ROM_ID="10ec,8168" +CONFIG_FSP_M_XIP=y +CONFIG_BOARD_ROMSIZE_KB_16384=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x1000000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y +# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set +CONFIG_POWER_STATE_ON_AFTER_FAILURE=y +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=1 +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_SYSTEM_TYPE_TABLET is not set +# CONFIG_SYSTEM_TYPE_DETACHABLE is not set +# CONFIG_SYSTEM_TYPE_CONVERTIBLE is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +CONFIG_CPU_SPECIFIC_OPTIONS=y +CONFIG_HEAP_SIZE=0x8000 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x200000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" +CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=216 +# CONFIG_SOC_CAVIUM_CN81XX is not set +CONFIG_ARCH_ARMV8_EXTENSION=0 +CONFIG_STACK_SIZE=0x1000 +# CONFIG_SOC_CAVIUM_COMMON is not set +# CONFIG_SOC_INTEL_GLK is not set +CONFIG_PCR_BASE_ADDRESS=0xfd000000 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_FSP_HEADER_PATH="3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" +CONFIG_FSP_FD_PATH="3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" +# CONFIG_NHLT_DMIC_1CH_16B is not set +# CONFIG_NHLT_DMIC_2CH_16B is not set +# CONFIG_NHLT_DMIC_4CH_16B is not set +# CONFIG_NHLT_MAX98357 is not set +# CONFIG_NHLT_DA7219 is not set +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_IFD_CHIPSET="cnl" +CONFIG_CPU_BCLK_MHZ=100 +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30 +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=3 +CONFIG_SOC_INTEL_I2C_DEV_MAX=6 +# CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE is not set +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_TTYS0_BASE=0x3e8 +CONFIG_SOC_INTEL_CANNONLAKE=y +CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE=y +# CONFIG_SOC_INTEL_COFFEELAKE is not set +CONFIG_SOC_INTEL_WHISKEYLAKE=y +# CONFIG_SOC_INTEL_CANNONLAKE_PCH_H is not set +# CONFIG_NHLT_MAX98373 is not set +CONFIG_MAX_ROOT_PORTS=16 +CONFIG_EXCLUDE_EMMC_INTERFACE=y +# CONFIG_USE_CANNONLAKE_CAR_NEM_ENHANCED is not set +CONFIG_USE_CANNONLAKE_FSP_CAR=y +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +# CONFIG_SOC_INTEL_KABYLAKE is not set +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=4 +CONFIG_SOC_INTEL_COMMON=y + +# +# Intel SoC Common Code +# +CONFIG_SOC_INTEL_COMMON_BLOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_CAR is not set +# CONFIG_INTEL_CAR_NEM is not set +# CONFIG_INTEL_CAR_CQOS is not set +# CONFIG_INTEL_CAR_NEM_ENHANCED is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y +CONFIG_SOC_INTEL_COMMON_BLOCK_EBDA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y +CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES is not set +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2=y +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y +# CONFIG_PMC_INVALID_READ_AFTER_WRITE is not set +CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y +CONFIG_SOC_AHCI_PORT_IMPLEMENTED_INVERT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0 +CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y +CONFIG_SA_PCIEX_LENGTH=0x10000000 +# CONFIG_SA_ENABLE_IMR is not set +# CONFIG_SA_ENABLE_DPR is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y +CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_VMX is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y + +# +# Intel SoC Common PCH Code +# +CONFIG_SOC_INTEL_COMMON_PCH_BASE=y +CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y +CONFIG_PCH_SPECIFIC_OPTIONS=y + +# +# Intel SoC Common coreboot stages +# +# CONFIG_DISPLAY_SMM_MEMORY_MAP is not set +CONFIG_SOC_INTEL_COMMON_RESET=y +CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y +# CONFIG_ACPI_CONSOLE is not set +# CONFIG_SOC_INTEL_COMMON_ACPI is not set +# CONFIG_SOC_INTEL_COMMON_ACPI_EC_PTS_WAK is not set +CONFIG_SOC_INTEL_COMMON_NHLT=y +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_MEDIATEK_MT8183 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_QUALCOMM_SDM845 is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_SSE2=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_MICROCODE_UPDATE_PRE_RAM=y +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +CONFIG_PARALLEL_MP=y +CONFIG_PARALLEL_MP_AP_WORK=y +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_CONSTANT_RATE=y +CONFIG_TSC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +# CONFIG_TSC_SYNC_MFENCE is not set +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_MODULE_HEAP_SIZE=0x4000 +CONFIG_SMM_STUB_STACK_SIZE=0x400 +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_NO_CAR_GLOBAL_MIGRATION=y +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set +CONFIG_CPU_UCODE_BINARIES="system76/$(VARIANT_DIR)/microcode" + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set + +# +# Super I/O +# +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +# CONFIG_EC_GOOGLE_WILCO is not set +CONFIG_EC_BASE_ACPI_DATA=0x930 +CONFIG_EC_BASE_ACPI_COMMAND=0x934 +CONFIG_EC_BASE_HOST_DATA=0x940 +CONFIG_EC_BASE_HOST_COMMAND=0x944 +CONFIG_EC_BASE_PACKET=0x950 +CONFIG_SEABIOS_PS2_TIMEOUT=1000 + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_MAINBOARD_USES_IFD_GBE_REGION is not set +# CONFIG_MAINBOARD_USES_IFD_EC_REGION is not set +# CONFIG_CAVIUM_BDK is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set +CONFIG_UDK_2017_BINDING=y +CONFIG_UDK_2013_VERSION=2013 +CONFIG_UDK_2015_VERSION=2015 +CONFIG_UDK_2017_VERSION=2017 +CONFIG_UDK_VERSION=2017 +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_USE_ARCH_TIMER is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_PPC64 is not set +# CONFIG_ARCH_BOOTBLOCK_PPC64 is not set +# CONFIG_ARCH_VERSTAGE_PPC64 is not set +# CONFIG_ARCH_ROMSTAGE_PPC64 is not set +# CONFIG_ARCH_RAMSTAGE_PPC64 is not set +# CONFIG_ARCH_RISCV is not set +CONFIG_ARCH_RISCV_M=y +# CONFIG_ARCH_RISCV_S is not set +# CONFIG_ARCH_RISCV_U is not set +# CONFIG_ARCH_RISCV_RV64 is not set +# CONFIG_ARCH_RISCV_RV32 is not set +# CONFIG_ARCH_RISCV_PMP is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +# CONFIG_RISCV_USE_ARCH_TIMER is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_POSTCAR_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_RAMBASE=0xe00000 +CONFIG_RAMTOP=0x1000000 +# CONFIG_CBMEM_TOP_BACKUP is not set +CONFIG_EARLY_EBDA_INIT=y +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_HPET_ADDRESS_OVERRIDE is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POSTCAR_STAGE=y +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +# CONFIG_PAGING_IN_CACHE_AS_RAM is not set +CONFIG_IDT_IN_EVERY_STAGE=y +CONFIG_HAVE_CF9_RESET=y + +# +# Devices +# +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_HAVE_FSP_GOP=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +# CONFIG_VGA_ROM_RUN is not set +CONFIG_RUN_FSP_GOP=y +# CONFIG_NO_GFX_INIT is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +CONFIG_PCI=y +# CONFIG_NO_MMCONF_SUPPORT is not set +CONFIG_MMCONF_SUPPORT=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_ELOG is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +CONFIG_CACHE_MRC_SETTINGS=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_MRC_SETTINGS_PROTECT=y +# CONFIG_HAS_RECOVERY_MRC_CACHE is not set +# CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN is not set +# CONFIG_MRC_SETTINGS_VARIABLE_DATA is not set +# CONFIG_MRC_WRITE_NV_LATE is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +# CONFIG_SMMSTORE is not set +# CONFIG_SMMSTORE_IN_CBFS is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +# CONFIG_HAVE_USBDEBUG is not set +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_AMD_PI is not set +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +CONFIG_DRIVERS_I2C_DESIGNWARE=y +# CONFIG_DRIVERS_I2C_DESIGNWARE_DEBUG is not set +# CONFIG_DRIVERS_I2C_MAX98373 is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCA9538 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_DRIVERS_I2C_SX9310 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set +# CONFIG_DISPLAY_HOBS is not set +# CONFIG_DISPLAY_UPD_DATA is not set +CONFIG_PLATFORM_USES_FSP2_0=y +# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set +# CONFIG_DISPLAY_FSP_HEADER is not set +CONFIG_FSP_T_CBFS="fspt.bin" +CONFIG_FSP_USE_REPO=y +CONFIG_FSP_T_FILE="$(obj)/Fsp_T.fd" +CONFIG_FSP_CAR=y +CONFIG_FSP_T_XIP=y +# CONFIG_FSP_USES_CB_STACK is not set +# CONFIG_VERIFY_HOBS is not set +CONFIG_DISPLAY_FSP_VERSION_INFO=y +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set +# CONFIG_INTEL_GMA_SWSMISCI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_LPC_TPM is not set +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_USB_ACPI is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# + +# +# Trusted Platform Module +# +CONFIG_USER_NO_TPM=y +# CONFIG_ACPI_SATA_GENERATOR is not set +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3e8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +# CONFIG_HAVE_OPTION_TABLE is not set +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_COMMON_FADT=y +CONFIG_ACPI_NHLT=y + +# +# System tables +# +# CONFIG_GENERATE_MP_TABLE is not set +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_BAYOU is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_LINUXBOOT is not set +CONFIG_PAYLOAD_SEABIOS=y +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_YABITS is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf" +CONFIG_SEABIOS_STABLE=y +# CONFIG_SEABIOS_MASTER is not set +# CONFIG_SEABIOS_REVISION is not set +CONFIG_SEABIOS_THREAD_OPTIONROMS=y +CONFIG_SEABIOS_VGA_COREBOOT=y +CONFIG_SEABIOS_BOOTORDER_FILE="" +# CONFIG_SEABIOS_ADD_SERCON_PORT_FILE is not set +CONFIG_PAYLOAD_VGABIOS_FILE="payloads/external/SeaBIOS/seabios/out/vgabios.bin" +CONFIG_SEABIOS_DEBUG_LEVEL=-1 + +# +# Using default SeaBIOS log level +# +CONFIG_PAYLOAD_OPTIONS="" +CONFIG_PXE=y + +# +# PXE Options +# +CONFIG_PXE_ROM=y +# CONFIG_BUILD_IPXE is not set +CONFIG_PXE_ROM_FILE="system76/$(VARIANT_DIR)/pxe" +# CONFIG_PXE_SERIAL_CONSOLE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +# CONFIG_PAYLOAD_FIT_SUPPORT is not set +CONFIG_COMPRESS_SECONDARY_PAYLOAD=y + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# + +# +# CPU Debug Settings +# +CONFIG_HAVE_DISPLAY_MTRRS=y +# CONFIG_DISPLAY_MTRRS is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +CONFIG_HAVE_DEBUG_GPIO=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_CBFS is not set +# CONFIG_HAVE_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +CONFIG_NO_EDID_FILL_FB=y +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +CONFIG_REG_SCRIPT=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_GENERIC_GPIO_LIB=y +CONFIG_C_ENVIRONMENT_BOOTBLOCK=y diff --git a/system76/galp3-c/coreboot b/system76/galp3-c/coreboot new file mode 100644 index 0000000000..e3ed620377 Binary files /dev/null and b/system76/galp3-c/coreboot differ diff --git a/system76/galp3-c/coreboot-collector b/system76/galp3-c/coreboot-collector new file mode 100644 index 0000000000..5b6f7009dd --- /dev/null +++ b/system76/galp3-c/coreboot-collector @@ -0,0 +1,233 @@ +## PCI ## +PCI Device: 0000:00:00.0: Class 0x00060000, Vendor 0x8086, Device 0x3E34, Revision 0x0B +PCI Device: 0000:00:02.0: Class 0x00030000, Vendor 0x8086, Device 0x3EA0, Revision 0x00 +PCI Device: 0000:00:12.0: Class 0x00118000, Vendor 0x8086, Device 0x9DF9, Revision 0x30 +PCI Device: 0000:00:14.0: Class 0x000C0330, Vendor 0x8086, Device 0x9DED, Revision 0x30 +PCI Device: 0000:00:14.2: Class 0x00050000, Vendor 0x8086, Device 0x9DEF, Revision 0x30 +PCI Device: 0000:00:14.3: Class 0x00028000, Vendor 0x8086, Device 0x9DF0, Revision 0x30 +PCI Device: 0000:00:17.0: Class 0x00010601, Vendor 0x8086, Device 0x9DD3, Revision 0x30 +PCI Device: 0000:00:1c.0: Class 0x00060400, Vendor 0x8086, Device 0x9DBC, Revision 0xF0 +PCI Device: 0000:00:1d.0: Class 0x00060400, Vendor 0x8086, Device 0x9DB0, Revision 0xF0 +PCI Device: 0000:00:1f.0: Class 0x00060100, Vendor 0x8086, Device 0x9D84, Revision 0x30 +PCI Device: 0000:00:1f.3: Class 0x00040300, Vendor 0x8086, Device 0x9DC8, Revision 0x30 +PCI Device: 0000:00:1f.4: Class 0x000C0500, Vendor 0x8086, Device 0x9DA3, Revision 0x30 +PCI Device: 0000:00:1f.5: Class 0x000C8000, Vendor 0x8086, Device 0x9DA4, Revision 0x30 +PCI Device: 0000:39:00.0: Class 0x00FF0000, Vendor 0x10EC, Device 0x5287, Revision 0x01 +PCI Device: 0000:39:00.1: Class 0x00020000, Vendor 0x10EC, Device 0x8168, Revision 0x12 +## GPIO ## +300 Series PCH +GPP_A0 = 0x44000702 0x00000018 0x00000010 0x00000000 +GPP_A1 = 0x44000702 0x00003c19 0x00000010 0x00000000 +GPP_A2 = 0x44000702 0x00003c1a 0x00000010 0x00000000 +GPP_A3 = 0x44000702 0x00003c1b 0x00000010 0x00000000 +GPP_A4 = 0x44000702 0x00003c1c 0x00000010 0x00000000 +GPP_A5 = 0x44000700 0x0000001d 0x00000010 0x00000000 +GPP_A6 = 0x44000702 0x0000001e 0x00000010 0x00000000 +GPP_A7 = 0x44000102 0x0000001f 0x00000010 0x00000000 +GPP_A8 = 0x44000700 0x00000020 0x00000010 0x00000000 +GPP_A9 = 0x44000700 0x00001021 0x00000010 0x00000000 +GPP_A10 = 0x44000500 0x00001022 0x00000010 0x00000000 +GPP_A11 = 0x44000102 0x00003023 0x00000010 0x00000000 +GPP_A12 = 0x44000102 0x00000024 0x00000010 0x00000000 +GPP_A13 = 0x44000700 0x00000025 0x00000010 0x00000000 +GPP_A14 = 0x44000700 0x00000026 0x00000010 0x00000000 +GPP_A15 = 0x44000702 0x00003027 0x00000010 0x00000000 +GPP_A16 = 0x44000102 0x00000028 0x00000010 0x00000000 +GPP_A17 = 0x44000100 0x00000029 0x00000010 0x00000000 +GPP_A18 = 0x44000102 0x0000002a 0x00000010 0x00000000 +GPP_A19 = 0x44000102 0x0000002b 0x00000010 0x00000000 +GPP_A20 = 0x44000102 0x0000002c 0x00000010 0x00000000 +GPP_A21 = 0x44000102 0x0000002d 0x00000010 0x00000000 +GPP_A22 = 0x44000200 0x0000002e 0x00000010 0x00000000 +GPP_A23 = 0x44000102 0x0000002f 0x00000010 0x00000000 +GPP_B0 = 0x44000700 0x00000000 0x00000000 0x00000000 +GPP_B1 = 0x44000102 0x00000030 0x00000010 0x00000000 +GPP_B2 = 0x44000102 0x00000031 0x00000010 0x00000000 +GPP_B3 = 0x44000102 0x00000032 0x00000010 0x00000000 +GPP_B4 = 0x44000102 0x00000033 0x00000010 0x00000000 +GPP_B5 = 0x44000102 0x00000034 0x00000010 0x00000000 +GPP_B6 = 0x44000102 0x00000035 0x00000010 0x00000000 +GPP_B7 = 0x44000102 0x00000036 0x00000010 0x00000000 +GPP_B8 = 0x44000702 0x00000037 0x00000010 0x00000000 +GPP_B9 = 0x44000700 0x00000038 0x00000010 0x00000000 +GPP_B10 = 0x44000702 0x00000039 0x00000010 0x00000000 +GPP_B11 = 0x44000702 0x0000003a 0x00000010 0x00000000 +GPP_B12 = 0x44000102 0x0000003b 0x00000010 0x00000000 +GPP_B13 = 0x44000700 0x0000003c 0x00000010 0x00000000 +GPP_B14 = 0x44000700 0x0000003d 0x00000010 0x00000000 +GPP_B15 = 0x44000600 0x0000003e 0x00000010 0x00000000 +GPP_B16 = 0x44000102 0x0000003f 0x00000010 0x00000000 +GPP_B17 = 0x44000102 0x00000040 0x00000010 0x00000000 +GPP_B18 = 0x44000100 0x00000041 0x00000010 0x00000000 +GPP_B19 = 0x44000102 0x00000042 0x00000010 0x00000000 +GPP_B20 = 0x44000102 0x00000043 0x00000010 0x00000000 +GPP_B21 = 0x44000102 0x00000044 0x00000010 0x00000000 +GPP_B22 = 0x44000102 0x00000045 0x00000010 0x00000000 +GPP_B23 = 0x44000102 0x00000046 0x00000010 0x00000000 +GPP_G0 = 0x44000102 0x00000047 0x00000010 0x00000000 +GPP_G1 = 0x44000700 0x00000000 0x00000000 0x00000000 +GPP_G2 = 0x44000700 0x00000000 0x00000000 0x00000000 +GPP_G3 = 0x44000102 0x0000006c 0x00000010 0x00000000 +GPP_G4 = 0x44000102 0x0000006d 0x00000010 0x00000000 +GPP_G5 = 0x44000102 0x0000006e 0x00000010 0x00000000 +GPP_G6 = 0x44000102 0x0000006f 0x00000010 0x00000000 +GPP_G7 = 0x44000102 0x00000070 0x00000010 0x00000000 +GPP_D0 = 0x44000102 0x00000060 0x00000010 0x00000000 +GPP_D1 = 0x44000102 0x00000061 0x00000010 0x00000000 +GPP_D2 = 0x44000102 0x00000062 0x00000010 0x00000000 +GPP_D3 = 0x44000102 0x00000063 0x00000010 0x00000000 +GPP_D4 = 0x44000102 0x00000064 0x00000010 0x00000000 +GPP_D5 = 0x44000102 0x00000065 0x00000010 0x00000000 +GPP_D6 = 0x44000102 0x00000066 0x00000010 0x00000000 +GPP_D7 = 0x44000102 0x00000067 0x00000010 0x00000000 +GPP_D8 = 0x44000201 0x00000068 0x00000010 0x00000000 +GPP_D9 = 0x40880102 0x00000069 0x00000010 0x00000000 +GPP_D10 = 0x44000102 0x0000006a 0x00000010 0x00000000 +GPP_D11 = 0x40880102 0x0000306b 0x00000010 0x00000000 +GPP_D12 = 0x44000102 0x0000006c 0x00000810 0x00000000 +GPP_D13 = 0x44000102 0x0000006d 0x00000010 0x00000000 +GPP_D14 = 0x44000102 0x0000006e 0x00000010 0x00000000 +GPP_D15 = 0x44000102 0x0000006f 0x00000010 0x00000000 +GPP_D16 = 0x04000201 0x00000070 0x00000010 0x00000000 +GPP_D17 = 0x44000102 0x00000071 0x00000010 0x00000000 +GPP_D18 = 0x44000102 0x00000072 0x00000010 0x00000000 +GPP_D19 = 0x44000500 0x00000073 0x00000010 0x00000000 +GPP_D20 = 0x44000500 0x00000074 0x00000010 0x00000000 +GPP_D21 = 0x44000102 0x00000075 0x00000010 0x00000000 +GPP_D22 = 0x44000102 0x00000076 0x00000010 0x00000000 +GPP_D23 = 0x44000102 0x00000077 0x00000010 0x00000000 +GPP_F0 = 0x44000700 0x00000000 0x00000000 0x00000000 +GPP_F1 = 0x44000700 0x00000030 0x00000010 0x00000000 +GPP_F2 = 0x44000100 0x00000031 0x00000010 0x00000000 +GPP_F3 = 0x44000100 0x00000032 0x00000010 0x00000000 +GPP_F4 = 0x44000100 0x00000033 0x00000010 0x00000000 +GPP_F5 = 0x44000700 0x00000034 0x00000010 0x00000000 +GPP_F6 = 0x44000702 0x00003035 0x00000010 0x00000000 +GPP_F7 = 0x44000700 0x00000036 0x00000010 0x00000000 +GPP_F8 = 0x44000702 0x00003037 0x00000010 0x00000000 +GPP_F9 = 0x44000700 0x00000038 0x00000010 0x00000000 +GPP_F10 = 0x44000700 0x00000039 0x00000010 0x00000000 +GPP_F11 = 0x44000100 0x0000003a 0x00000010 0x00000000 +GPP_F12 = 0x44000100 0x0000003b 0x00000010 0x00000000 +GPP_F13 = 0x44000100 0x0000003c 0x00000010 0x00000000 +GPP_F14 = 0x44000100 0x0000003d 0x00000010 0x00000000 +GPP_F15 = 0x44000100 0x0000003e 0x00000010 0x00000000 +GPP_F16 = 0x44000100 0x0000003f 0x00000010 0x00000000 +GPP_F17 = 0x44000100 0x00000040 0x00000010 0x00000000 +GPP_F18 = 0x44000100 0x00000041 0x00000010 0x00000000 +GPP_F19 = 0x44000100 0x00000042 0x00000010 0x00000000 +GPP_F20 = 0x44000100 0x00000043 0x00000010 0x00000000 +GPP_F21 = 0x44000100 0x00000044 0x00000010 0x00000000 +GPP_F22 = 0x44000100 0x00000045 0x00000010 0x00000000 +GPP_F23 = 0x44000100 0x00000046 0x00000010 0x00000000 +GPP_H0 = 0x44000100 0x00001047 0x00000010 0x00000000 +GPP_H1 = 0x44000102 0x00000048 0x00000010 0x00000000 +GPP_H2 = 0x44000f00 0x00000049 0x00000010 0x00000000 +GPP_H3 = 0x44000f00 0x0000004a 0x00000010 0x00000000 +GPP_H4 = 0x44000102 0x0000004b 0x00000010 0x00000000 +GPP_H5 = 0x44000102 0x0000004c 0x00000010 0x00000000 +GPP_H6 = 0x44000102 0x0000004d 0x00000010 0x00000000 +GPP_H7 = 0x44000102 0x0000004e 0x00000010 0x00000000 +GPP_H8 = 0x44000102 0x0000004f 0x00000010 0x00000000 +GPP_H9 = 0x44000102 0x00000050 0x00000010 0x00000000 +GPP_H10 = 0x44000102 0x00000051 0x00000010 0x00000000 +GPP_H11 = 0x44000102 0x00000052 0x00000010 0x00000000 +GPP_H12 = 0x44000102 0x00000053 0x00000010 0x00000000 +GPP_H13 = 0x44000102 0x00000054 0x00000010 0x00000000 +GPP_H14 = 0x44000102 0x00000055 0x00000010 0x00000000 +GPP_H15 = 0x44000102 0x00000056 0x00000010 0x00000000 +GPP_H16 = 0x44000102 0x00000057 0x00000010 0x00000000 +GPP_H17 = 0x44000102 0x00000058 0x00000010 0x00000000 +GPP_H18 = 0x44000102 0x00000059 0x00000010 0x00000000 +GPP_H19 = 0x44000500 0x0000005a 0x00000010 0x00000000 +GPP_H20 = 0x44000102 0x0000005b 0x00000010 0x00000000 +GPP_H21 = 0x44000102 0x0000005c 0x00000010 0x00000000 +GPP_H22 = 0x44000102 0x0000005d 0x00000810 0x00000000 +GPP_H23 = 0x84000201 0x0000005e 0x00000010 0x00000000 +GPD0 = 0x04000102 0x00000060 0x00000010 0x00000000 +GPD1 = 0x44000700 0x00003c61 0x00000010 0x00000000 +GPD2 = 0x04000102 0x00003c62 0x00000010 0x00000000 +GPD3 = 0x44000702 0x00003063 0x00000010 0x00000000 +GPD4 = 0x44000600 0x00000064 0x00000010 0x00000000 +GPD5 = 0x44000600 0x00000065 0x00000010 0x00000000 +GPD6 = 0x44000600 0x00000066 0x00000010 0x00000000 +GPD7 = 0x04000102 0x00000067 0x00000810 0x00000000 +GPD8 = 0x44000700 0x00000068 0x00000010 0x00000000 +GPD9 = 0x04000102 0x00000069 0x00000010 0x00000000 +GPD10 = 0x44000600 0x0000006a 0x00000010 0x00000000 +GPD11 = 0x04000102 0x0000006b 0x00000010 0x00000000 +GPP_C0 = 0x44000702 0x00000048 0x00000010 0x00000000 +GPP_C1 = 0x44000702 0x00000049 0x00000010 0x00000000 +GPP_C2 = 0x44000102 0x0000004a 0x00000010 0x00000000 +GPP_C3 = 0x44000102 0x0000004b 0x00000010 0x00000000 +GPP_C4 = 0x44000102 0x0000004c 0x00000010 0x00000000 +GPP_C5 = 0x44000100 0x0000004d 0x00000010 0x00000000 +GPP_C6 = 0x44000102 0x0000004e 0x00000010 0x00000000 +GPP_C7 = 0x44000102 0x0000004f 0x00000010 0x00000000 +GPP_C8 = 0x44000102 0x00000050 0x00000010 0x00000000 +GPP_C9 = 0x82880102 0x00003051 0x00000010 0x00000000 +GPP_C10 = 0x84000200 0x00000052 0x00000010 0x00000000 +GPP_C11 = 0x44000102 0x00000053 0x00000010 0x00000000 +GPP_C12 = 0x84000201 0x00000054 0x00000010 0x00000000 +GPP_C13 = 0x84000201 0x00000055 0x00000010 0x00000000 +GPP_C14 = 0x84000200 0x00000056 0x00000010 0x00000000 +GPP_C15 = 0x84000201 0x00003057 0x00000010 0x00000000 +GPP_C16 = 0x44000102 0x00000058 0x00000010 0x00000000 +GPP_C17 = 0x44000102 0x00000059 0x00000010 0x00000000 +GPP_C18 = 0x44000102 0x0000005a 0x00000010 0x00000000 +GPP_C19 = 0x44000102 0x0000005b 0x00000010 0x00000000 +GPP_C20 = 0x44000102 0x0000005c 0x00000010 0x00000000 +GPP_C21 = 0x44000102 0x0000005d 0x00000010 0x00000000 +GPP_C22 = 0x44000102 0x0000005e 0x00000010 0x00000000 +GPP_C23 = 0x44000102 0x0000005f 0x00000010 0x00000000 +GPP_E0 = 0x44000102 0x00000018 0x00000010 0x00000000 +GPP_E1 = 0x44000102 0x00000019 0x00000010 0x00000000 +GPP_E2 = 0x44000700 0x0000301a 0x00000010 0x00000000 +GPP_E3 = 0x44000102 0x0000001b 0x00000010 0x00000000 +GPP_E4 = 0x44000102 0x0000001c 0x00000010 0x00000000 +GPP_E5 = 0x44000102 0x0000001d 0x00000010 0x00000000 +GPP_E6 = 0x44000700 0x0000001e 0x00000010 0x00000000 +GPP_E7 = 0x44000102 0x0000001f 0x00000010 0x00000000 +GPP_E8 = 0x44000700 0x00000020 0x00000010 0x00000000 +GPP_E9 = 0x44000102 0x00000021 0x00000810 0x00000000 +GPP_E10 = 0x44000102 0x00000022 0x00000810 0x00000000 +GPP_E11 = 0x44000102 0x00000023 0x00000810 0x00000000 +GPP_E12 = 0x44000102 0x00000024 0x00000010 0x00000000 +GPP_E13 = 0x44000700 0x00000025 0x00000010 0x00000000 +GPP_E14 = 0x44000700 0x00000026 0x00000010 0x00000000 +GPP_E15 = 0x44000102 0x00000027 0x00000010 0x00000000 +GPP_E16 = 0x80880102 0x00000028 0x00000010 0x00000000 +GPP_E17 = 0x44000702 0x00000029 0x00000010 0x00000000 +GPP_E18 = 0x44000702 0x0000002a 0x00000010 0x00000000 +GPP_E19 = 0x44000602 0x0000002b 0x00000810 0x00000000 +GPP_E20 = 0x44000702 0x0000002c 0x00000010 0x00000000 +GPP_E21 = 0x44000602 0x0000002d 0x00000810 0x00000000 +GPP_E22 = 0x44000102 0x0000002e 0x00000010 0x00000000 +GPP_E23 = 0x44000102 0x0000002f 0x00000010 0x00000000 +## HDAUDIO ## +hdaudioC0D0 + vendor_name: Realtek + chip_name: ALC293 + vendor_id: 0x10ec0293 + subsystem_id: 0x15581323 + revision_id: 0x100003 + 0x12: 0x90a60130 + 0x13: 0x40000000 + 0x14: 0x90170110 + 0x15: 0x02211020 + 0x16: 0x411111f0 + 0x18: 0x02a11040 + 0x19: 0x411111f0 + 0x1a: 0x411111f0 + 0x1b: 0x411111f0 + 0x1d: 0x40738205 + 0x1e: 0x411111f0 +hdaudioC0D2 + vendor_name: Intel + chip_name: Kabylake HDMI + vendor_id: 0x8086280b + subsystem_id: 0x80860101 + revision_id: 0x100000 + 0x05: 0x18560010 + 0x06: 0x18560010 + 0x07: 0x18560010 diff --git a/system76/galp3-c/descriptor b/system76/galp3-c/descriptor new file mode 100644 index 0000000000..3ebad4aa6d Binary files /dev/null and b/system76/galp3-c/descriptor differ diff --git a/system76/galp3-c/flashrom b/system76/galp3-c/flashrom new file mode 100755 index 0000000000..75832cba0b Binary files /dev/null and b/system76/galp3-c/flashrom differ diff --git a/system76/galp3-c/gpio.h b/system76/galp3-c/gpio.h new file mode 100644 index 0000000000..887bcb355c --- /dev/null +++ b/system76/galp3-c/gpio.h @@ -0,0 +1,218 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include +#include + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + _PAD_CFG_STRUCT(GPD0, 0x4000100, 0x0), + _PAD_CFG_STRUCT(GPD1, 0x44000700, 0x3c00), + _PAD_CFG_STRUCT(GPD2, 0x4000100, 0x3c00), + _PAD_CFG_STRUCT(GPD3, 0x44000700, 0x3000), + _PAD_CFG_STRUCT(GPD4, 0x44000600, 0x0), + _PAD_CFG_STRUCT(GPD5, 0x44000600, 0x0), + _PAD_CFG_STRUCT(GPD6, 0x44000600, 0x0), + _PAD_CFG_STRUCT(GPD7, 0x4000100, 0x0), + _PAD_CFG_STRUCT(GPD8, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPD9, 0x4000100, 0x0), + _PAD_CFG_STRUCT(GPD10, 0x44000600, 0x0), + _PAD_CFG_STRUCT(GPD11, 0x4000100, 0x0), + _PAD_CFG_STRUCT(GPP_A0, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x3c00), + _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x3c00), + _PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x3c00), + _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x3c00), + _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_A7, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), + _PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x1000), + _PAD_CFG_STRUCT(GPP_A11, 0x44000100, 0x3000), + _PAD_CFG_STRUCT(GPP_A12, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x3000), + _PAD_CFG_STRUCT(GPP_A16, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_A17, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_A18, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_A19, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_A20, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_A21, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_A22, 0x44000200, 0x0), + _PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B1, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B2, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B3, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B4, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B5, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B6, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B7, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B8, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B10, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B12, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B14, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_B15, 0x44000600, 0x0), + _PAD_CFG_STRUCT(GPP_B16, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B17, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B18, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B19, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B20, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B21, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B22, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_B23, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C0, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C1, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_C2, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C3, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C4, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C5, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C6, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C7, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C8, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000), + _PAD_CFG_STRUCT(GPP_C10, 0x84000200, 0x0), + _PAD_CFG_STRUCT(GPP_C11, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C12, 0x84000201, 0x0), + _PAD_CFG_STRUCT(GPP_C13, 0x84000201, 0x0), + _PAD_CFG_STRUCT(GPP_C14, 0x84000200, 0x0), + _PAD_CFG_STRUCT(GPP_C15, 0x84000201, 0x3000), + _PAD_CFG_STRUCT(GPP_C16, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C17, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C18, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C19, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C20, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C21, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C22, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_C23, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D0, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D1, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D2, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D3, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D4, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D5, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D6, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D7, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D8, 0x44000201, 0x0), + _PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0), + _PAD_CFG_STRUCT(GPP_D10, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000), + _PAD_CFG_STRUCT(GPP_D12, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D13, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D14, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D15, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D16, 0x4000201, 0x0), + _PAD_CFG_STRUCT(GPP_D17, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D18, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D19, 0x44000500, 0x0), + _PAD_CFG_STRUCT(GPP_D20, 0x44000500, 0x0), + _PAD_CFG_STRUCT(GPP_D21, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D22, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_D23, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E0, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E1, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E2, 0x44000700, 0x3000), + _PAD_CFG_STRUCT(GPP_E3, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E4, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E5, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E6, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E7, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E9, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E10, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E11, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E12, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E15, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0), + _PAD_CFG_STRUCT(GPP_E17, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E19, 0x44000600, 0x0), + _PAD_CFG_STRUCT(GPP_E20, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_E21, 0x44000600, 0x0), + _PAD_CFG_STRUCT(GPP_E22, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_E23, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F2, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F3, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F4, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F5, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F6, 0x44000700, 0x3000), + _PAD_CFG_STRUCT(GPP_F7, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F8, 0x44000700, 0x3000), + _PAD_CFG_STRUCT(GPP_F9, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_F11, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F12, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F13, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F14, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F15, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F16, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F17, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F18, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F19, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F20, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F21, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F22, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_F23, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_G1, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), + _PAD_CFG_STRUCT(GPP_G3, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_G4, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_G5, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_G6, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_G7, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H0, 0x44000100, 0x1000), + _PAD_CFG_STRUCT(GPP_H1, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H2, 0x44000f00, 0x0), + _PAD_CFG_STRUCT(GPP_H3, 0x44000f00, 0x0), + _PAD_CFG_STRUCT(GPP_H4, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H5, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H6, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H7, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H8, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H9, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H10, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H11, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H12, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H13, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H14, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H15, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H16, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H17, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H18, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H19, 0x44000500, 0x0), + _PAD_CFG_STRUCT(GPP_H20, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H21, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H22, 0x44000100, 0x0), + _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x0), +}; + +#endif + +#endif diff --git a/system76/galp3-c/hda_verb.c b/system76/galp3-c/hda_verb.c new file mode 100644 index 0000000000..200748515f --- /dev/null +++ b/system76/galp3-c/hda_verb.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC293 */ + 0x10ec0293, /* Vendor ID */ + 0x15581323, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15581323), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x02211020), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x02a11040), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40738205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + /* Intel, KabylakeHDMI */ + 0x8086280b, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/system76/galp3-c/me b/system76/galp3-c/me new file mode 100644 index 0000000000..a0d2979eb3 Binary files /dev/null and b/system76/galp3-c/me differ diff --git a/system76/galp3-c/microcode b/system76/galp3-c/microcode new file mode 100644 index 0000000000..474ff6f815 Binary files /dev/null and b/system76/galp3-c/microcode differ diff --git a/system76/galp3-c/pxe b/system76/galp3-c/pxe new file mode 100644 index 0000000000..46e67afcf8 Binary files /dev/null and b/system76/galp3-c/pxe differ diff --git a/system76/galp3-c/vbt b/system76/galp3-c/vbt new file mode 100644 index 0000000000..df819a1076 Binary files /dev/null and b/system76/galp3-c/vbt differ diff --git a/system76/galp3-c/vga b/system76/galp3-c/vga new file mode 100644 index 0000000000..2306fd7a92 Binary files /dev/null and b/system76/galp3-c/vga differ diff --git a/system76/galp3/config b/system76/galp3/config new file mode 100644 index 0000000000..c2ce800a69 --- /dev/null +++ b/system76/galp3/config @@ -0,0 +1,862 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +CONFIG_CCACHE=y +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +# CONFIG_NO_RELOCATABLE_RAMSTAGE is not set +CONFIG_RELOCATABLE_RAMSTAGE=y +CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM=y +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_ELMEX is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SCALEWAY is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_SUPERMICRO is not set +CONFIG_VENDOR_SYSTEM76=y +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="system76/kbl-u" +CONFIG_MAINBOARD_PART_NUMBER="galp3" +CONFIG_MAX_CPUS=8 +CONFIG_CBFS_SIZE=0x600000 +CONFIG_UART_FOR_CONSOLE=2 +CONFIG_PAYLOAD_CONFIGFILE="" +CONFIG_MAINBOARD_VENDOR="System76" +CONFIG_VGA_BIOS_ID="8086,5917" +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_DIMM_SPD_SIZE=512 +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_VGA_BIOS_FILE="system76/$(VARIANT_DIR)/vga" +CONFIG_C_ENV_BOOTBLOCK_SIZE=0xC000 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1558 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1313 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="System76" +CONFIG_VARIANT_DIR="galp3" +CONFIG_DEVICETREE="devicetree.cb" +CONFIG_INTEL_GMA_VBT_FILE="system76/$(VARIANT_DIR)/vbt" +CONFIG_POST_IO=y +CONFIG_DCACHE_RAM_BASE=0xfef00000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_OVERRIDE_DEVICETREE="" +CONFIG_ME_CLEANER_ARGS="-S" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 +CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 +CONFIG_HAVE_INTEL_FIRMWARE=y +# CONFIG_POST_DEVICE is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_VBOOT is not set +CONFIG_DIMM_MAX=2 +CONFIG_TPM_PIRQ=0x0 +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_TTYS0_LCS=3 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Galago Pro" +CONFIG_IFD_BIN_PATH="system76/$(VARIANT_DIR)/descriptor" +CONFIG_ME_BIN_PATH="system76/$(VARIANT_DIR)/me" +CONFIG_HAVE_IFD_BIN=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_M_FILE="$(obj)/Fsp_M.fd" +CONFIG_FSP_S_FILE="$(obj)/Fsp_S.fd" +CONFIG_FSP_S_CBFS="fsps.bin" +CONFIG_FSP_M_CBFS="fspm.bin" +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_MAINBOARD_VERSION="galp3" +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_SMBIOS_ENCLOSURE_TYPE=0x09 +# CONFIG_BOARD_SYSTEM76_GALP2 is not set +CONFIG_BOARD_SYSTEM76_GALP3=y +# CONFIG_BOARD_SYSTEM76_GALP3_B is not set +# CONFIG_BOARD_SYSTEM76_GALP3_C is not set +# CONFIG_BOARD_SYSTEM76_DARP5 is not set +CONFIG_CONSOLE_POST=y +CONFIG_PXE_ROM_ID="10ec,8168" +CONFIG_FSP_M_XIP=y +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y +# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set +CONFIG_POWER_STATE_ON_AFTER_FAILURE=y +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=1 +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_SYSTEM_TYPE_TABLET is not set +# CONFIG_SYSTEM_TYPE_DETACHABLE is not set +# CONFIG_SYSTEM_TYPE_CONVERTIBLE is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +CONFIG_CPU_SPECIFIC_OPTIONS=y +CONFIG_HEAP_SIZE=0x80000 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x200000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" +CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120 +# CONFIG_SOC_CAVIUM_CN81XX is not set +CONFIG_ARCH_ARMV8_EXTENSION=0 +CONFIG_STACK_SIZE=0x1000 +# CONFIG_SOC_CAVIUM_COMMON is not set +# CONFIG_SOC_INTEL_GLK is not set +CONFIG_PCR_BASE_ADDRESS=0xfd000000 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/" +CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" +# CONFIG_NHLT_MAX98357 is not set +# CONFIG_NHLT_DA7219 is not set +# CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS is not set +CONFIG_IFD_CHIPSET="sklkbl" +CONFIG_CPU_BCLK_MHZ=100 +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30 +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2 +CONFIG_SOC_INTEL_I2C_DEV_MAX=6 +# CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE is not set +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_TTYS0_BASE=0x3e8 +# CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE is not set +# CONFIG_SOC_INTEL_COFFEELAKE is not set +# CONFIG_SOC_INTEL_WHISKEYLAKE is not set +# CONFIG_SOC_INTEL_CANNONLAKE_PCH_H is not set +# CONFIG_NHLT_MAX98373 is not set +CONFIG_MAX_ROOT_PORTS=24 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_SOC_INTEL_SKYLAKE=y +CONFIG_SOC_INTEL_KABYLAKE=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10 +CONFIG_MAINBOARD_USES_FSP2_0=y +CONFIG_USE_FSP2_0_DRIVER=y +# CONFIG_EXCLUDE_NATIVE_SD_INTERFACE is not set +# CONFIG_SKYLAKE_SOC_PCH_H is not set +# CONFIG_NHLT_DMIC_2CH is not set +# CONFIG_NHLT_DMIC_4CH is not set +# CONFIG_NHLT_NAU88L25 is not set +# CONFIG_NHLT_SSM4567 is not set +# CONFIG_NHLT_RT5514 is not set +# CONFIG_NHLT_RT5663 is not set +# CONFIG_NHLT_MAX98927 is not set +# CONFIG_NO_FADT_8042 is not set +CONFIG_SOC_INTEL_COMMON=y + +# +# Intel SoC Common Code +# +CONFIG_SOC_INTEL_COMMON_BLOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y +# CONFIG_INTEL_CAR_NEM is not set +# CONFIG_INTEL_CAR_CQOS is not set +CONFIG_INTEL_CAR_NEM_ENHANCED=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y +CONFIG_SOC_INTEL_COMMON_BLOCK_EBDA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y +CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y +# CONFIG_PMC_INVALID_READ_AFTER_WRITE is not set +CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0 +CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y +CONFIG_SA_PCIEX_LENGTH=0x4000000 +CONFIG_PCIEX_LENGTH_64MB=y +# CONFIG_SA_ENABLE_IMR is not set +CONFIG_SA_ENABLE_DPR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y +CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_VMX is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y + +# +# Intel SoC Common PCH Code +# +CONFIG_SOC_INTEL_COMMON_PCH_BASE=y +CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y +CONFIG_PCH_SPECIFIC_OPTIONS=y + +# +# Intel SoC Common coreboot stages +# +# CONFIG_DISPLAY_SMM_MEMORY_MAP is not set +CONFIG_SOC_INTEL_COMMON_RESET=y +CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y +# CONFIG_ACPI_CONSOLE is not set +# CONFIG_MMA is not set +# CONFIG_SOC_INTEL_COMMON_ACPI is not set +# CONFIG_SOC_INTEL_COMMON_ACPI_EC_PTS_WAK is not set +CONFIG_SOC_INTEL_COMMON_NHLT=y +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_MEDIATEK_MT8183 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_QUALCOMM_SDM845 is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_SSE2=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_MICROCODE_UPDATE_PRE_RAM=y +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +CONFIG_PARALLEL_MP=y +CONFIG_PARALLEL_MP_AP_WORK=y +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_CONSTANT_RATE=y +CONFIG_TSC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_NO_FIXED_XIP_ROM_SIZE=y +CONFIG_LOGICAL_CPUS=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_MODULE_HEAP_SIZE=0x4000 +CONFIG_SMM_STUB_STACK_SIZE=0x400 +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_NO_CAR_GLOBAL_MIGRATION=y +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set + +# +# Super I/O +# +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +# CONFIG_EC_GOOGLE_WILCO is not set +CONFIG_EC_BASE_ACPI_DATA=0x930 +CONFIG_EC_BASE_ACPI_COMMAND=0x934 +CONFIG_EC_BASE_HOST_DATA=0x940 +CONFIG_EC_BASE_HOST_COMMAND=0x944 +CONFIG_EC_BASE_PACKET=0x950 +CONFIG_SEABIOS_PS2_TIMEOUT=0 + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +CONFIG_CHECK_ME=y +CONFIG_USE_ME_CLEANER=y + +# +# Please test the modified ME/TXE firmware and coreboot in two steps +# +# CONFIG_MAINBOARD_USES_IFD_GBE_REGION is not set +# CONFIG_MAINBOARD_USES_IFD_EC_REGION is not set +# CONFIG_CAVIUM_BDK is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set +# CONFIG_UEFI_2_4_BINDING is not set +CONFIG_UDK_2015_BINDING=y +# CONFIG_UDK_2017_BINDING is not set +CONFIG_UDK_2013_VERSION=2013 +CONFIG_UDK_2015_VERSION=2015 +CONFIG_UDK_2017_VERSION=2017 +CONFIG_UDK_VERSION=2015 +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_USE_ARCH_TIMER is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_PPC64 is not set +# CONFIG_ARCH_BOOTBLOCK_PPC64 is not set +# CONFIG_ARCH_VERSTAGE_PPC64 is not set +# CONFIG_ARCH_ROMSTAGE_PPC64 is not set +# CONFIG_ARCH_RAMSTAGE_PPC64 is not set +# CONFIG_ARCH_RISCV is not set +CONFIG_ARCH_RISCV_M=y +# CONFIG_ARCH_RISCV_S is not set +# CONFIG_ARCH_RISCV_U is not set +# CONFIG_ARCH_RISCV_RV64 is not set +# CONFIG_ARCH_RISCV_RV32 is not set +# CONFIG_ARCH_RISCV_PMP is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +# CONFIG_RISCV_USE_ARCH_TIMER is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_POSTCAR_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_RAMBASE=0xe00000 +CONFIG_RAMTOP=0x1000000 +# CONFIG_CBMEM_TOP_BACKUP is not set +CONFIG_EARLY_EBDA_INIT=y +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_HPET_ADDRESS_OVERRIDE is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POSTCAR_STAGE=y +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +# CONFIG_PAGING_IN_CACHE_AS_RAM is not set +# CONFIG_IDT_IN_EVERY_STAGE is not set +CONFIG_HAVE_CF9_RESET=y + +# +# Devices +# +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_HAVE_FSP_GOP=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +# CONFIG_VGA_ROM_RUN is not set +CONFIG_RUN_FSP_GOP=y +# CONFIG_NO_GFX_INIT is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +CONFIG_PCI=y +# CONFIG_NO_MMCONF_SUPPORT is not set +CONFIG_MMCONF_SUPPORT=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_ELOG is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +CONFIG_CACHE_MRC_SETTINGS=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_MRC_SETTINGS_PROTECT=y +# CONFIG_HAS_RECOVERY_MRC_CACHE is not set +# CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN is not set +# CONFIG_MRC_SETTINGS_VARIABLE_DATA is not set +# CONFIG_MRC_WRITE_NV_LATE is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +# CONFIG_SMMSTORE is not set +# CONFIG_SMMSTORE_IN_CBFS is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_TPM_INIT=y +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +# CONFIG_HAVE_USBDEBUG is not set +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_AMD_PI is not set +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +CONFIG_DRIVERS_I2C_DESIGNWARE=y +# CONFIG_DRIVERS_I2C_DESIGNWARE_DEBUG is not set +# CONFIG_DRIVERS_I2C_MAX98373 is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCA9538 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_DRIVERS_I2C_SX9310 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set +# CONFIG_DISPLAY_HOBS is not set +# CONFIG_DISPLAY_UPD_DATA is not set +CONFIG_PLATFORM_USES_FSP2_0=y +# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set +# CONFIG_DISPLAY_FSP_HEADER is not set +CONFIG_FSP_USE_REPO=y +# CONFIG_FSP_CAR is not set +# CONFIG_FSP_T_XIP is not set +# CONFIG_FSP_USES_CB_STACK is not set +# CONFIG_VERIFY_HOBS is not set +# CONFIG_DISPLAY_FSP_VERSION_INFO is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set +# CONFIG_INTEL_GMA_SWSMISCI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_LPC_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +CONFIG_MAINBOARD_HAS_LPC_TPM=y +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_USB_ACPI is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# + +# +# Trusted Platform Module +# +CONFIG_TPM2=y +CONFIG_MAINBOARD_HAS_TPM2=y +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3e8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +# CONFIG_HAVE_OPTION_TABLE is not set +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_COMMON_FADT=y +CONFIG_ACPI_NHLT=y + +# +# System tables +# +# CONFIG_GENERATE_MP_TABLE is not set +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_BAYOU is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_LINUXBOOT is not set +CONFIG_PAYLOAD_SEABIOS=y +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_YABITS is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf" +CONFIG_SEABIOS_STABLE=y +# CONFIG_SEABIOS_MASTER is not set +# CONFIG_SEABIOS_REVISION is not set +CONFIG_SEABIOS_THREAD_OPTIONROMS=y +CONFIG_SEABIOS_VGA_COREBOOT=y +CONFIG_SEABIOS_BOOTORDER_FILE="" +# CONFIG_SEABIOS_ADD_SERCON_PORT_FILE is not set +CONFIG_PAYLOAD_VGABIOS_FILE="payloads/external/SeaBIOS/seabios/out/vgabios.bin" +CONFIG_SEABIOS_DEBUG_LEVEL=-1 + +# +# Using default SeaBIOS log level +# +CONFIG_PAYLOAD_OPTIONS="" +CONFIG_PXE=y + +# +# PXE Options +# +CONFIG_PXE_ROM=y +# CONFIG_BUILD_IPXE is not set +CONFIG_PXE_ROM_FILE="system76/$(VARIANT_DIR)/pxe" +CONFIG_PXE_SERIAL_CONSOLE=y +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +# CONFIG_PAYLOAD_FIT_SUPPORT is not set +CONFIG_COMPRESS_SECONDARY_PAYLOAD=y + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# + +# +# CPU Debug Settings +# +CONFIG_HAVE_DISPLAY_MTRRS=y +# CONFIG_DISPLAY_MTRRS is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +CONFIG_HAVE_DEBUG_GPIO=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_CBFS is not set +# CONFIG_HAVE_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +CONFIG_NO_EDID_FILL_FB=y +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +CONFIG_REG_SCRIPT=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_GENERIC_GPIO_LIB=y +CONFIG_C_ENVIRONMENT_BOOTBLOCK=y diff --git a/system76/galp3/coreboot b/system76/galp3/coreboot new file mode 100644 index 0000000000..f54c2f80d9 Binary files /dev/null and b/system76/galp3/coreboot differ diff --git a/system76/galp3/descriptor b/system76/galp3/descriptor new file mode 100644 index 0000000000..91d587336e Binary files /dev/null and b/system76/galp3/descriptor differ diff --git a/system76/galp3/flashrom b/system76/galp3/flashrom new file mode 100755 index 0000000000..46d0c94f75 Binary files /dev/null and b/system76/galp3/flashrom differ diff --git a/system76/galp3/gpio.h b/system76/galp3/gpio.h new file mode 100644 index 0000000000..18883347ac --- /dev/null +++ b/system76/galp3/gpio.h @@ -0,0 +1 @@ +./gpio.sh [coreboot-collector output] diff --git a/system76/galp3/hda_verb.c b/system76/galp3/hda_verb.c new file mode 100644 index 0000000000..3fbe5dfc33 --- /dev/null +++ b/system76/galp3/hda_verb.c @@ -0,0 +1 @@ +./hda.sh [coreboot-collector output] diff --git a/system76/galp3/me b/system76/galp3/me new file mode 100644 index 0000000000..11071a3295 Binary files /dev/null and b/system76/galp3/me differ diff --git a/system76/galp3/pxe b/system76/galp3/pxe new file mode 100644 index 0000000000..46e67afcf8 Binary files /dev/null and b/system76/galp3/pxe differ diff --git a/system76/galp3/vbt b/system76/galp3/vbt new file mode 100644 index 0000000000..5c0118036a Binary files /dev/null and b/system76/galp3/vbt differ diff --git a/system76/galp3/vga b/system76/galp3/vga new file mode 100644 index 0000000000..5618f9f789 Binary files /dev/null and b/system76/galp3/vga differ diff --git a/system76/gpio.sh b/system76/gpio.sh new file mode 100755 index 0000000000..db20d82474 --- /dev/null +++ b/system76/gpio.sh @@ -0,0 +1,58 @@ +#!/usr/bin/env bash + +set -e + +if [ ! -e "$1" ] +then + echo "$0 [coreboot-collector output]" + exit 1 +fi + +cat <<"EOF" +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include +#include + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +EOF + +grep ^GP "$1" | \ +cut -d ' ' -f1,3,4 | \ +sort -V | \ +while read line +do + parts=() + for part in $line + do + parts+=("$part") + done + echo -e "\t_PAD_CFG_STRUCT(${parts[0]}, $(printf '0x%x' "$((${parts[1]} & 0xfffffffd))"), $(printf '0x%x' "$((${parts[2]} & 0xffffff00))"))," +done + +cat <<"EOF" +}; + +#endif + +#endif +EOF diff --git a/system76/hda.sh b/system76/hda.sh new file mode 100755 index 0000000000..d8f32018e0 --- /dev/null +++ b/system76/hda.sh @@ -0,0 +1,71 @@ +#!/usr/bin/env bash + +set -e + +if [ ! -e "$1" ] +then + echo "$0 [coreboot-collector output]" + exit 1 +fi + +cat <<"EOF" +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include + +const u32 cim_verb_data[] = { +EOF + +grep "^hdaudio" "$1" | \ +while read line +do + data="$(sed -n "/^$line/,/^hdaudio/p" "$1" | grep -v "^hdaudio" | tr -d " ")" + index="$(cut -d 'D' -f2 <<< "$line")" + vendor_name="$(grep "^vendor_name:" <<< "$data" | cut -d ':' -f2)" + chip_name="$(grep "^chip_name:" <<< "$data" | cut -d ':' -f2)" + vendor_id="$(grep "^vendor_id:" <<< "$data" | cut -d ':' -f2)" + subsystem_id="$(grep "^subsystem_id:" <<< "$data" | cut -d ':' -f2)" + + widgets="$(grep "^0x" <<< "$data")" + + echo -e "\t/* $vendor_name, $chip_name */" + echo -e "\t$vendor_id, /* Vendor ID */" + echo -e "\t$subsystem_id, /* Subsystem ID */" + echo -e "\t$(($(wc -l <<<"$widgets") + 1)), /* Number of entries */" + + echo -e "\tAZALIA_SUBVENDOR($index, $subsystem_id)," + + cat <<< "$widgets" | \ + while read line + do + nid="$(cut -d ':' -f1 <<< "$line")" + pin_cfg="$(cut -d ':' -f2 <<< "$line")" + echo -e "\tAZALIA_PIN_CFG($index, $nid, $pin_cfg)," + done +done + +cat <<"EOF" +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; + +#endif +EOF diff --git a/system76/qemu/config b/system76/qemu/config new file mode 100644 index 0000000000..65c8f4059a --- /dev/null +++ b/system76/qemu/config @@ -0,0 +1,665 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +CONFIG_CCACHE=y +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_USE_OPTION_TABLE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +# CONFIG_NO_RELOCATABLE_RAMSTAGE is not set +CONFIG_RELOCATABLE_RAMSTAGE=y +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_ELMEX is not set +CONFIG_VENDOR_EMULATION=y +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SCALEWAY is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="emulation/qemu-q35" +CONFIG_MAINBOARD_PART_NUMBER="QEMU x86 q35/ich9" +CONFIG_MAX_CPUS=1 +CONFIG_CBFS_SIZE=0x800000 +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_PAYLOAD_CONFIGFILE="" +CONFIG_MAINBOARD_VENDOR="Emulation" +CONFIG_VGA_BIOS_ID="1106,3230" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_VGA_BIOS=y +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_VGA_BIOS_FILE="system76/qemu/vga" +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x4000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="System76" +CONFIG_DEVICETREE="devicetree.cb" +CONFIG_POST_IO=y +CONFIG_BOOTBLOCK_MAINBOARD_INIT="mainboard/emulation/qemu-q35/bootblock.c" +CONFIG_DCACHE_RAM_BASE=0x10000 +CONFIG_DCACHE_RAM_SIZE=0x90000 +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_OVERRIDE_DEVICETREE="" +CONFIG_FMDFILE="" +# CONFIG_BOARD_EMULATION_QEMU_ARMV7 is not set +# CONFIG_BOARD_EMULATION_QEMU_X86_I440FX is not set +# CONFIG_BOARD_EMULATION_QEMU_POWER8 is not set +CONFIG_BOARD_EMULATION_QEMU_X86_Q35=y +# CONFIG_BOARD_EMULATION_QEMU_RISCV is not set +# CONFIG_BOARD_EMULATION_SPIKE_RISCV is not set +CONFIG_BOARD_EMULATION_QEMU_X86=y +CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 +CONFIG_MMCONF_BASE_ADDRESS=0xb0000000 +# CONFIG_HAVE_INTEL_FIRMWARE is not set +CONFIG_POST_DEVICE=y +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_VBOOT is not set +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_TTYS0_LCS=3 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="qemu" +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +# CONFIG_USBDEBUG is not set +CONFIG_MAINBOARD_VERSION="1.0" +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SMBIOS_ENCLOSURE_TYPE=0x03 +# CONFIG_CONSOLE_POST is not set +CONFIG_PXE_ROM_ID="10ec,8168" +CONFIG_BOARD_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# CONFIG_SYSTEM_TYPE_LAPTOP is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +CONFIG_HEAP_SIZE=0x4000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" +# CONFIG_SOC_CAVIUM_CN81XX is not set +CONFIG_ARCH_ARMV8_EXTENSION=0 +CONFIG_STACK_SIZE=0x1000 +# CONFIG_SOC_CAVIUM_COMMON is not set +# CONFIG_SOC_INTEL_GLK is not set +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" +CONFIG_TTYS0_BASE=0x3f8 +# CONFIG_SOC_INTEL_COFFEELAKE is not set +# CONFIG_SOC_INTEL_CANNONLAKE_PCH_H is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_MEDIATEK_MT8183 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_QUALCOMM_SDM845 is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +# CONFIG_SSE2 is not set +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_QEMU_X86=y +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +# CONFIG_TSC_CONSTANT_RATE is not set +# CONFIG_TSC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +# CONFIG_TSC_SYNC_MFENCE is not set +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_NO_CAR_GLOBAL_MIGRATION=y +CONFIG_SMP=y +# CONFIG_SUPPORT_CPU_UCODE_IN_CBFS is not set +# CONFIG_USES_MICROCODE_HEADER_FILES is not set + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y + +# +# Super I/O +# +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set + +# +# Embedded Controllers +# +# CONFIG_EC_GOOGLE_WILCO is not set +CONFIG_EC_BASE_ACPI_DATA=0x930 +CONFIG_EC_BASE_ACPI_COMMAND=0x934 +CONFIG_EC_BASE_HOST_DATA=0x940 +CONFIG_EC_BASE_HOST_COMMAND=0x944 +CONFIG_EC_BASE_PACKET=0x950 +CONFIG_SEABIOS_PS2_TIMEOUT=0 +# CONFIG_CAVIUM_BDK is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set +# CONFIG_UDK_2017_BINDING is not set +CONFIG_UDK_2013_VERSION=2013 +CONFIG_UDK_2015_VERSION=2015 +CONFIG_UDK_2017_VERSION=2017 +CONFIG_UDK_VERSION=2013 +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_USE_ARCH_TIMER is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_PPC64 is not set +# CONFIG_ARCH_BOOTBLOCK_PPC64 is not set +# CONFIG_ARCH_VERSTAGE_PPC64 is not set +# CONFIG_ARCH_ROMSTAGE_PPC64 is not set +# CONFIG_ARCH_RAMSTAGE_PPC64 is not set +# CONFIG_ARCH_RISCV is not set +CONFIG_ARCH_RISCV_M=y +# CONFIG_ARCH_RISCV_S is not set +# CONFIG_ARCH_RISCV_U is not set +# CONFIG_ARCH_RISCV_RV64 is not set +# CONFIG_ARCH_RISCV_RV32 is not set +# CONFIG_ARCH_RISCV_PMP is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +# CONFIG_RISCV_USE_ARCH_TIMER is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +# CONFIG_ARCH_POSTCAR_X86_32 is not set +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_POSTCAR_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_RAMBASE=0xe00000 +CONFIG_RAMTOP=0x1000000 +# CONFIG_CBMEM_TOP_BACKUP is not set +# CONFIG_EARLY_EBDA_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +# CONFIG_HAVE_CMOS_DEFAULT is not set +CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS=y +# CONFIG_HPET_ADDRESS_OVERRIDE is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_ID_SECTION_OFFSET=0x80 +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +# CONFIG_PAGING_IN_CACHE_AS_RAM is not set +# CONFIG_IDT_IN_EVERY_STAGE is not set +CONFIG_HAVE_CF9_RESET=y + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT=y +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +CONFIG_PCI=y +# CONFIG_NO_MMCONF_SUPPORT is not set +CONFIG_MMCONF_SUPPORT=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +# CONFIG_SMMSTORE_IN_CBFS is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_VPD is not set +# CONFIG_DRIVERS_AMD_PI is not set +CONFIG_DRIVERS_EMULATION_QEMU_BOCHS=y +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_MAX98373 is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCA9538 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_DRIVERS_I2C_SX9310 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set +# CONFIG_PLATFORM_USES_FSP2_0 is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +# CONFIG_INTEL_GMA_ACPI is not set +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set +# CONFIG_INTEL_GMA_SWSMISCI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_LPC_TPM is not set +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_USB_ACPI is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# + +# +# Trusted Platform Module +# +CONFIG_USER_NO_TPM=y +# CONFIG_ACPI_SATA_GENERATOR is not set +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set +# CONFIG_RTC is not set + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_SPI_FLASH is not set +CONFIG_CONSOLE_QEMU_DEBUGCON=y +CONFIG_CONSOLE_QEMU_DEBUGCON_PORT=0x402 +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y +# CONFIG_HAVE_ACPI_RESUME is not set +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +# CONFIG_GENERATE_MP_TABLE is not set +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_BAYOU is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_LINUXBOOT is not set +CONFIG_PAYLOAD_SEABIOS=y +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_YABITS is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf" +CONFIG_SEABIOS_STABLE=y +# CONFIG_SEABIOS_MASTER is not set +# CONFIG_SEABIOS_REVISION is not set +# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set +# CONFIG_SEABIOS_VGA_COREBOOT is not set +CONFIG_SEABIOS_BOOTORDER_FILE="" +# CONFIG_SEABIOS_ADD_SERCON_PORT_FILE is not set +CONFIG_SEABIOS_DEBUG_LEVEL=-1 + +# +# Using default SeaBIOS log level +# +CONFIG_PAYLOAD_OPTIONS="" +CONFIG_PXE=y + +# +# PXE Options +# +CONFIG_PXE_ROM=y +# CONFIG_BUILD_IPXE is not set +CONFIG_PXE_ROM_FILE="system76/qemu/pxe" +CONFIG_PXE_SERIAL_CONSOLE=y +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +# CONFIG_PAYLOAD_FIT_SUPPORT is not set +CONFIG_COMPRESS_SECONDARY_PAYLOAD=y + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DEBUG_SMM_RELOCATION is not set + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +# CONFIG_HAVE_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +# CONFIG_HAVE_EM100_SUPPORT is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_NO_STAGE_CACHE=y +CONFIG_C_ENVIRONMENT_BOOTBLOCK=y diff --git a/system76/qemu/coreboot b/system76/qemu/coreboot new file mode 100644 index 0000000000..781929ec30 Binary files /dev/null and b/system76/qemu/coreboot differ diff --git a/system76/qemu/pxe b/system76/qemu/pxe new file mode 100644 index 0000000000..46e67afcf8 Binary files /dev/null and b/system76/qemu/pxe differ diff --git a/system76/qemu/vga b/system76/qemu/vga new file mode 100644 index 0000000000..0ec67b191f Binary files /dev/null and b/system76/qemu/vga differ diff --git a/system76/run.sh b/system76/run.sh new file mode 100755 index 0000000000..181b2cb7c7 --- /dev/null +++ b/system76/run.sh @@ -0,0 +1,23 @@ +#!/usr/bin/env bash + +set -e + +D="$(dirname "$(realpath "$0")")" + +for N in "$@" +do + P="$D/$N" + if [ ! -d "$P" ] + then + echo "$0 [model]" + exit 1 + fi + + kvm \ + -bios "$P/coreboot" \ + -M q35 \ + -m 2048 \ + -net nic,model=rtl8139 \ + -serial mon:stdio \ + -vga std +done