soc/amd/picasso: Move memmap_early_dram to common blocks

We need the same functionality for cezanne.

TEST=Boot ezknil

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0800c662bb473eb571c74e76a8247298f534b53f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/soc/amd/common/block/cpu/noncar/Makefile.inc

@@ -2,5 +2,7 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR),y)
 
 bootblock-y += pre_c.S
 bootblock-y += write_resume_eip.c
+romstage-y += memmap.c
+ramstage-y += memmap.c
 
 endif # CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR

src/soc/amd/common/block/cpu/noncar/memmap.c

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdint.h>
+#include <console/console.h>
+#include <cbmem.h>
+#include <amdblocks/memmap.h>
+
+void memmap_stash_early_dram_usage(void)
+{
+	struct memmap_early_dram *e;
+
+	e = cbmem_add(CBMEM_ID_CB_EARLY_DRAM, sizeof(*e));
+
+	if (!e)
+		die("ERROR: Failed to stash early dram usage!\n");
+
+	e->base = (uint32_t)(uintptr_t)_early_reserved_dram;
+	e->size = REGION_SIZE(early_reserved_dram);
+}
+
+const struct memmap_early_dram *memmap_get_early_dram_usage(void)
+{
+	struct memmap_early_dram *e = cbmem_find(CBMEM_ID_CB_EARLY_DRAM);
+
+	if (!e)
+		die("ERROR: Failed to read early dram usage!\n");
+
+	return e;
+}

src/soc/amd/common/block/include/amdblocks/memmap.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#ifndef AMD_PICASSO_MEMMAP_H
-#define AMD_PICASSO_MEMMAP_H
+#ifndef AMD_BLOCK_MEMMAP_H
+#define AMD_BLOCK_MEMMAP_H
 
 #include <stdint.h>
 #include <symbols.h>
@@ -16,4 +16,4 @@ struct memmap_early_dram {
 void memmap_stash_early_dram_usage(void);
 const struct memmap_early_dram *memmap_get_early_dram_usage(void);
 
-#endif /* AMD_PICASSO_MEMMAP_H */
+#endif /* AMD_BLOCK_MEMMAP_H */

src/soc/amd/picasso/memmap.c

@@ -4,7 +4,6 @@
 
 #include <assert.h>
 #include <stdint.h>
-#include <cbmem.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include <cpu/amd/msr.h>
@@ -12,7 +11,6 @@
 #include <memrange.h>
 #include <fsp/util.h>
 #include <FspGuids.h>
-#include <soc/memmap.h>
 
 /*
  * For data stored in TSEG, ensure TValid is clear so R/W access can reach
@@ -79,26 +77,3 @@ void bert_reserved_region(void **start, size_t *size)
 	*start = (void *)(uintptr_t)range_entry_base(&bert);
 	*size = range_entry_size(&bert);
 }
-
-void memmap_stash_early_dram_usage(void)
-{
-	struct memmap_early_dram *e;
-
-	e = cbmem_add(CBMEM_ID_CB_EARLY_DRAM, sizeof(*e));
-
-	if (!e)
-		die("ERROR: Failed to stash early dram usage!\n");
-
-	e->base = (uint32_t)(uintptr_t)_early_reserved_dram;
-	e->size = REGION_SIZE(early_reserved_dram);
-}
-
-const struct memmap_early_dram *memmap_get_early_dram_usage(void)
-{
-	struct memmap_early_dram *e = cbmem_find(CBMEM_ID_CB_EARLY_DRAM);
-
-	if (!e)
-		die("ERROR: Failed to read early dram usage!\n");
-
-	return e;
-}

src/soc/amd/picasso/romstage.c

@@ -3,6 +3,7 @@
 #include <arch/cpu.h>
 #include <acpi/acpi.h>
 #include <amdblocks/acpi.h>
+#include <amdblocks/memmap.h>
 #include <cbmem.h>
 #include <cpu/x86/cache.h>
 #include <cpu/amd/mtrr.h>
@@ -13,7 +14,6 @@
 #include <program_loading.h>
 #include <elog.h>
 #include <soc/acpi.h>
-#include <soc/memmap.h>
 #include <soc/mrc_cache.h>
 #include <soc/pci_devs.h>
 #include <types.h>

src/soc/amd/picasso/root_complex.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpigen.h>
+#include <amdblocks/memmap.h>
 #include <arch/ioapic.h>
 #include <assert.h>
 #include <cbmem.h>
@@ -12,7 +13,6 @@
 #include <device/pci_ids.h>
 #include <fsp/util.h>
 #include <stdint.h>
-#include <soc/memmap.h>
 #include <soc/iomap.h>
 #include "chip.h"