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soc/intel/apollolake: Consolidate ISH enabling

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Since the Integrated Sensor Hub can be disabled through devicetree.cb
as a PCI device, there is no need for a separate register variable.
Remove handling the register and update mainboards' devicetrees. Also
keep ISH disabled on both Reef and Amenia.

Change-Id: I90dbf57b353ae1b80295ecf39877b10ed21de146
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15710
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Andrey Petrov
2016-07-14 09:52:00 -07:00
committed by Aaron Durbin
parent d779605c29
commit 89e7b49a11
4 changed files with 2 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/mainboard/google/reef/devicetree.cb
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@@ -6,11 +6,6 @@ chip soc/intel/apollolake
register "pcie_rp4_clkreq_pin" = "0" # wifi/bt register "pcie_rp4_clkreq_pin" = "0" # wifi/bt
# TODO(furquan): Remove this once global reset issue is fixed in later
# steppings.
# Integrated Sensor Hub
register "integrated_sensor_hub_enable" = "1"
# EMMC TX DATA Delay 1# # EMMC TX DATA Delay 1#
# 0x0C[14:8] stands for 12*125 = 1500 pSec delay for HS400 # 0x0C[14:8] stands for 12*125 = 1500 pSec delay for HS400
# 0x11[6:0] stands for 17*125 = 2125 pSec delay for SDR104/HS200 # 0x11[6:0] stands for 17*125 = 2125 pSec delay for SDR104/HS200
@@ -61,7 +56,7 @@ chip soc/intel/apollolake
device generic 0 on end device generic 0 on end
end end
end end
device pci 11.0 on end # - ISH device pci 11.0 off end # - ISH
device pci 12.0 off end # - SATA device pci 12.0 off end # - SATA
device pci 13.0 off end # - Root Port 2 - PCIe-A 0 device pci 13.0 off end # - Root Port 2 - PCIe-A 0
device pci 13.1 off end # - Root Port 3 - PCIe-A 1 device pci 13.1 off end # - Root Port 3 - PCIe-A 1

5
src/mainboard/intel/amenia/devicetree.cb
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@@ -7,9 +7,6 @@ chip soc/intel/apollolake
register "pcie_rp0_clkreq_pin" = "3" # wifi/bt register "pcie_rp0_clkreq_pin" = "3" # wifi/bt
register "pcie_rp2_clkreq_pin" = "0" # SSD register "pcie_rp2_clkreq_pin" = "0" # SSD
# Integrated Sensor Hub
register "integrated_sensor_hub_enable" = "0"
# EMMC TX DATA Delay 1# # EMMC TX DATA Delay 1#
# 0x1A[14:8] stands for 26*125 = 3250 pSec delay for HS400 # 0x1A[14:8] stands for 26*125 = 3250 pSec delay for HS400
# 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200 # 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200
@@ -43,7 +40,7 @@ chip soc/intel/apollolake
device generic 0 on end device generic 0 on end
end end
end end
device pci 11.0 on end # - ISH device pci 11.0 off end # - ISH
device pci 12.0 on end # - SATA device pci 12.0 on end # - SATA
device pci 13.0 off end # - PCIe-A 0 device pci 13.0 off end # - PCIe-A 0
device pci 13.1 off end # - PCIe-A 1 device pci 13.1 off end # - PCIe-A 1

2
src/soc/intel/apollolake/chip.c
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@@ -396,8 +396,6 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
if (cfg->emmc_rx_cmd_data_cntl2 != 0) if (cfg->emmc_rx_cmd_data_cntl2 != 0)
silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2; silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2;
silconfig->IshEnable = cfg->integrated_sensor_hub_enable;
silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable;
/* Disable setting of EISS bit in FSP. */ /* Disable setting of EISS bit in FSP. */

3
src/soc/intel/apollolake/chip.h
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@@ -93,9 +93,6 @@ struct soc_intel_apollolake_config {
/* Configure serial IRQ (SERIRQ) line. */ /* Configure serial IRQ (SERIRQ) line. */
enum serirq_mode serirq_mode; enum serirq_mode serirq_mode;
/* Integrated Sensor Hub */
uint8_t integrated_sensor_hub_enable;
/* I2C bus configuration */ /* I2C bus configuration */
struct apollolake_i2c_config i2c[APOLLOLAKE_I2C_DEV_MAX]; struct apollolake_i2c_config i2c[APOLLOLAKE_I2C_DEV_MAX];