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intel car: Unify postcodes

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Not all are matched, but this makes it easier to backport
MTRR changes from haswell.

Change-Id: Ida5943b1469fc0089a31ff3b18131fb82b0941c6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15760
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki
2016-07-20 13:29:59 +03:00
parent eb61ea84f7
commit 8a2f167e7b
5 changed files with 22 additions and 27 deletions
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6
src/cpu/intel/model_2065x/cache_as_ram.inc
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@@ -150,8 +150,6 @@ clear_var_mtrrs:
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
post_code(0x27)
post_code(0x28)
/* Enable cache. */
movl %cr0, %eax
@@ -177,8 +175,6 @@ before_romstage:
*/
movl %eax, %ebx
post_code(0x2f)
post_code(0x30)
/* Disable cache. */
@@ -194,7 +190,7 @@ before_romstage:
andl $(~MTRR_DEF_TYPE_EN), %eax
wrmsr
post_code(0x31)
post_code(0x32)
/* Disable the no eviction run state */
movl $NoEvictMod_MSR, %ecx