From 8a6907c59219787d32608e1579b431a0ea2bffe4 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Fri, 18 Jun 2021 12:40:38 -0600 Subject: [PATCH] include/pci_def.h: Add some PCI Power Management CSR bits Signed-off-by: Tim Wawrzynczak Change-Id: I84c8470764a4e6e09220044966111ffe72078099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55674 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/include/device/pci_def.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index d18e750520..22a5390e05 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -233,6 +233,10 @@ #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ #define PCI_PM_CTRL 4 /* PM control and status register */ #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ +#define PCI_PM_CTRL_POWER_STATE_D0 0x0 +#define PCI_PM_CTRL_POWER_STATE_D1 0x1 +#define PCI_PM_CTRL_POWER_STATE_D2 0x2 +#define PCI_PM_CTRL_POWER_STATE_D3HOT 0x3 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */