diff --git a/3rdparty/blobs b/3rdparty/blobs index d7600dd871..62aa0e0c54 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit d7600dd8718a076f0f9a89e53968b484254624dc +Subproject commit 62aa0e0c54295bbb7b1a3e5e73f960bafdb59d04 diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index b3b9fa34bb..a815704c84 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit b3b9fa34bb99d33d0fc6a69c64966a71cebd5bd6 +Subproject commit a815704c84b4823f5b723404a37efed9d6c85d66 diff --git a/3rdparty/opensbi b/3rdparty/opensbi index 804b997ed4..ce228ee091 160000 --- a/3rdparty/opensbi +++ b/3rdparty/opensbi @@ -1 +1 @@ -Subproject commit 804b997ed415001097803e4b537fd63d043874b9 +Subproject commit ce228ee0919deb9957192d723eecc8aaae2697c6 diff --git a/3rdparty/vboot b/3rdparty/vboot index dac763c782..9c90611097 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit dac763c782ce05476dec02e855f349d2b6f3a910 +Subproject commit 9c906110972f538ee5753845916ebd1f826f54b6 diff --git a/AUTHORS b/AUTHORS new file mode 100644 index 0000000000..c5fec189ab --- /dev/null +++ b/AUTHORS @@ -0,0 +1,14 @@ +# This is the list of coreboot authors for copyright purposes. +# +# This does not necessarily list everyone who has contributed code, since in +# some cases, their employer may be the copyright holder. To see the full list +# of contributors, see the revision history in source control. +# git log --pretty=format:%an | sort | uniq +# + +Alexander Couzens + + + +# Directories transferred +src/acpi diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index fff536b9b1..6b1bb30740 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -148,7 +148,6 @@ mv build/coreboot.rom.new build/coreboot.rom
  • Edit the src/soc/<Vendor>/<Chip Family>/memmap.c file
    1. Add the fsp/memmap.h include file
      2. -
    2. Add the mmap_region_granularity routine
  • Add the necessary .h files to define the necessary values and structures
    • diff --git a/Documentation/arch/riscv/index.md b/Documentation/arch/riscv/index.md index 9a5de34f09..ea6a5cd47e 100644 --- a/Documentation/arch/riscv/index.md +++ b/Documentation/arch/riscv/index.md @@ -23,8 +23,20 @@ On entry to a stage or payload (including SELF payloads), ## Additional payload handoff requirements The location of cbmem should be placed in a node in the FDT. +## OpenSBI +In case the payload doesn't install it's own SBI, like the [RISCV-PK] does, +[OpenSBI] can be used instead. +It's loaded into RAM after coreboot has finished loading the payload. +coreboot then will jump to OpenSBI providing a pointer to the real payload, +which OpenSBI will jump to once the SBI is installed. + +Besides providing SBI it also sets protected memory regions and provides +a platform independent console. + +The OpenSBI code is always run in M mode. + ## Trap delegation -Traps are delegated in the ramstage. +Traps are delegated to the payload. ## SMP within a stage At the beginning of each stage, all harts save 0 are spinning in a loop on @@ -44,3 +56,6 @@ The hart blocks until fn is non-null, and then calls it. If fn returns, we will panic if possible, but behavior is largely undefined. Only hart 0 runs through most of the code in each stage. + +[RISCV-PK]: https://github.com/riscv/riscv-pk +[OpenSBI]: https://github.com/riscv/opensbi diff --git a/Documentation/community/code_of_conduct.md b/Documentation/community/code_of_conduct.md index c40393f919..249a575f0d 100644 --- a/Documentation/community/code_of_conduct.md +++ b/Documentation/community/code_of_conduct.md @@ -22,19 +22,30 @@ Refrain from insulting anyone or the group they belong to. Remember that people might be sensitive to other things than you are. Most of our community members are not native English speakers, thus -misunderstandings can (and do) happen. Always assume that others are -friendly and may have picked less-than-stellar wording by accident. +misunderstandings can (and do) happen. Assume that others are friendly +and may have picked less-than-stellar wording by accident as long as +you possibly can. -If you have a grievance due to conduct in this community, we want to hear -about it so we can handle the situation. Please contact our arbitration -team directly: They will listen to you and react in a timely fashion. +## Reporting Issues + +If you have a grievance due to conduct in this community, we're sorry +that you have had a bad experience, and we want to hear about it so +we can resolve the situation. + +Please contact members of our arbitration team (listed below) promptly +and directly, in person (if available) or by email: They will listen +to you and react in a timely fashion. + +If you feel uncomfortable, please don't wait it out, ask for help, +so we can work on setting things right. For transparency there is no alias or private mailing list address for you to reach out to, since we want to make sure that you know who will -(and who won't) read your message. +and who won't read your message. -However since people might be on travel or otherwise be unavailable at -times, consider reaching out to multiple persons. +However since people might be on travel or otherwise be unavailable +at times, please reach out to multiple persons at once, especially +when using email. The team will treat your messages confidential as far as the law permits. For the purpose of knowing what law applies, the list provides the usual @@ -73,15 +84,10 @@ immediately. If a community member engages in unacceptable behavior, the community organizers may take any action they deem appropriate, up to and including a temporary ban or permanent expulsion from the community without warning -(and without refund in the case of a paid event). Community organizers -can be part of the arbitration team, or organizers of events and online -communities. - -## If You Witness or Are Subject to Unacceptable Behavior - -If you are subject to or witness unacceptable behavior, or have any other -concerns, please notify someone from the arbitration team immediately. +(and without refund in the case of a paid event). +Community organizers can be members of the arbitration team, or organizers +of events and online communities. ## Addressing Grievances @@ -102,7 +108,7 @@ Our arbitration team consists of the following people * Stefan Reinauer (USA) * Patrick Georgi (Germany) * Ronald Minnich (USA) -* Marc Jones (USA) +* Martin Roth (USA) ## License and attribution diff --git a/Documentation/distributions.md b/Documentation/distributions.md index 1deff6349d..fbfeb7c378 100644 --- a/Documentation/distributions.md +++ b/Documentation/distributions.md @@ -58,16 +58,6 @@ fixes not found in the stock firmware, and offer much broader OS compatibility microcode, as well as firmware updates for the device's embedded controller (EC). This firmware "takes the training wheels off" your ChromeOS device :) -### John Lewis - -[John Lewis](https://johnlewis.ie/custom-chromebook-firmware) also provides -replacement firmware for ChromeOS devices, for the express purpose of -running Linux on Chromebooks. John Lewis' firmware supports a much smaller -set of devices, and uses SeaBIOS as the payload to support Legacy BIOS booting. -His firmware images are significantly older, and not actively maintained or -supported, but worth a look if you need Legacy Boot support and is not -available via Mr Chromebox's firmware. - ### Heads [Heads](http://osresearch.net) is an open source custom firmware and OS diff --git a/Documentation/drivers/index.md b/Documentation/drivers/index.md index 642ae1a5f3..60e90c3bf6 100644 --- a/Documentation/drivers/index.md +++ b/Documentation/drivers/index.md @@ -1,4 +1,4 @@ -# Platform indenpendend drivers documentation +# Platform independent drivers documentation The drivers can be found in `src/drivers`. They are intended for onboard and plugin devices, significantly reducing integration complexity and diff --git a/Documentation/lessons/lesson1.md b/Documentation/lessons/lesson1.md index 2ca25b3b25..bbb3eb5582 100644 --- a/Documentation/lessons/lesson1.md +++ b/Documentation/lessons/lesson1.md @@ -1,5 +1,5 @@ -coreboot lesson 1 - Starting from scratch -========================================= +coreboot Lesson 1: Starting from scratch +======================================== From a fresh Ubuntu 16.04 or 18.04 install, here are all the steps required for a very basic build: diff --git a/Documentation/lib/payloads/fit.md b/Documentation/lib/payloads/fit.md index 24807bfc6a..57a1a54566 100644 --- a/Documentation/lib/payloads/fit.md +++ b/Documentation/lib/payloads/fit.md @@ -6,6 +6,7 @@ ## Supported architectures * aarch64 +* riscv ## Supported FIT sections @@ -24,6 +25,7 @@ The section must be named in order to be found by the FIT parser: ## Architecture specifics The FIT parser needs architecure support. + ### aarch64 The source code can be found in `src/arch/arm64/fit_payload.c`. @@ -31,6 +33,13 @@ On aarch64 the kernel (a section named 'kernel') must be in **Image** format and it needs a devicetree (a section named 'fdt') to boot. The kernel will be placed close to "*DRAMSTART*". +### RISC-V +The source code can be found in `src/arch/riscv/fit_payload.c`. + +On RISC-V the kernel (a section named 'kernel') must be in **Image** +format and it needs a devicetree (a section named 'fdt') to boot. +The kernel will be placed close to "*DRAMSTART*". + ### Other Other architectures aren't supported. diff --git a/Documentation/mainboard/emulation/qemu-aarch64.md b/Documentation/mainboard/emulation/qemu-aarch64.md new file mode 100644 index 0000000000..ee4c9e7a3b --- /dev/null +++ b/Documentation/mainboard/emulation/qemu-aarch64.md @@ -0,0 +1,47 @@ +# QEMU AArch64 emulator +This page discribes how to build and run coreboot for QEMU/AArch64. +You can use LinuxBoot via `make menuconfig` or an arbitrary FIT image +as a payload for QEMU/AArch64. + +## Running coreboot in QEMU +```bash +qemu-system-aarch64 -bios ./build/coreboot.rom \ + -M virt,secure=on,virtualization=on -cpu cortex-a53 \ + -nographic -m 8912M +``` + +- The default CPU in QEMU for AArch64 is a cortex-a15 which is 32-bit +ARM CPU. You need to specify 64-bit ARM CPU via `-cpu cortex-a53`. +- The default privilege level in QEMU for AArch64 is EL1 that we can't +have the right to access EL3/EL2 registers. You need to enable EL3/EL2 +via `-machine secure=on,virtualization=on`. +- You need to specify the size of memory more than 544 MiB because 512 +MiB is reserved for the kernel. + +## Building coreboot with an arbitrary FIT payload +There are 3 steps to make coreboot.rom for QEMU/AArch64. If you select +LinuxBoot, step 2 and 3 have done by LinuxBoot. +1. Get a DTB (Device Tree Blob) +2. Build a FIT image with a DTB +3. Add a FIT image to coreboot.rom + +### 1. Get a DTB +You can get the DTB from QEMU with the following command. +``` +$ qemu-system-aarch64 \ + -M virt,dumpdtb=virt.dtb,secure=on,virtualization=on \ + -cpu cortex-a53 -nographic -m 2048M +``` + +### 2. Build a FIT image with a DTB +You need to write an image source file that has an `.its` extension to +configure kernels, ramdisks, and DTBs. +See [Flattened uImage Tree documentation](../../lib/payloads/fit.md) for more details. + +### 3. Add a FIT image to coreboot.rom +You can use cbfstool to add the payload you created in step 2 to +the coreboot.rom. +``` +$ ./build/cbfstool ./build/coreboot.rom add -f /uImage \ + -n fallback/payload -t fit -c lzma +``` diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 14c62edeb9..0f3105f85b 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -24,6 +24,7 @@ The boards in this section are not real mainboards, but emulators. - [Spike RISC-V emulator](emulation/spike-riscv.md) - [Qemu RISC-V emulator](emulation/qemu-riscv.md) +- [Qemu AArch64 emulator](emulation/qemu-aarch64.md) ## Intel @@ -69,6 +70,10 @@ The boards in this section are not real mainboards, but emulators. - [T4xx common](lenovo/t4xx_series.md) - [X2xx common](lenovo/x2xx_series.md) +## Portwell + +- [PQ7-M107](portwell/pq7-m107.md) + ### Sandy Bridge series - [T420](lenovo/t420.md) diff --git a/Documentation/mainboard/portwell/pq7-m107.md b/Documentation/mainboard/portwell/pq7-m107.md new file mode 100644 index 0000000000..e4da415bf4 --- /dev/null +++ b/Documentation/mainboard/portwell/pq7-m107.md @@ -0,0 +1,79 @@ +# Portwell PQ7-M107 + +This page describes how to run coreboot on the [Portwell PQ7-M107]. + +PQ7-M107 are assembled with different onboard memory modules: + Rev 1.0 Onboard Samsung K4B8G1646D-MYKO memory + Rev 1.1 and 1.2 Onboard Micron MT41K512M16HA-125A memory + +Use 'make menuconfig' to configure `onboard memory manufacture` in Mainboard +menu. + +## Required blobs + +This board currently requires: +fsp blob 3rdparty/fsp/BraswellFspBinPkg/FspBin/BSWFSP.fd +Microcode Intel Braswell cpuid 1046C4 version 410 + (Used pre-built binary retrieved from Intel site) + +## Flashing coreboot + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. + +### External programming + +The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip. +This chip is located on the top middle side of the board. It's located +between SoC and Q7 connector. Use clip (or solder wires) to program +the chip. +Specifically, it's a Winbond W25Q64FW (1.8V), whose datasheet can be found +[here][W25Q64FW]. + +## Known issues + +- The PQ7 module contains Q7 connector only. Depending on the carrier +serial/video/pcie ports might be available. + +## Untested + +- hardware monitor +- SDIO +- Full Embedded Controller support + +## Working (using carrier) + +- USB +- Gigabit Ethernet +- integrated graphics +- flashrom +- external graphics +- PCIe +- eMMC +- SATA +- serial port +- SMbus +- HDA (codec on carrier) +- initialization with FSP MR2 +- SeaBIOS payload (version rel-1.11.0-44-g7961917) +- Embedded Linux (Ubuntu 4.15+) + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| SoC | Intel Atom Processor N3710 | ++------------------+--------------------------------------------------+ +| CPU | Intel Braswell (N3710) | ++------------------+--------------------------------------------------+ +| Super I/O, EC | ITE8256 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[Portwell PQ7-M107]: http://portwell.com/products/detail.php?CUSTCHAR1=PQ7-M107 +[W25Q64FW]: https://www.winbond.com/resource-files/w25q64fw%20revn%2005182017%20sfdp.pdf +[flashrom]: https://flashrom.org/Flashrom +[Board manual]: www.portwell.com/pdf/embedded/PQ7-M107.pdf diff --git a/Documentation/mainboard/sifive/hifive-unleashed.md b/Documentation/mainboard/sifive/hifive-unleashed.md index 495dade212..4dbbf0e073 100644 --- a/Documentation/mainboard/sifive/hifive-unleashed.md +++ b/Documentation/mainboard/sifive/hifive-unleashed.md @@ -17,7 +17,6 @@ The following things are still missing from this coreboot port: - Provide serial number to payload (e.g. in device tree) - Implement instruction emulation - Support for booting Linux on RISC-V -- Add support to run OpenSBI payload in m-mode - SMP support in trap handler ## Configuration diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md index f03f87d937..ad00ce8de7 100644 --- a/Documentation/releases/checklist.md +++ b/Documentation/releases/checklist.md @@ -68,6 +68,7 @@ be more frequent than was needed, so we scaled it back to twice a year. - [ ] Announce that the release tag is done on IRC - [ ] Update release notes with actual commit id, push to repo - [ ] Upload release files to web server +- [ ] Upload crossgcc sources to web server - [ ] Update download page to point to files, push to repo - [ ] Write and publish blog post with release notes. - [ ] Update the topic in the irc channel that the release is done. @@ -195,6 +196,22 @@ The downloads page is the official place to download the releases from, and it n Here is an example commit to change it: https://review.coreboot.org/#/c/19515/ +## Upload crossgcc sources +Sometimes the source files for older revisions of +crossgcc disappear. To deal with that we maintain a mirror at +https://www.coreboot.org/releases/crossgcc-sources/ where we host the +sources used by the crossgcc scripts that are part of coreboot releases. + +Run + +```` +% util/crossgcc/buildgcc -u +```` + +This will output the set of URLs that the script uses to download the +sources. Download them yourself and copy them into the crossgcc-sources +directory on the server. + ## After the release is complete Post the release notes on https://blogs.coreboot.org diff --git a/Documentation/releases/coreboot-4.10-relnotes.md b/Documentation/releases/coreboot-4.10-relnotes.md index 9a6d63c16c..0f935c21cc 100644 --- a/Documentation/releases/coreboot-4.10-relnotes.md +++ b/Documentation/releases/coreboot-4.10-relnotes.md @@ -1,18 +1,39 @@ -Upcoming release - coreboot 4.10 +coreboot 4.10 release notes =========================== -The 4.10 release is planned for April/May 2019 +The 4.10 release covers commit a2faaa9a2 to commit ae317695e3 +There is a pgp signed 4.10 tag in the git repository, and a branch will +be created as needed. -Update this document with changes that should be in the release -notes. -* Please use Markdown. -* See the [4.7](coreboot-4.7-relnotes.md) and [4.9](coreboot-4.9-relnotes.md) - release notes for the general format. -* The chip and board additions and removals will be updated right -before the release, so those do not need to be added. +In nearly 8 months since 4.9 we had 198 authors commit 2538 changes +to master. Of these, 85 authors made their first commit to coreboot: +Welcome! -Significant changes -------------------- +Between the releases the tree grew by about 11000 lines of code plus +5000 lines of comments. + +Again, a big Thank You to all contributors who helped shape the coreboot +project, community and code with their effort, no matter if through +development, review, testing, documentation or by helping people asking +questions on our venues like IRC or our mailing list. + +What's New +---------- + +Most of the changes were to mainboards, and on the chipset side, lots +of activity concentrated on x86. However compared to previous releases +activity (and therefore interest, probably) increased in vboot and in +non-x86 architectures. However it's harder this time to give this release +a single topic like the last: This release accumulates some of everything. + +Clean Up +-------- +As usual, there was a lot of cleaning up going on, and there notably, +a good chunk of this year's Google Summer of Code project to clean out +the issues reported by Coverity Scan is already in. + +The only larger scale change that was registered in the pre-release +notes was also about cleaning up the tree: ### `device_t` is no more coreboot used to have a data type, `device_t` that changed shape depending on @@ -22,3 +43,97 @@ time when romstage wasn't operated in Cache-As-RAM mode, but compiled with our romcc compiler. That data type is now gone. + +Release Notes maintenance +------------------------- +Speaking of pre-release notes: After 4.10 we'll start a document for +4.11 in the git repository. Feel free to add notable achievements there +so we remember to give them a shout out in the next release's notes. + +Known Issues +------------ +Sadly, Google Cyan is broken in this release. It doesn't work with the +"C environment" bootblock (as compared to the old romcc type bootblock) +which is now the default. Sadly it doesn't help to simply revert that +change because doing so breaks other boards. + +If you want to use Google Cyan with the release (or if +you're tracking the master branch), please keep an eye on +https://review.coreboot.org/c/coreboot/+/34304 where a solution for this +issue is sought. + +Deprecations +------------ +As announced in the 4.9 release notes, there are no deprecations after 4.10. +While 4.10 is also released late and we target a 4.11 release in October we +nonetheless want to announce deprecations this time: These are under +discussion since January, people are working on mitigations for about as long +and so it should be possible to resolve the outstanding issues by the end of +October. + +Specifically, we want to require code to work with the following Kconfig +options so we can remove the options and the code they disable: + +* C\_ENVIRONMENT\_BOOTBLOCK +* NO\_CAR\_GLOBAL\_MIGRATION +* RELOCATABLE\_RAMSTAGE + +These only affect x86. If your platform only works without them, please +look into fixing that. + +Added 28 mainboards: +-------------------- +* ASROCK H110M-DVS +* ASUS H61M-CS +* ASUS P5G41T-M-LX +* ASUS P5QPL-AM +* ASUS P8Z77-M-PRO +* FACEBOOK FBG1701 +* FOXCONN G41M +* GIGABYTE GA-H61MA-D3V +* GOOGLE BLOOG +* GOOGLE FLAPJACK +* GOOGLE GARG +* GOOGLE HATCH-WHL +* GOOGLE HELIOS +* GOOGLE KINDRED +* GOOGLE KODAMA +* GOOGLE KOHAKU +* GOOGLE KRANE +* GOOGLE MISTRAL +* HP COMPAQ-8200-ELITE-SFF-PC +* INTEL COMETLAKE-RVP +* INTEL KBLRVP11 +* LENOVO R500 +* LENOVO X1 +* MSI MS7707 +* PORTWELL M107 +* PURISM LIBREM13-V4 +* PURISM LIBREM15-V4 +* SUPERMICRO X10SLM-PLUS-F +* UP SQUARED + +Removed 7 mainboards: +--------------------- +* GOOGLE BIP +* GOOGLE DELAN +* GOOGLE ROWAN +* PCENGINES ALIX1C +* PCENGINES ALIX2C +* PCENGINES ALIX2D +* PCENGINES ALIX6 + +Removed 3 processors: +--------------------- +* src/cpu/amd/geode\_lx +* src/cpu/intel/model\_69x +* src/cpu/intel/model\_6dx + +Added 2 socs: +------------- +* src/soc/amd/picasso +* src/soc/qualcomm/qcs405 + +Toolchain +--------- +* Update to gcc 8.3.0, binutils 2.32, IASL 20190509, clang 8 diff --git a/Documentation/releases/coreboot-4.11-relnotes.md b/Documentation/releases/coreboot-4.11-relnotes.md new file mode 100644 index 0000000000..995a8e7eea --- /dev/null +++ b/Documentation/releases/coreboot-4.11-relnotes.md @@ -0,0 +1,17 @@ +Upcoming release - coreboot 4.11 +================================ + +The 4.11 release is planned for October 2019 + +Update this document with changes that should be in the release +notes. +* Please use Markdown. +* See the [4.9](coreboot-4.9-relnotes.md) and [4.10](coreboot-4.10-relnotes.md) + release notes for the general format. +* The chip and board additions and removals will be updated right + before the release, so those do not need to be added. + +Significant changes +------------------- + +### Add significant changes here diff --git a/Documentation/security/index.md b/Documentation/security/index.md index 379375b616..d5d4e2b93e 100644 --- a/Documentation/security/index.md +++ b/Documentation/security/index.md @@ -7,3 +7,9 @@ This section describes documentation about the security architecture of coreboot - [Verified Boot](vboot/index.md) - [Measured Boot](vboot/measured_boot.md) - [Memory clearing](memory_clearing.md) + +## Intel TXT + +- [Intel TXT in general](intel/txt.md) +- [Intel TXT Initial Boot Block](intel/txt_ibb.md) +- [Intel Authenticated Code Modules](intel/acm.md) diff --git a/Documentation/security/intel/acm.md b/Documentation/security/intel/acm.md new file mode 100644 index 0000000000..b7dfacde8c --- /dev/null +++ b/Documentation/security/intel/acm.md @@ -0,0 +1,57 @@ +# Intel Authenticated Code Modules + +The Authenticated Code Modules (ACMs) are Intel digitally signed modules +that contain code to be run before the traditional x86 CPU reset vector. +The ACMs can be invoked at runtime through the GETSEC instruction, too. + +A platform that wants to use Intel TXT must use two ACMs: +1. BIOS ACM + * The BIOS ACM must be present in the boot flash. + * The BIOS ACM must be referenced by the [FIT]. +2. SINIT ACM + * The SINIT ACM isn't referenced by the [FIT]. + * The SINIT ACM should be provided by the boot firmware, but bootloaders + like [TBOOT] are able to load them from the filesystem as well. + +## Retrieving ACMs + +The ACMs can be downloaded on Intel's website: +[Intel Trusted Execution Technology](https://software.intel.com/en-us/articles/intel-trusted-execution-technology) + +If you want to extract the BLOB from vendor firmware you can search for the +string ``LCP_POLICY_DATA`` or ``TXT``. + +## Header + +Every ACM has a fixed size header: + +```c +/* + * ACM Header v0.0 without dynamic part + * Chapter A.1 + * Intel TXT Software Development Guide (Document: 315168-015) + */ +struct acm_header_v0 { + uint16_t module_type; + uint16_t module_sub_type; + uint32_t header_len; + uint16_t header_version[2]; + uint16_t chipset_id; + uint16_t flags; + uint32_t module_vendor; + uint32_t date; + uint32_t size; + uint16_t txt_svn; + uint16_t se_svn; + uint32_t code_control; + uint32_t error_entry_point; + uint32_t gdt_limit; + uint32_t gdt_ptr; + uint32_t seg_sel; + uint32_t entry_point; + uint8_t reserved2[63]; +} __packed; +``` + +[FIT]: ../../soc/intel/fit.md +[TBOOT]: https://sourceforge.net/p/tboot/wiki/Home/ diff --git a/Documentation/security/intel/fit_ibb.dia b/Documentation/security/intel/fit_ibb.dia new file mode 100644 index 0000000000..9d389e1e9b Binary files /dev/null and b/Documentation/security/intel/fit_ibb.dia differ diff --git a/Documentation/security/intel/fit_ibb.svg b/Documentation/security/intel/fit_ibb.svg new file mode 100644 index 0000000000..cadf2cde6c --- /dev/null +++ b/Documentation/security/intel/fit_ibb.svg @@ -0,0 +1,153 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + 4 GiB + + + FIT Ptr + + + IA32 reset vec + + + + + + + + + + + + + + + + + + + + BIOS ACM + + + BOOTBLOCK + CODE + + + uCode + + + + + + + + + + + + + + + + + + + + + + + + + + + uCode + + + + + + + + + + + + + + verstage + + + FSP + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IBB + + + IBB + + + IBB + + + type 7 + + + type 7 + + + type 7 + + + + diff --git a/Documentation/security/intel/txt.md b/Documentation/security/intel/txt.md new file mode 100644 index 0000000000..f67b63942e --- /dev/null +++ b/Documentation/security/intel/txt.md @@ -0,0 +1,117 @@ +# Intel Trusted Execution Technology + +Intel TXT allows +1. Attestation of the authenticity of a platform and its operating system. +2. Assuring that an authentic operating system starts in a + trusted environment, which can then be considered trusted. +3. Providing of a trusted operating system with additional + security capabilities not available to an unproven one. + +Intel TXT requirements: + +1. Intel TXT requires a **TPM** to measure parts of the firmware before it's + run on the BSP. +2. Intel TXT requires signed **Authenticated Code Modules** ([ACM]s), provided + by Intel. +3. Intel TXT requires **CPU and Chipset** support (supported since + Intel Core 2 Duo/ICH9). + +## Authenticated Code Modules + +The ACMs are Intel digitally signed modules that contain code to be run +before the traditional x86 CPU reset vector. + +More details can be found here: [Intel ACM]. + +## Modified bootflow with Intel TXT + +With Intel TXT the first instruction executed on the BSP isn't the +*reset vector*, but the [Intel ACM]. +It initializes the TPM and measures parts of the firmware, the IBB. + +### Marking the Initial Boot Block + +Individual files in the CBFS can be marked as IBB. + +More details can be found in the [Intel TXT IBB] chapter. + +### Measurements +The IBBs (Initial Boot Blocks) are measured into TPM's PCR0 by the BIOS [ACM] +before the CPU reset vector is executed. To indentify the regions that need +to be measured, the [FIT] contains one ore multiple *Type 7* entries, that +point to the IBBs. + +### Authentication + +After the IBBs have been measured, the ACM decides if the boot firmware is +trusted. There exists two validation modes: +1. HASH Autopromotion + * Uses a known good HASH stored in TPM NVRAM + * Doesn't allow to boot a fallback IBB +2. Signed BIOS policy + * Uses a signed policy stored in flash containing multiple HASHes + * The public key HASH of BIOS policy is burned into TPM by manufacturer + * Can be updated by firmware + * Allows to boot a fallback IBB + +At the moment only *Autopromotion mode* is implemented and tested well. + +In the next step the ACM terminates and the regular x86 CPU reset vector +is being executed on the BSP. + +### Protecting Secrets in Memory + +Intel TXT sets the `Secrets in Memory` bit, whenever the launch of the SINIT +ACM was successful. +The bit is reset when leaving the *MLE* by a regular shutdown or by removing +the CMOS battery. + +When `Secrets in Memory` bit is set and the IBB isn't trusted, the memory +controller won't be unlocked, resulting in a platform that cannot access DRAM. + +When `Secrets in Memory` bit is set and the IBB is trusted, the memory +controller will be unlocked, and it's the responsibility of the firmware to +[clear all DRAM] and wipe any secrets of the MLE. +The platform will be reset after all DRAM has been wiped and will boot +with the `Secrets in Memory` bit cleared. + +### Configuring protected regions for SINIT ACM + +The memory regions used by the SINIT ACM need to be prepared and protected +against DMA attacks. +The SINIT ACM as well as the SINIT handoff data are placed in memory. + +### Locking TXT register + +As last step the TXT registers are locked. + +Whenever the SINIT ACM is invoked, it verifies that the hardware is in the +correct state. If it's not the SINIT ACM will reset the platform. + +## For developers +### Configuring Intel TXT in Kconfig +Enable ``TEE_INTEL_TXT`` and set the following: + +``TEE_INTEL_TXT_BIOSACM_FILE`` to the path of the BIOS ACM provided by Intel + +``TEE_INTEL_TXT_SINITACM_FILE`` to the path of the SINIT ACM provided by Intel +### Print TXT status as early as possible +Add platform code to print the TXT status as early as possible, as the register +is cleared on cold reset. + +## References +More information can be found here: +* [Intel TXT Software Development Guide] +* [Intel TXT enabling] +* [FIT] +* [Intel TXT Lab Handout] + +[Intel TXT IBB]: txt_ibb.md +[FIT]: ../../soc/intel/fit.md +[Intel ACM]: acm.md +[ACM]: acm.md +[FIT table]: ../../soc/intel/fit.md +[clear all DRAM]: ../memory_clearing.md +[Intel TXT Lab Handout]: https://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Handout.pdf +[Intel TXT Software Development Guide]: https://www.intel.com/content/dam/www/public/us/en/documents/guides/intel-txt-software-development-guide.pdf +[Intel TXT enabling]: https://www.intel.com/content/dam/www/public/us/en/documents/guides/txt-enabling-guide.pdf diff --git a/Documentation/security/intel/txt_ibb.md b/Documentation/security/intel/txt_ibb.md new file mode 100644 index 0000000000..56cee8dca5 --- /dev/null +++ b/Documentation/security/intel/txt_ibb.md @@ -0,0 +1,39 @@ +# Intel TXT Initial Boot Block + +The Initial Boot Block (IBB) consists out of one or more files in the CBFS. + +## Constraints + +The IBB must follow the following constrains: +* One IBB must contain the reset vector as well as the [FIT table]. +* The IBB should be as small as possible. +* The IBBs must not overlap each other. +* The IBB might overlap with microcode. +* The IBB must not overlap the BIOS ACM. +* The IBB size must be a multiple of 16. +* Either one of the following: + * The IBB must be able to train the main system memory and clear all secrets. + * If the IBB cannot train the main system memory it must verify the code + that can train the main system memory and is able to clear all secrets. + +## Identification + +To add the IBBs to the [FIT], all CBFS files are added using the `cbfstool` +with the `--ibb` flag set. +The flags sets the CBFS file attribute tag to LE `' IBB'`. + +The make system in turn adds all those files to the [FIT] as type 7. + +## Intel TXT measurements + +Each IBB is measured and extended into PCR0 by [Intel TXT], before the CPU +reset vector is executed. +The IBBs are measured in the order they are listed in the [FIT]. + +## FIT schematic + +![][fit_ibb] + +[fit_ibb]: fit_ibb.svg +[FIT]: ../../soc/intel/fit.md +[Intel TXT]: txt.md diff --git a/MAINTAINERS b/MAINTAINERS index 73ca6dfed9..030ed7a593 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -135,7 +135,6 @@ Maintainers List (try to look for most precise areas first) RISC-V ARCHITECTURE M: Ronald Minnich -M: Jonathan Neuschäfer R: Philipp Hug S: Maintained F: src/arch/riscv/ @@ -398,6 +397,12 @@ M: Wim Vervoorn S: Maintained F: src/mainboard/facebook/fbg1701/ +PORTWELL PQ-M107 MAINBOARD +M: Frans Hendriks +M: Wim Vervoorn +S: Maintained +F: src/mainboard/portwell/m107/ + AMD FAMILY10H & FAMILY15H (NON-AGESA) CPUS & NORTHBRIDGE M: Timothy Pearson S: Supported @@ -674,6 +679,14 @@ MISSING: SPI # Owners: Patrick, Philipp # Backups: +CODE OF CONDUCT +M: Stefan Reinauer +M: Patrick Georgi +M: Ronald Minnich +M: Martin Roth +S: Maintained +F: Documentation/community/code_of_conduct.md + # Wiki # Owners: Stefan, Patrick # Backups: diff --git a/Makefile b/Makefile index 45b0bc5f8c..317a8eb1cf 100644 --- a/Makefile +++ b/Makefile @@ -124,16 +124,17 @@ ifneq ($(MAKECMDGOALS),) ifneq ($(filter %config %clean cross% clang iasl gnumake lint% help% what-jenkins-does,$(MAKECMDGOALS)),) NOCOMPILE:=1 endif -ifeq ($(MAKECMDGOALS), %clean) +ifneq ($(filter %clean lint% help% what-jenkins-does,$(MAKECMDGOALS)),) NOMKDIR:=1 endif endif +-include $(TOPLEVEL)/site-local/Makefile.inc + ifeq ($(NOCOMPILE),1) include $(TOPLEVEL)/Makefile.inc include $(TOPLEVEL)/payloads/Makefile.inc include $(TOPLEVEL)/util/testing/Makefile.inc --include $(TOPLEVEL)/site-local/Makefile.inc real-all: @echo "Error: Expected config file ($(DOTCONFIG)) not present." >&2 @echo "Please specify a config file or run 'make menuconfig' to" >&2 diff --git a/Makefile.inc b/Makefile.inc index 28f1363131..c275d1efa5 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -401,7 +401,7 @@ endif CFLAGS_common += -pipe -g -nostdinc -std=gnu11 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs +CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie @@ -705,6 +705,11 @@ $(objcbfs)/bootblock.raw.bin: $(objcbfs)/bootblock.raw.elf @printf " OBJCOPY $(notdir $(@))\n" $(OBJCOPY_bootblock) -O binary $< $@ +ifneq ($(CONFIG_HAVE_BOOTBLOCK),y) +$(objcbfs)/bootblock.bin: + dd if=/dev/zero of=$@ bs=64 count=1 +endif + $(objcbfs)/%.bin: $(objcbfs)/%.raw.bin cp $< $@ diff --git a/configs/config.emulation_qemu_riscv_rv64 b/configs/config.emulation_qemu_riscv_rv64 new file mode 100644 index 0000000000..d41963c157 --- /dev/null +++ b/configs/config.emulation_qemu_riscv_rv64 @@ -0,0 +1,2 @@ +CONFIG_BOARD_EMULATION_QEMU_RISCV_RV64=y +CONFIG_RISCV_OPENSBI=y diff --git a/configs/config.up_squared.vboot b/configs/config.up_squared.vboot new file mode 100644 index 0000000000..130c02f6ec --- /dev/null +++ b/configs/config.up_squared.vboot @@ -0,0 +1,2 @@ +CONFIG_VENDOR_UP=y +CONFIG_VBOOT=y diff --git a/payloads/Kconfig b/payloads/Kconfig index d0f8a44080..46cfaf5ad0 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -30,7 +30,7 @@ config PAYLOAD_ELF config PAYLOAD_FIT bool "A FIT payload" - depends on ARCH_ARM64 + depends on ARCH_ARM64 || ARCH_RISCV select PAYLOAD_FIT_SUPPORT help Select this option if you have a payload image (a FIT file) which @@ -99,8 +99,8 @@ config PAYLOAD_IS_FLAT_BINARY config PAYLOAD_FIT_SUPPORT bool "FIT support" default n - default y if PAYLOAD_LINUX && (ARCH_ARM || ARCH_ARM64) - depends on ARCH_ARM64 + default y if PAYLOAD_LINUX && (ARCH_ARM || ARCH_ARM64 || ARCH_RISCV) + depends on ARCH_ARM64 || ARCH_RISCV select FLATTENED_DEVICE_TREE help Select this option if your payload is of type FIT. diff --git a/payloads/external/GRUB2/Makefile b/payloads/external/GRUB2/Makefile index 43da597eb7..b433bc09b3 100644 --- a/payloads/external/GRUB2/Makefile +++ b/payloads/external/GRUB2/Makefile @@ -28,7 +28,7 @@ grub2/build/config.h: $(CONFIG_DEP) | checkout echo " CONFIG GRUB2 $(NAME-y)" rm -rf grub2/build mkdir grub2/build - cd grub2 && ./bootstrap.sh ; ./autogen.sh + cd grub2 && ./bootstrap ; ./autogen.sh cd grub2/build && ../configure CC="$(HOSTCC)" LD="$(LD)" \ FREETYPE="pkg-config freetype2" BUILD_FREETYPE="pkg-config freetype2" \ TARGET_CC="$(CC)" TARGET_OBJCOPY="$(OBJCOPY)" TARGET_STRIP="$(STRIP)" \ diff --git a/payloads/external/LinuxBoot/Kconfig b/payloads/external/LinuxBoot/Kconfig index 84af49ccc0..a91288bca7 100644 --- a/payloads/external/LinuxBoot/Kconfig +++ b/payloads/external/LinuxBoot/Kconfig @@ -39,6 +39,13 @@ config LINUXBOOT_ARM64 help AARCH64 kernel and initramfs +config LINUXBOOT_RISCV + bool "RISC-V" + depends on ARCH_RISCV + select PAYLOAD_FIT_SUPPORT + help + RISC-V kernel and initramfs + endchoice comment "Linux kernel" @@ -126,7 +133,7 @@ config LINUXBOOT_KERNEL_CONFIGFILE choice prompt "Kernel binary format" default LINUXBOOT_KERNEL_BZIMAGE if LINUXBOOT_X86 || LINUXBOOT_X86_64 - default LINUXBOOT_KERNEL_UIMAGE if LINUXBOOT_ARM64 + default LINUXBOOT_KERNEL_UIMAGE if LINUXBOOT_ARM64 || LINUXBOOT_RISCV config LINUXBOOT_KERNEL_BZIMAGE bool "bzImage" @@ -134,14 +141,14 @@ config LINUXBOOT_KERNEL_BZIMAGE config LINUXBOOT_KERNEL_UIMAGE bool "uImage" - depends on LINUXBOOT_ARM64 + depends on LINUXBOOT_ARM64 || LINUXBOOT_RISCV endchoice config LINUXBOOT_DTB_FILE string "Compiled devicetree file" - depends on LINUXBOOT_ARM64 + depends on LINUXBOOT_ARM64 || LINUXBOOT_RISCV default "" endif #LINUXBOOT_COMPILE_KERNEL @@ -154,7 +161,7 @@ config LINUX_COMMAND_LINE config PAYLOAD_FILE default "payloads/external/LinuxBoot/linuxboot/bzImage" if LINUXBOOT_COMPILE_KERNEL && ( LINUXBOOT_X86 || LINUXBOOT_X86_64 ) - default "payloads/external/LinuxBoot/linuxboot/uImage" if LINUXBOOT_COMPILE_KERNEL && LINUXBOOT_ARM64 + default "payloads/external/LinuxBoot/linuxboot/uImage" if LINUXBOOT_COMPILE_KERNEL && (LINUXBOOT_ARM64 || LINUXBOOT_RISCV) default LINUXBOOT_KERNEL_PATH if !LINUXBOOT_COMPILE_KERNEL comment "Linux initramfs" diff --git a/payloads/external/LinuxBoot/Kconfig.name b/payloads/external/LinuxBoot/Kconfig.name index 18438c7861..c59a8bcee9 100644 --- a/payloads/external/LinuxBoot/Kconfig.name +++ b/payloads/external/LinuxBoot/Kconfig.name @@ -14,7 +14,7 @@ config PAYLOAD_LINUXBOOT bool "LinuxBoot" - depends on ARCH_X86 || ARCH_ARM64 + depends on ARCH_X86 || ARCH_ARM64 || ARCH_RISCV help Select this option if you want to build a coreboot image with a LinuxBoot payload. If you don't know what this is diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 9c34efabeb..df168f2bee 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -300,10 +300,7 @@ payloads/external/LinuxBoot/linuxboot/initramfs_u-root.cpio: linuxboot payloads/external/Yabits/uefi/build/uefi.elf yabits: $(MAKE) -C payloads/external/Yabits all \ - CC="$(CC_x86_32)" \ - LD="$(LD_x86_32)" \ - OBJCOPY="$(OBJCOPY_x86_32)" \ - AS="$(AS_x86_32)" \ + XGCCPATH="$(XGCCPATH)" \ CONFIG_YABITS_REVISION=$(CONFIG_YABITS_REVISION) \ CONFIG_YABITS_REVISION_ID=$(CONFIG_YABITS_REVISION_ID) \ CONFIG_YABITS_MASTER=$(CONFIG_YABITS_MASTER) \ diff --git a/payloads/external/linux/Kconfig.name b/payloads/external/linux/Kconfig.name index 63621d88c7..493eb982ef 100644 --- a/payloads/external/linux/Kconfig.name +++ b/payloads/external/linux/Kconfig.name @@ -1,6 +1,6 @@ config PAYLOAD_LINUX bool "A Linux payload" - depends on ARCH_X86 || ARCH_ARM + depends on ARCH_X86 || ARCH_ARM || ARCH_RISCV help Select this option if you have a Linux bzImage which coreboot should run as soon as the basic hardware initialization diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index 1fa07f9a7a..f0aaa2727f 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -63,7 +63,7 @@ CFLAGS += $(EXTRA_CFLAGS) $(INCLUDES) -Os -pipe -nostdinc -ggdb3 CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer CFLAGS += -ffunction-sections -fdata-sections CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs +CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough CFLAGS += -Wstrict-aliasing -Wshadow -Werror $(obj)/libpayload-config.h: $(KCONFIG_AUTOHEADER) diff --git a/payloads/libpayload/curses/PDCurses/pdcurses/scanw.c b/payloads/libpayload/curses/PDCurses/pdcurses/scanw.c index 47f205052b..d1fd908dab 100644 --- a/payloads/libpayload/curses/PDCurses/pdcurses/scanw.c +++ b/payloads/libpayload/curses/PDCurses/pdcurses/scanw.c @@ -274,7 +274,7 @@ static int _pdc_vsscanf(const char *buf, const char *fmt, va_list arg_ptr) NEXT(c); goto string; } - /* no break */ + /* fall through */ default: if (fmt[1] == '-' && fmt[2] && f < (unsigned char)fmt[2]) diff --git a/payloads/libpayload/drivers/serial/qcs405.c b/payloads/libpayload/drivers/serial/qcs405.c index 7a80aae9c3..06ec5b9e1d 100644 --- a/payloads/libpayload/drivers/serial/qcs405.c +++ b/payloads/libpayload/drivers/serial/qcs405.c @@ -285,6 +285,7 @@ struct uart_params_t { static struct console_input_driver consin = { .havekey = serial_havechar, .getchar = serial_getchar, + .input_type = CONSOLE_INPUT_TYPE_UART, }; static struct console_output_driver consout = { diff --git a/payloads/libpayload/drivers/video/graphics.c b/payloads/libpayload/drivers/video/graphics.c index 85a8642c72..6b5664bbcf 100644 --- a/payloads/libpayload/drivers/video/graphics.c +++ b/payloads/libpayload/drivers/video/graphics.c @@ -129,8 +129,30 @@ static inline void set_pixel(struct vector *coord, uint32_t color) { const int bpp = fbinfo->bits_per_pixel; const int bpl = fbinfo->bytes_per_line; + struct vector rcoord; int i; - uint8_t * const pixel = fbaddr + coord->y * bpl + coord->x * bpp / 8; + + switch (fbinfo->orientation) { + case CB_FB_ORIENTATION_NORMAL: + default: + rcoord.x = coord->x; + rcoord.y = coord->y; + break; + case CB_FB_ORIENTATION_BOTTOM_UP: + rcoord.x = screen.size.width - 1 - coord->x; + rcoord.y = screen.size.height - 1 - coord->y; + break; + case CB_FB_ORIENTATION_LEFT_UP: + rcoord.x = coord->y; + rcoord.y = screen.size.width - 1 - coord->x; + break; + case CB_FB_ORIENTATION_RIGHT_UP: + rcoord.x = screen.size.height - 1 - coord->y; + rcoord.y = coord->x; + break; + } + + uint8_t * const pixel = fbaddr + rcoord.y * bpl + rcoord.x * bpp / 8; for (i = 0; i < bpp / 8; i++) pixel[i] = (color >> (i * 8)); } @@ -152,8 +174,17 @@ static int cbgfx_init(void) if (!fbaddr) return CBGFX_ERROR_FRAMEBUFFER_ADDR; - screen.size.width = fbinfo->x_resolution; - screen.size.height = fbinfo->y_resolution; + switch (fbinfo->orientation) { + default: /* Normal or rotated 180 degrees. */ + screen.size.width = fbinfo->x_resolution; + screen.size.height = fbinfo->y_resolution; + break; + case CB_FB_ORIENTATION_LEFT_UP: /* 90 degree rotation. */ + case CB_FB_ORIENTATION_RIGHT_UP: + screen.size.width = fbinfo->y_resolution; + screen.size.height = fbinfo->x_resolution; + break; + } screen.offset.x = 0; screen.offset.y = 0; @@ -242,7 +273,7 @@ int clear_screen(const struct rgb_color *rgb) * We assume that for 32bpp the high byte gets ignored anyway. */ if ((((color >> 8) & 0xff) == (color & 0xff)) && (bpp == 16 || (((color >> 16) & 0xff) == (color & 0xff)))) { - memset(fbaddr, color & 0xff, screen.size.height * bpl); + memset(fbaddr, color & 0xff, fbinfo->y_resolution * bpl); } else { for (p.y = 0; p.y < screen.size.height; p.y++) for (p.x = 0; p.x < screen.size.width; p.x++) diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index b0d7c90389..bf2cf022d1 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -57,7 +57,7 @@ enum { CB_TAG_CBMEM_CONSOLE = 0x0017, CB_TAG_MRC_CACHE = 0x0018, CB_TAG_VBNV = 0x0019, - CB_TAG_VBOOT_HANDOFF = 0x0020, + CB_TAG_VBOOT_HANDOFF = 0x0020, /* deprecated */ CB_TAG_X86_ROM_MTRR = 0x0021, CB_TAG_DMA = 0x0022, CB_TAG_RAM_OOPS = 0x0023, @@ -189,6 +189,14 @@ struct cb_forward { u64 forward; }; +/* Panel orientation, matches drm_connector.h in the Linux kernel. */ +enum cb_fb_orientation { + CB_FB_ORIENTATION_NORMAL = 0, + CB_FB_ORIENTATION_BOTTOM_UP = 1, + CB_FB_ORIENTATION_LEFT_UP = 2, + CB_FB_ORIENTATION_RIGHT_UP = 3, +}; + struct cb_framebuffer { u32 tag; u32 size; @@ -206,6 +214,7 @@ struct cb_framebuffer { u8 blue_mask_size; u8 reserved_mask_pos; u8 reserved_mask_size; + u8 orientation; }; #define CB_GPIO_ACTIVE_LOW 0 diff --git a/payloads/libpayload/include/string.h b/payloads/libpayload/include/string.h index 4aff0e8994..52379a034d 100644 --- a/payloads/libpayload/include/string.h +++ b/payloads/libpayload/include/string.h @@ -73,7 +73,7 @@ char *strerror(int errnum); * @defgroup string Unicode functions * @{ */ -char *utf16le_to_ascii(uint16_t *utf16_string, int maxlen); +char *utf16le_to_ascii(const uint16_t *utf16_string, size_t maxlen); /** @} */ /** diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index 72059adb91..50f0e3962c 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -95,8 +95,6 @@ struct sysinfo_t { struct cb_header *header; struct cb_mainboard *mainboard; - void *vboot_handoff; - u32 vboot_handoff_size; void *vboot_workbuf; uint32_t vboot_workbuf_size; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 26a3a48c23..03778b6d2a 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -78,14 +78,6 @@ static void cb_parse_serial(void *ptr, struct sysinfo_t *info) info->serial = ((struct cb_serial *)ptr); } -static void cb_parse_vboot_handoff(unsigned char *ptr, struct sysinfo_t *info) -{ - struct lb_range *vbho = (struct lb_range *)ptr; - - info->vboot_handoff = (void *)(uintptr_t)vbho->range_start; - info->vboot_handoff_size = vbho->range_size; -} - static void cb_parse_vboot_workbuf(unsigned char *ptr, struct sysinfo_t *info) { struct lb_range *vbwb = (struct lb_range *)ptr; @@ -367,9 +359,6 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_VBNV: cb_parse_vbnv(ptr, info); break; - case CB_TAG_VBOOT_HANDOFF: - cb_parse_vboot_handoff(ptr, info); - break; case CB_TAG_VBOOT_WORKBUF: cb_parse_vboot_workbuf(ptr, info); break; diff --git a/payloads/libpayload/libc/printf.c b/payloads/libpayload/libc/printf.c index cb623aa51a..3896f01b86 100644 --- a/payloads/libpayload/libc/printf.c +++ b/payloads/libpayload/libc/printf.c @@ -585,6 +585,7 @@ static int printf_core(const char *fmt, struct printf_spec *ps, va_list ap) /* Integer values */ case 'P': /* pointer */ flags |= __PRINTF_FLAG_BIGCHARS; + /* fall through */ case 'p': flags |= __PRINTF_FLAG_PREFIX; base = 16; @@ -599,10 +600,12 @@ static int printf_core(const char *fmt, struct printf_spec *ps, va_list ap) case 'd': case 'i': flags |= __PRINTF_FLAG_SIGNED; + break; case 'u': break; case 'X': flags |= __PRINTF_FLAG_BIGCHARS; + /* fall through */ case 'x': base = 16; break; diff --git a/payloads/libpayload/libc/string.c b/payloads/libpayload/libc/string.c index 6c257cbdaa..0e34a036b0 100644 --- a/payloads/libpayload/libc/string.c +++ b/payloads/libpayload/libc/string.c @@ -91,9 +91,9 @@ size_t strlen(const char *str) */ int strcasecmp(const char *s1, const char *s2) { - int i, res; + int res; - for (i = 0; 1; i++) { + for (size_t i = 0; 1; i++) { res = tolower(s1[i]) - tolower(s2[i]); if (res || (s1[i] == '\0')) break; @@ -112,10 +112,9 @@ int strcasecmp(const char *s1, const char *s2) */ int strncasecmp(const char *s1, const char *s2, size_t maxlen) { - int i, res; + int res = 0; - res = 0; - for (i = 0; i < maxlen; i++) { + for (size_t i = 0; i < maxlen; i++) { res = tolower(s1[i]) - tolower(s2[i]); if (res || (s1[i] == '\0')) break; @@ -135,9 +134,9 @@ int strncasecmp(const char *s1, const char *s2, size_t maxlen) */ int strcmp(const char *s1, const char *s2) { - int i, res; + int res; - for (i = 0; 1; i++) { + for (size_t i = 0; 1; i++) { res = s1[i] - s2[i]; if (res || (s1[i] == '\0')) break; @@ -156,10 +155,9 @@ int strcmp(const char *s1, const char *s2) */ int strncmp(const char *s1, const char *s2, size_t maxlen) { - int i, res; + int res = 0; - res = 0; - for (i = 0; i < maxlen; i++) { + for (size_t i = 0; i < maxlen; i++) { res = s1[i] - s2[i]; if (res || (s1[i] == '\0')) break; @@ -179,10 +177,9 @@ int strncmp(const char *s1, const char *s2, size_t maxlen) char *strncpy(char *d, const char *s, size_t n) { /* Use +1 to get the NUL terminator. */ - int max = n > strlen(s) + 1 ? strlen(s) + 1 : n; - int i; + size_t max = n > strlen(s) + 1 ? strlen(s) + 1 : n; - for (i = 0; i < max; i++) + for (size_t i = 0; i < max; i++) d[i] = (char)s[i]; return d; @@ -210,13 +207,12 @@ char *strcpy(char *d, const char *s) char *strcat(char *d, const char *s) { char *p = d + strlen(d); - int sl = strlen(s); - int i; + size_t sl = strlen(s); - for (i = 0; i < sl; i++) + for (size_t i = 0; i < sl; i++) p[i] = s[i]; - p[i] = '\0'; + p[sl] = '\0'; return d; } @@ -231,15 +227,13 @@ char *strcat(char *d, const char *s) char *strncat(char *d, const char *s, size_t n) { char *p = d + strlen(d); - int sl = strlen(s); - int max = n > sl ? sl : n; - // int max = n > strlen(s) ? strlen(s) : n; - int i; + size_t sl = strlen(s); + size_t max = n > sl ? sl : n; - for (i = 0; i < max; i++) + for (size_t i = 0; i < max; i++) p[i] = s[i]; - p[i] = '\0'; + p[max] = '\0'; return d; } @@ -249,22 +243,24 @@ char *strncat(char *d, const char *s, size_t n) * @param d The destination string. * @param s The source string. * @param n d will have at most n-1 characters (plus NUL) after invocation. - * @return A pointer to the destination string. + * @return The total length of the concatenated string. */ size_t strlcat(char *d, const char *s, size_t n) { - int sl = strlen(s); - int dl = strlen(d); + size_t sl = strlen(s); + size_t dl = strlen(d); + + if (n <= dl + 1) + return sl + dl; char *p = d + dl; - int max = n > (sl + dl) ? sl : (n - dl - 1); - int i; + size_t max = n > (sl + dl) ? sl : (n - dl - 1); - for (i = 0; i < max; i++) + for (size_t i = 0; i < max; i++) p[i] = s[i]; - p[i] = '\0'; - return max; + p[max] = '\0'; + return sl + dl; } /** @@ -316,7 +312,7 @@ char *strrchr(const char *s, int c) */ char *strdup(const char *s) { - int n = strlen(s); + size_t n = strlen(s); char *p = malloc(n + 1); if (p != NULL) { @@ -336,11 +332,13 @@ char *strdup(const char *s) */ char *strstr(const char *h, const char *n) { - int hn = strlen(h); - int nn = strlen(n); - int i; + size_t hn = strlen(h); + size_t nn = strlen(n); - for (i = 0; i <= hn - nn; i++) + if (hn < nn) + return NULL; + + for (size_t i = 0; i <= hn - nn; i++) if (!memcmp(&h[i], n, nn)) return (char *)&h[i]; @@ -532,11 +530,11 @@ unsigned long int strtoul(const char *ptr, char **endptr, int base) */ size_t strspn(const char *s, const char *a) { - int i, j; - int al = strlen(a); + size_t i; + size_t al = strlen(a); for (i = 0; s[i] != 0; i++) { int found = 0; - for (j = 0; j < al; j++) { + for (size_t j = 0; j < al; j++) { if (s[i] == a[j]) { found = 1; break; @@ -556,11 +554,11 @@ size_t strspn(const char *s, const char *a) */ size_t strcspn(const char *s, const char *a) { - int i, j; - int al = strlen(a); + size_t i; + size_t al = strlen(a); for (i = 0; s[i] != 0; i++) { int found = 0; - for (j = 0; j < al; j++) { + for (size_t j = 0; j < al; j++) { if (s[i] == a[j]) { found = 1; break; @@ -645,12 +643,11 @@ char *strerror(int errnum) * @param maxlen Maximum possible length of the string in code points * @return Newly allocated ASCII string */ -char *utf16le_to_ascii(uint16_t *utf16_string, int maxlen) +char *utf16le_to_ascii(const uint16_t *utf16_string, size_t maxlen) { char *ascii_string = xmalloc(maxlen + 1); /* +1 for trailing \0 */ ascii_string[maxlen] = '\0'; - int i; - for (i = 0; i < maxlen; i++) { + for (size_t i = 0; i < maxlen; i++) { uint16_t wchar = utf16_string[i]; ascii_string[i] = wchar > 0x7f ? '?' : (char)wchar; } diff --git a/src/Kconfig b/src/Kconfig index 2bb5bfeab0..6288d0bc74 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -250,12 +250,28 @@ config RELOCATABLE_RAMSTAGE wake. When selecting this option the romstage is responsible for determing a stack location to use for loading the ramstage. -config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM - depends on RELOCATABLE_RAMSTAGE +config TSEG_STAGE_CACHE bool + default y + depends on !NO_STAGE_CACHE && SMM_TSEG help - The relocated ramstage is saved in an area specified by the - by the board and/or chipset. + The option enables stage cache support for platform. Platform + can stash copies of postcar, ramstage and raw runtime data + inside SMM TSEG, to be restored on S3 resume path. + +config CBMEM_STAGE_CACHE + bool "Cache stages in CBMEM" + depends on !NO_STAGE_CACHE && !TSEG_STAGE_CACHE + help + The option enables stage cache support for platform. Platform + can stash copies of postcar, ramstage and raw runtime data + inside CBMEM. + + While the approach is faster than reloading stages from boot media + it is also a possible attack scenario via which OS can possibly + circumvent SMM locks and SPI write protections. + + If unsure, select 'N' config UPDATE_IMAGE bool "Update existing coreboot.rom image" @@ -1143,7 +1159,7 @@ config RELOCATABLE_MODULES config NO_STAGE_CACHE bool - default y if !HAVE_ACPI_RESUME + default y if !HAVE_ACPI_RESUME || !RELOCATABLE_RAMSTAGE help Do not save any component in stage cache for resume path. On resume, all components would be read back from CBFS again. diff --git a/src/acpi/sata.c b/src/acpi/sata.c index ec0d505ca0..d7fcbd6daf 100644 --- a/src/acpi/sata.c +++ b/src/acpi/sata.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2015 Alexander Couzens + * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/src/arch/mips/bootblock.S b/src/arch/mips/bootblock.S index 849c168fd0..f8049c96d4 100644 --- a/src/arch/mips/bootblock.S +++ b/src/arch/mips/bootblock.S @@ -33,7 +33,7 @@ _start: addi $t0, $t0, 4 /* Run main */ - b main + b mips_main /* * Should never return from main. Make sure there is no branch in the diff --git a/src/arch/mips/bootblock_simple.c b/src/arch/mips/bootblock_simple.c index 84029ebedb..e195b6ac85 100644 --- a/src/arch/mips/bootblock_simple.c +++ b/src/arch/mips/bootblock_simple.c @@ -19,7 +19,10 @@ #include #include -void main(void) +/* called from assembly in bootblock.S */ +void mips_main(void); + +void mips_main(void) { bootblock_cpu_init(); diff --git a/src/arch/ppc64/Kconfig b/src/arch/ppc64/Kconfig index 9e37bfc15f..0699e910ce 100644 --- a/src/arch/ppc64/Kconfig +++ b/src/arch/ppc64/Kconfig @@ -1,25 +1,20 @@ config ARCH_PPC64 bool - default n config ARCH_BOOTBLOCK_PPC64 bool - default n select ARCH_PPC64 select BOOTBLOCK_CUSTOM select C_ENVIRONMENT_BOOTBLOCK - select ARCH_VERSTAGE_PPC64 - select ARCH_ROMSTAGE_PPC64 - select ARCH_RAMSTAGE_PPC64 config ARCH_VERSTAGE_PPC64 bool - default n + select ARCH_PPC64 config ARCH_ROMSTAGE_PPC64 bool - default n + select ARCH_PPC64 config ARCH_RAMSTAGE_PPC64 bool - default n + select ARCH_PPC64 diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index a4f1788497..f2ca571c97 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -41,6 +41,30 @@ config ARCH_RISCV_S bool default n +config RISCV_HAS_OPENSBI + def_bool n + +config RISCV_OPENSBI + bool "Use OpenSBI to hand over control to payload" + depends on ARCH_RISCV_M && ARCH_RISCV_S + depends on RISCV_HAS_OPENSBI + default n + help + Load OpenSBI after payload has been loaded and use it to + provide the SBI and to handover control to payload. + +config OPENSBI_PLATFORM + string + depends on RISCV_HAS_OPENSBI + help + The OpenSBI platform to build for. + +config OPENSBI_TEXT_START + hex + depends on RISCV_HAS_OPENSBI + help + The linking address used to build opensbi. + config ARCH_RISCV_U # U (user) mode is for programs. bool diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index d5f62954eb..0039fab180 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -147,6 +147,7 @@ ramstage-y += boot.c ramstage-y += tables.c ramstage-y += payload.c ramstage-$(ARCH_RISCV_PMP) += pmp.c +ramstage-y += fit_payload.c ramstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ @@ -174,4 +175,45 @@ LDFLAGS_ramstage += -m elf32lriscv endif #CONFIG_ARCH_RISCV_RV32 endif #CONFIG_ARCH_RAMSTAGE_RISCV + +ifeq ($(CONFIG_RISCV_OPENSBI),y) + +OPENSBI_SOURCE := $(top)/3rdparty/opensbi +OPENSBI_BUILD := $(abspath $(obj)/3rdparty/opensbi) +OPENSBI_TARGET := $(OPENSBI_BUILD)/platform/$(CONFIG_OPENSBI_PLATFORM)/firmware/fw_dynamic.elf +OPENSBI := $(obj)/opensbi.elf + +$(OPENSBI_TARGET): $(obj)/config.h | $(OPENSBI_SOURCE) + printf " MAKE $(subst $(obj)/,,$(@))\n" + mkdir -p $(OPENSBI_BUILD) + $(MAKE) \ + -C "$(OPENSBI_SOURCE)" \ + CC="$(CC_ramstage)" \ + LD="$(LD_ramstage)" \ + OBJCOPY="$(OBJCOPY_ramstage)" \ + AR="$(AR_ramstage)" \ + PLATFORM=$(CONFIG_OPENSBI_PLATFORM) \ + O="$(OPENSBI_BUILD)" \ + FW_JUMP=y \ + FW_DYNAMIC=y \ + FW_PAYLOAD=n \ + FW_PAYLOAD_OFFSET=0 \ + FW_TEXT_START=$(CONFIG_OPENSBI_TEXT_START) + +$(OPENSBI): $(OPENSBI_TARGET) + cp $< $@ + +OPENSBI_CBFS := $(CONFIG_CBFS_PREFIX)/opensbi +$(OPENSBI_CBFS)-file := $(OPENSBI) +$(OPENSBI_CBFS)-type := payload +$(OPENSBI_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(OPENSBI_CBFS) + +check-ramstage-overlap-files += $(OPENSBI_CBFS) + +CPPFLAGS_common += -I$(OPENSBI_SOURCE)/include +ramstage-y += opensbi.c + +endif #CONFIG_RISCV_OPENSBI + endif #CONFIG_ARCH_RISCV diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 8e4bb36af5..6a23b8a696 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -20,6 +20,12 @@ #include #include #include +#include + +struct arch_prog_run_args { + struct prog *prog; + struct prog *opensbi; +}; /* * A pointer to the Flattened Device Tree passed to coreboot by the boot ROM. @@ -28,10 +34,10 @@ * This pointer is only used in ramstage! */ -static void do_arch_prog_run(struct prog *prog) +static void do_arch_prog_run(struct arch_prog_run_args *args) { - void (*doit)(int hart_id, void *fdt); int hart_id; + struct prog *prog = args->prog; void *fdt = prog_entry_arg(prog); /* @@ -48,17 +54,39 @@ static void do_arch_prog_run(struct prog *prog) fdt = HLS()->fdt; if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { - run_payload(prog, fdt, RISCV_PAYLOAD_MODE_S); - return; + if (CONFIG(RISCV_OPENSBI)) + run_payload_opensbi(prog, fdt, args->opensbi, RISCV_PAYLOAD_MODE_S); + else + run_payload(prog, fdt, RISCV_PAYLOAD_MODE_S); + } else { + void (*doit)(int hart_id, void *fdt) = prog_entry(prog); + + hart_id = HLS()->hart_id; + + doit(hart_id, fdt); } - doit = prog_entry(prog); - hart_id = HLS()->hart_id; - - doit(hart_id, fdt); + die("Failed to run stage"); } void arch_prog_run(struct prog *prog) { - smp_resume((void (*)(void *))do_arch_prog_run, prog); + struct arch_prog_run_args args = {}; + + args.prog = prog; + + /* In case of OpenSBI we have to load it before resuming all HARTs */ + if (ENV_RAMSTAGE && CONFIG(RISCV_OPENSBI)) { + struct prog sbi = PROG_INIT(PROG_OPENSBI, CONFIG_CBFS_PREFIX"/opensbi"); + + if (prog_locate(&sbi)) + die("OpenSBI not found"); + + if (!selfload_check(&sbi, BM_MEM_OPENSBI)) + die("OpenSBI load failed"); + + args.opensbi = &sbi; + } + + smp_resume((void (*)(void *))do_arch_prog_run, &args); } diff --git a/src/arch/riscv/fit_payload.c b/src/arch/riscv/fit_payload.c new file mode 100644 index 0000000000..60a4bc0557 --- /dev/null +++ b/src/arch/riscv/fit_payload.c @@ -0,0 +1,141 @@ +/* + * Copyright 2013 Google Inc. + * Copyright 2018 Facebook, Inc. + * Copyright 2019 9elements Agency GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Implements a Berkley Boot Loader (BBL) compatible payload loading */ + +#define MAX_KERNEL_SIZE (64*MiB) + +#if CONFIG(ARCH_RISCV_RV32) +#define SECTION_ALIGN (4 * MiB) +#endif +#if CONFIG(ARCH_RISCV_RV64) +#define SECTION_ALIGN (2 * MiB) +#endif + +static size_t get_kernel_size(const struct fit_image_node *node) +{ + /* + * Since we don't have a way to determine the uncompressed size of the + * kernel, we have to keep as much memory as possible free for use by + * the kernel immediately after the end of the kernel image. The amount + * of space required will vary depending on selected features, and is + * effectively unbound. + */ + + printk(BIOS_INFO, + "FIT: Leaving additional %u MiB of free space after kernel.\n", + MAX_KERNEL_SIZE >> 20); + + return node->size + MAX_KERNEL_SIZE; +} + +/** + * Place the region in free memory range. + * + * The caller has to set region->offset to the minimum allowed address. + */ +static bool fit_place_mem(const struct range_entry *r, void *arg) +{ + struct region *region = arg; + resource_t start; + + if (range_entry_tag(r) != BM_MEM_RAM) + return true; + + /* Section must be aligned at page boundary */ + start = ALIGN_UP(MAX(region->offset, range_entry_base(r)), SECTION_ALIGN); + + if (start + region->size < range_entry_end(r)) { + region->offset = (size_t)start; + return false; + } + + return true; +} + +bool fit_payload_arch(struct prog *payload, struct fit_config_node *config, + struct region *kernel, + struct region *fdt, + struct region *initrd) +{ + void *arg = NULL; + + if (!config->fdt || !fdt) { + printk(BIOS_CRIT, "CRIT: Providing a valid FDT is mandatory to " + "boot a RISC-V kernel!\n"); + return false; + /* TODO: Fall back to the ROM FDT? */ + } + + /* Update kernel size from image header, if possible */ + kernel->size = get_kernel_size(config->kernel); + printk(BIOS_DEBUG, "FIT: Using kernel size of 0x%zx bytes\n", + kernel->size); + + /* + * The code assumes that bootmem_walk provides a sorted list of memory + * regions, starting from the lowest address. + * The order of the calls here doesn't matter, as the placement is + * enforced in the called functions. + * For details check code on top. + */ + kernel->offset = 0; + if (!bootmem_walk(fit_place_mem, kernel)) + return false; + + /* Mark as reserved for future allocations. */ + bootmem_add_range(kernel->offset, kernel->size, BM_MEM_PAYLOAD); + + /* Place FDT and INITRD after kernel. */ + + /* Place INITRD */ + if (config->ramdisk) { + initrd->offset = kernel->offset + kernel->size; + + if (!bootmem_walk(fit_place_mem, initrd)) + return false; + /* Mark as reserved for future allocations. */ + bootmem_add_range(initrd->offset, initrd->size, BM_MEM_PAYLOAD); + } + + /* Place FDT */ + fdt->offset = kernel->offset + kernel->size; + + if (!bootmem_walk(fit_place_mem, fdt)) + return false; + /* Mark as reserved for future allocations. */ + bootmem_add_range(fdt->offset, fdt->size, BM_MEM_PAYLOAD); + + /* Kernel expects FDT as argument */ + arg = (void *)fdt->offset; + + prog_set_entry(payload, (void *)kernel->offset, arg); + + bootmem_dump_ranges(); + + return true; +} diff --git a/src/arch/riscv/include/arch/boot.h b/src/arch/riscv/include/arch/boot.h index 34a507edec..c05c669f00 100644 --- a/src/arch/riscv/include/arch/boot.h +++ b/src/arch/riscv/include/arch/boot.h @@ -16,12 +16,17 @@ #ifndef ARCH_RISCV_INCLUDE_ARCH_BOOT_H #define ARCH_RISCV_INCLUDE_ARCH_BOOT_H -#include - #define RISCV_PAYLOAD_MODE_U 0 #define RISCV_PAYLOAD_MODE_S 1 #define RISCV_PAYLOAD_MODE_M 3 +struct prog; void run_payload(struct prog *prog, void *fdt, int payload_mode); +void run_payload_opensbi(struct prog *prog, void *fdt, struct prog *opensbi, int payload_mode); +void run_opensbi(const int hart_id, + const void *opensbi, + const void *fdt, + const void *payload, + const int payload_mode); #endif diff --git a/src/arch/riscv/opensbi.c b/src/arch/riscv/opensbi.c new file mode 100644 index 0000000000..695c24f756 --- /dev/null +++ b/src/arch/riscv/opensbi.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 9elements Agency GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +/* DO NOT INLCUDE COREBOOT HEADERS HERE */ + +void run_opensbi(const int hart_id, + const void *fdt, + const void *opensbi, + const void *payload, + const int payload_mode) +{ + struct fw_dynamic_info info = { + .magic = FW_DYNAMIC_INFO_MAGIC_VALUE, + .version = FW_DYNAMIC_INFO_VERSION_MAX, + .next_mode = payload_mode, + .next_addr = (uintptr_t)payload, + }; + + csr_write(mepc, opensbi); + asm volatile ( + "mv a0, %0\n\t" + "mv a1, %1\n\t" + "mv a2, %2\n\t" + "mret" : + : "r"(hart_id), "r"(fdt), "r"(&info) + : "a0", "a1", "a2"); +} diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c index 903e8a6ab6..297d30d2a5 100644 --- a/src/arch/riscv/payload.c +++ b/src/arch/riscv/payload.c @@ -15,18 +15,44 @@ * GNU General Public License for more details. */ +#include #include #include #include +#include #include #include +/* Run OpenSBI and let OpenSBI hand over control to the payload */ +void run_payload_opensbi(struct prog *prog, void *fdt, struct prog *opensbi, int payload_mode) +{ + int hart_id = read_csr(mhartid); + uintptr_t status = read_csr(mstatus); + status = INSERT_FIELD(status, MSTATUS_MPIE, 0); + + /* + * In case of OpenSBI we always run it in M-Mode. + * OpenSBI will switch to payload_mode when done. + */ + + status = INSERT_FIELD(status, MSTATUS_MPP, PRV_M); + /* Trap vector base address point to the payload */ + write_csr(mtvec, prog_entry(opensbi)); + /* disable M-Mode interrupt */ + write_csr(mie, 0); + write_csr(mstatus, status); + + run_opensbi(hart_id, fdt, prog_entry(opensbi), prog_entry(prog), payload_mode); +} + +/* Runs the payload without OpenSBI integration */ void run_payload(struct prog *prog, void *fdt, int payload_mode) { void (*doit)(int hart_id, void *fdt) = prog_entry(prog); int hart_id = read_csr(mhartid); uintptr_t status = read_csr(mstatus); status = INSERT_FIELD(status, MSTATUS_MPIE, 0); + switch (payload_mode) { case RISCV_PAYLOAD_MODE_U: status = INSERT_FIELD(status, MSTATUS_MPP, PRV_U); diff --git a/src/arch/riscv/stages.c b/src/arch/riscv/stages.c index 07b898f853..5b27508c47 100644 --- a/src/arch/riscv/stages.c +++ b/src/arch/riscv/stages.c @@ -24,8 +24,6 @@ * linker script. */ -#include -#include #include #include #include diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c index eef6bf2ffd..c5bcab0661 100644 --- a/src/arch/riscv/tables.c +++ b/src/arch/riscv/tables.c @@ -18,6 +18,9 @@ #include #include #include +#include + +DECLARE_OPTIONAL_REGION(opensbi); void arch_write_tables(uintptr_t coreboot_table) { @@ -25,6 +28,9 @@ void arch_write_tables(uintptr_t coreboot_table) void bootmem_arch_add_ranges(void) { + if (CONFIG(RISCV_OPENSBI) && REGION_SIZE(opensbi) > 0) + bootmem_add_range((uintptr_t)_opensbi, REGION_SIZE(opensbi), + BM_MEM_OPENSBI); } void lb_arch_add_records(struct lb_header *header) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 8ab993ec48..fdcbcd3fb5 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -386,10 +386,15 @@ static void acpi_create_tpm2(acpi_tpm2_t *tpm2) /* Hard to detect for coreboot. Just set it to 0 */ tpm2->platform_class = 0; - /* Must be set to 0 for TIS interface support */ - tpm2->control_area = 0; - /* coreboot only supports the TIS interface driver. */ - tpm2->start_method = 6; + if (CONFIG(CRB_TPM)) { + /* Must be set to 7 for CRB Support */ + tpm2->control_area = CONFIG_CRB_TPM_BASE_ADDRESS + 0x40; + tpm2->start_method = 7; + } else { + /* Must be set to 0 for FIFO interface support */ + tpm2->control_area = 0; + tpm2->start_method = 6; + } memset(tpm2->msp, 0, sizeof(tpm2->msp)); /* Fill the log area size and start address fields. */ @@ -946,7 +951,7 @@ void acpi_create_dbg2(acpi_dbg2_header_t *dbg2, } unsigned long acpi_write_dbg2_pci_uart(acpi_rsdp_t *rsdp, unsigned long current, - struct device *dev, uint8_t access_size) + const struct device *dev, uint8_t access_size) { acpi_dbg2_header_t *dbg2 = (acpi_dbg2_header_t *)current; struct resource *res; diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index 0fb8f3b000..47bcc52c1e 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -53,9 +53,9 @@ static void acpi_device_fill_len(void *ptr) } /* Locate and return the ACPI name for this device */ -const char *acpi_device_name(struct device *dev) +const char *acpi_device_name(const struct device *dev) { - struct device *pdev = dev; + const struct device *pdev = dev; const char *name = NULL; if (!dev) @@ -82,7 +82,7 @@ const char *acpi_device_name(struct device *dev) } /* Recursive function to find the root device and print a path from there */ -static ssize_t acpi_device_path_fill(struct device *dev, char *buf, +static ssize_t acpi_device_path_fill(const struct device *dev, char *buf, size_t buf_len, size_t cur) { const char *name = acpi_device_name(dev); @@ -117,7 +117,7 @@ static ssize_t acpi_device_path_fill(struct device *dev, char *buf, * Warning: just as with dev_path() this uses a static buffer * so should not be called mulitple times in one statement */ -const char *acpi_device_path(struct device *dev) +const char *acpi_device_path(const struct device *dev) { static char buf[DEVICE_PATH_MAX] = {}; @@ -131,7 +131,7 @@ const char *acpi_device_path(struct device *dev) } /* Return the path of the parent device as the ACPI Scope for this device */ -const char *acpi_device_scope(struct device *dev) +const char *acpi_device_scope(const struct device *dev) { static char buf[DEVICE_PATH_MAX] = {}; @@ -145,7 +145,7 @@ const char *acpi_device_scope(struct device *dev) } /* Concatentate the device path and provided name suffix */ -const char *acpi_device_path_join(struct device *dev, const char *name) +const char *acpi_device_path_join(const struct device *dev, const char *name) { static char buf[DEVICE_PATH_MAX] = {}; ssize_t len; diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 6251b98142..259efcd2d5 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -901,7 +901,7 @@ void acpi_create_dbg2(acpi_dbg2_header_t *dbg2_header, const char *device_path); unsigned long acpi_write_dbg2_pci_uart(acpi_rsdp_t *rsdp, unsigned long current, - struct device *dev, uint8_t access_size); + const struct device *dev, uint8_t access_size); void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags, unsigned long (*acpi_fill_dmar)(unsigned long)); unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, diff --git a/src/arch/x86/include/arch/acpi_device.h b/src/arch/x86/include/arch/acpi_device.h index 35695467cb..d74af9da74 100644 --- a/src/arch/x86/include/arch/acpi_device.h +++ b/src/arch/x86/include/arch/acpi_device.h @@ -62,10 +62,10 @@ struct acpi_dp { #define ACPI_DT_NAMESPACE_HID "PRP0001" struct device; -const char *acpi_device_name(struct device *dev); -const char *acpi_device_path(struct device *dev); -const char *acpi_device_scope(struct device *dev); -const char *acpi_device_path_join(struct device *dev, const char *name); +const char *acpi_device_name(const struct device *dev); +const char *acpi_device_path(const struct device *dev); +const char *acpi_device_scope(const struct device *dev); +const char *acpi_device_path_join(const struct device *dev, const char *name); int acpi_device_status(const struct device *dev); /* diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 2f5c3a643e..346e874217 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -500,6 +500,11 @@ smbios_board_type __weak smbios_mainboard_board_type(void) return SMBIOS_BOARD_TYPE_UNKNOWN; } +u8 __weak smbios_mainboard_enclosure_type(void) +{ + return CONFIG_SMBIOS_ENCLOSURE_TYPE; +} + const char *__weak smbios_system_serial_number(void) { return smbios_mainboard_serial_number(); @@ -620,7 +625,7 @@ static int smbios_write_type3(unsigned long *current, int handle) t->bootup_state = SMBIOS_STATE_SAFE; t->power_supply_state = SMBIOS_STATE_SAFE; t->thermal_state = SMBIOS_STATE_SAFE; - t->_type = CONFIG_SMBIOS_ENCLOSURE_TYPE; + t->_type = smbios_mainboard_enclosure_type(); t->security_status = SMBIOS_STATE_SAFE; len = t->length + smbios_string_table_len(t->eos); *current += len; diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 2236c95b8f..ec702ecfdf 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -68,7 +68,7 @@ #define CBMEM_ID_TCPA_TCG_LOG 0x54445041 #define CBMEM_ID_TIMESTAMP 0x54494d45 #define CBMEM_ID_TPM2_TCG_LOG 0x54504d32 -#define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 +#define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 /* deprecated */ #define CBMEM_ID_VBOOT_SEL_REG 0x780074f1 /* deprecated */ #define CBMEM_ID_VBOOT_WORKBUF 0x78007343 #define CBMEM_ID_VPD 0x56504420 diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 1ae5421bba..7bded2a3a3 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -68,7 +68,7 @@ enum { LB_TAG_CBMEM_CONSOLE = 0x0017, LB_TAG_MRC_CACHE = 0x0018, LB_TAG_VBNV = 0x0019, - LB_TAG_VBOOT_HANDOFF = 0x0020, + LB_TAG_VBOOT_HANDOFF = 0x0020, /* deprecated */ LB_TAG_X86_ROM_MTRR = 0x0021, LB_TAG_DMA = 0x0022, LB_TAG_RAM_OOPS = 0x0023, @@ -283,6 +283,18 @@ struct lb_forward { * fields described above. It may, however, only implement a subset * of the possible color formats. */ + +/* + * Framebuffer orientation, matches drm_connector.h drm_panel_orientation in the + * Linux kernel. + */ +enum lb_fb_orientation { + LB_FB_ORIENTATION_NORMAL = 0, + LB_FB_ORIENTATION_BOTTOM_UP = 1, + LB_FB_ORIENTATION_LEFT_UP = 2, + LB_FB_ORIENTATION_RIGHT_UP = 3, +}; + struct lb_framebuffer { uint32_t tag; uint32_t size; @@ -300,6 +312,7 @@ struct lb_framebuffer { uint8_t blue_mask_size; uint8_t reserved_mask_pos; uint8_t reserved_mask_size; + uint8_t orientation; }; diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 848ad501ce..f34c91bb5f 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -271,6 +271,7 @@ repeat: case 'X': flags |= LARGE; + /* fall through */ case 'x': base = 16; break; diff --git a/src/cpu/allwinner/Kconfig b/src/cpu/allwinner/Kconfig deleted file mode 100644 index d97cb644ff..0000000000 --- a/src/cpu/allwinner/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source src/cpu/allwinner/a10/Kconfig diff --git a/src/cpu/allwinner/Makefile.inc b/src/cpu/allwinner/Makefile.inc deleted file mode 100644 index e52a12e41d..0000000000 --- a/src/cpu/allwinner/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_CPU_ALLWINNER_A10) += a10 diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig deleted file mode 100644 index 0b5d9bf60d..0000000000 --- a/src/cpu/allwinner/a10/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -config CPU_ALLWINNER_A10 - bool - default n - -if CPU_ALLWINNER_A10 - -config CPU_SPECIFIC_OPTIONS - def_bool y - select ARCH_BOOTBLOCK_ARMV7 - select ARCH_VERSTAGE_ARMV7 - select ARCH_ROMSTAGE_ARMV7 - select ARCH_RAMSTAGE_ARMV7 - select NO_MONOTONIC_TIMER - select HAVE_UART_SPECIAL - select UART_OVERRIDE_REFCLK - select BOOT_DEVICE_NOT_SPI_FLASH - -endif # if CPU_ALLWINNER_A10 diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc deleted file mode 100644 index cbdb5ae856..0000000000 --- a/src/cpu/allwinner/a10/Makefile.inc +++ /dev/null @@ -1,55 +0,0 @@ -bootblock-y += bootblock.c -bootblock-y += bootblock_media.c -bootblock-y += clock.c -bootblock-y += gpio.c -bootblock-y += pinmux.c -bootblock-y += raminit.c -bootblock-y += timer.c - -romstage-y += bootblock_media.c -romstage-y += cbmem.c -romstage-y += clock.c -romstage-y += pinmux.c -romstage-y += timer.c -romstage-y += twi.c - -ramstage-y += bootblock_media.c -ramstage-y += cbmem.c -ramstage-y += clock.c -ramstage-y += cpu.c -ramstage-y += timer.c -ramstage-y += twi.c - -bootblock-y += uart.c uart_console.c -romstage-y += uart.c uart_console.c -ramstage-y += uart.c uart_console.c - -real-target: $(obj)/BOOT0 - -get_bootblock_size= \ - $(eval bb_s=$(shell $(CBFSTOOL) $(1) print | grep bootblocksize | \ - sed 's/[^0-9 ]//g')) \ - $(shell echo $$(($(word 2, $(strip $(bb_s)))))) - -# This tool is used to prepend a header to coreboot.rom to trick the SoC into -# loading out bootblock -# -MKSUNXIBOOT:=$(objutil)/mksunxiboot -$(MKSUNXIBOOT): $(top)/util/arm_boot_tools/mksunxiboot/mksunxiboot.c - @printf " HOSTCC $(subst $(obj)/,,$(@))\n" - $(HOSTCC) $(HOSTCFLAGS) -o $@ $< - -# The boot ROM in the SoC will start loading code if a special BOOT0 header is -# found (at an offset of 8KiB in either NAND or SD), and the checksum is -# correct. This header is added by the 'mxsunxiboot' tool, which is provided -# under util/arm_boot_tools/mksunxiboot. The boot ROM will load at most 24KiB of -# data to SRAM. The BOOT0 header takes 32 bytes, so bootblock is limited to -# 24KiB - 32 bytes. -# TODO: make mksunxiboot take the bootblock size as a parameter -# TODO: print an error if bootblock is too large (maybe place ROMSTAGE at the -# exact offset needed to collide with the bootblock) -# FIXME: A10 loads 24KiB. According to Oliver other chips load a little more -# -$(obj)/BOOT0: $(obj)/coreboot.rom $(MKSUNXIBOOT) - @printf " BOOT0 $(subst $(obj)/,,$(^))\n" - $(MKSUNXIBOOT) $(word 1, $^) $@ diff --git a/src/cpu/allwinner/a10/bootblock.c b/src/cpu/allwinner/a10/bootblock.c deleted file mode 100644 index 471104b0ed..0000000000 --- a/src/cpu/allwinner/a10/bootblock.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Allwinner A10 bootblock initialization - * - */ - -#include -#include -#include - -void bootblock_soc_init(void) -{ - uint32_t sctlr; - - /* enable dcache */ - sctlr = read_sctlr(); - sctlr |= SCTLR_C; - write_sctlr(sctlr); -} diff --git a/src/cpu/allwinner/a10/bootblock_media.c b/src/cpu/allwinner/a10/bootblock_media.c deleted file mode 100644 index c89cac0ceb..0000000000 --- a/src/cpu/allwinner/a10/bootblock_media.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * CBFS accessors for bootblock stage. - * - */ -#include -#include - -const struct region_device *boot_device_ro(void) -{ - printk(BIOS_ERR, "Oh my! I don't know how to access CBFS yet."); - return NULL; -} diff --git a/src/cpu/allwinner/a10/cbmem.c b/src/cpu/allwinner/a10/cbmem.c deleted file mode 100644 index a4c563a30e..0000000000 --- a/src/cpu/allwinner/a10/cbmem.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Provides cbmem utilities for romstage and ramstage - * - */ - -#include "ram_segs.h" -#include - -void *cbmem_top(void) -{ - return a1x_get_cbmem_top(); -} diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c deleted file mode 100644 index 9e4e93dfe1..0000000000 --- a/src/cpu/allwinner/a10/clock.c +++ /dev/null @@ -1,283 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Helpers for clock control and gating on Allwinner CPUs - */ - -#include "clock.h" - -#include -#include -#include -#include - -static struct a10_ccm *const ccm = (void *)A1X_CCM_BASE; - -/** - * \brief Enable the clock source for the peripheral - * - * @param[in] periph peripheral and clock type to enable @see a1x_clken - */ -void a1x_periph_clock_enable(enum a1x_clken periph) -{ - void *addr; - u32 reg32; - - addr = (void *)A1X_CCM_BASE + (periph >> 5); - reg32 = read32(addr); - reg32 |= 1 << (periph & 0x1f); - write32(addr, reg32); -} - -/** - * \brief Disable the clock source for the peripheral - * - * @param[in] periph peripheral and clock type to disable @see a1x_clken - */ -void a1x_periph_clock_disable(enum a1x_clken periph) -{ - void *addr; - u32 reg32; - - addr = (void *)A1X_CCM_BASE + (periph >> 5); - reg32 = read32(addr); - reg32 &= ~(1 << (periph & 0x1f)); - write32(addr, reg32); -} - -/** - * \brief Configure PLL5 factors - * - * This is a low-level accessor to configure the divisors and multipliers of - * PLL5. PLL5 uses two factors to multiply the 24MHz oscillator clock to - * generate a pre-clock. The pre-divided clock is then divided by one of two - * independent divisors, one for DRAM, and another for peripherals clocked from - * this PLL. If the PLL was previously disabled, this function will enable it. - * Other than that, this function only modifies these factors, and leaves the - * other settings unchanged. - * - * The output clocks are given by the following formulas: - * - * Pre-clock = (24 MHz * N * K) <- Must be between 240MHz and 2GHz - * DRAM clock = pre / M - * Other module = pre / P - * - * It is the caller's responsibility to make sure the pre-divided clock falls - * within the operational range of the PLL, and that the divisors and - * multipliers are within their ranges. - * - * @param[in] mul_n Multiplier N, between 0 and 32 - * @param[in] mul_k Multiplier K, between 1 and 4 - * @param[in] div_m DRAM clock divisor, between 1 and 4 - * @param[in] exp_div_p Peripheral clock divisor exponent, between 0 and 3 - * (P = 1/2/4/8, respectively) - */ -void a1x_pll5_configure(u8 mul_n, u8 mul_k, u8 div_m, u8 exp_div_p) -{ - u32 reg32; - - reg32 = read32(&ccm->pll5_cfg); - reg32 &= ~(PLL5_FACTOR_M_MASK | PLL5_FACTOR_N_MASK | - PLL5_FACTOR_K_MASK | PLL5_DIV_EXP_P_MASK); - /* The M1 factor is not documented in the datasheet, and the reference - * raminit code does not use it. Whether this is a fractional divisor, - * or an additional divisor is unknown, so don't use it for now */ - reg32 &= ~PLL5_FACTOR_M1_MASK; - reg32 |= (PLL5_FACTOR_M(div_m) | PLL5_FACTOR_N(mul_n) | - PLL5_FACTOR_K(mul_k) | PLL5_DIV_EXP_P(exp_div_p)); - reg32 |= PLL5_PLL_ENABLE; - write32(&ccm->pll5_cfg, reg32); -} - -/** - * \brief Enable the clock output to DRAM chips - * - * This enables the DRAM clock to be sent to DRAM chips. This should normally be - * done after PLL5 is configured and locked. Note that the clock may be gated, - * and also needs to be ungated in order to reach the DDR chips. - * Also see @ref clock_ungate_dram_clk_output - */ -void a1x_pll5_enable_dram_clock_output(void) -{ - setbits_le32(&ccm->pll5_cfg, PLL5_DDR_CLK_OUT_EN); -} - -/** - * \brief Ungate the clock to DRAM chips - * - * Although the DRAM clock output may be enabled, it is by default gated. It - * needs to be ungated before reaching DRAM. - */ -void a1x_ungate_dram_clock_output(void) -{ - setbits_le32(&ccm->dram_clk_cfg, DRAM_CTRL_DCLK_OUT); -} - -/** - * \brief Gate the clock to DRAM chips - * - * Disable the clock to DRAM without altering PLL configuration, by closing the - * DRAM clock gate. - */ -void a1x_gate_dram_clock_output(void) -{ - clrbits_le32(&ccm->dram_clk_cfg, DRAM_CTRL_DCLK_OUT); -} - -/* - * Linker doesn't garbage collect and the function below adds about half - * kilobyte to the bootblock, and log2_ceil is not available in the bootblock. - */ -#ifndef __BOOTBLOCK__ - -#define PLL1_CFG(N, K, M, P_EXP) \ - ((1 << 31 | 0 << 30 | 8 << 26 | 0 << 25 | 16 << 20 | 2 << 13) | \ - (P_EXP) << 16 | (N) << 8 | \ - (K - 1) << 4 | 0 << 3 | 0 << 2 | (M -1) << 0) - -static const struct { - u32 pll1_cfg; - u16 freq_mhz; -} pll1_table[] = { - /* PLL1 output = (24MHz * N * K) / (M * P) */ - { PLL1_CFG(16, 1, 1, 0), 384 }, - { PLL1_CFG(16, 2, 1, 0), 768 }, - { PLL1_CFG(20, 2, 1, 0), 960 }, - { PLL1_CFG(21, 2, 1, 0), 1008 }, - { PLL1_CFG(22, 2, 1, 0), 1056 }, - { PLL1_CFG(23, 2, 1, 0), 1104 }, - { PLL1_CFG(24, 2, 1, 0), 1152 }, - { PLL1_CFG(25, 2, 1, 0), 1200 }, - { PLL1_CFG(26, 2, 1, 0), 1248 }, - { PLL1_CFG(27, 2, 1, 0), 1296 }, - { PLL1_CFG(28, 2, 1, 0), 1344 }, - { PLL1_CFG(29, 2, 1, 0), 1392 }, - { PLL1_CFG(30, 2, 1, 0), 1440 }, - { PLL1_CFG(31, 2, 1, 0), 1488 }, - { PLL1_CFG(20, 4, 1, 0), 1944 }, -}; - -static void cpu_clk_src_switch(u32 clksel_bits) -{ - u32 reg32; - - reg32 = read32(&ccm->cpu_ahb_apb0_cfg); - reg32 &= ~CPU_CLK_SRC_MASK; - reg32 |= clksel_bits & CPU_CLK_SRC_MASK; - write32(&ccm->cpu_ahb_apb0_cfg, reg32); -} - -static void change_sys_divisors(u8 axi, u8 ahb_exp, u8 apb0_exp) -{ - u32 reg32; - - reg32 = read32(&ccm->cpu_ahb_apb0_cfg); - /* Not a typo: We want to keep only the CLK_SRC bits */ - reg32 &= CPU_CLK_SRC_MASK; - reg32 |= ((axi - 1) << 0) & AXI_DIV_MASK; - reg32 |= (ahb_exp << 4) & AHB_DIV_MASK; - reg32 |= (apb0_exp << 8) & APB0_DIV_MASK; - write32(&ccm->cpu_ahb_apb0_cfg, reg32); -} - -static void spin_delay(u32 loops) -{ - volatile u32 x = loops; - while (x--); -} - -/** - * \brief Configure the CPU clock and PLL1 - * - * To run at full speed, the CPU uses PLL1 as the clock source. AXI, AHB, and - * APB0 are derived from the CPU clock, and need to be kept within certain - * limits. This function configures PLL1 as close as possible to the desired - * frequency, based on a set of known working configurations for PLL1. It then - * calculates and applies the appropriate divisors for the AXI/AHB/APB0 clocks, - * before finally switching the CPU to run from the new clock. - * No further configuration of the CPU clock or divisors is needed. after - * calling this function. - * - * @param[in] cpu_clk_mhz Desired CPU clock, in MHz - */ -void a1x_set_cpu_clock(u16 cpu_clk_mhz) -{ - int i = 0; - u8 axi, ahb, ahb_exp, apb0, apb0_exp; - u32 actual_mhz; - - /* - * Rated clock for PLL1 is 2000 MHz, but there is no combination of - * parameters that yields that exact frequency. 1944 MHz is the highest. - */ - if (cpu_clk_mhz > 1944) { - printk(BIOS_CRIT, "BUG! maximum PLL1 clock is 1944 MHz," - "but asked to clock CPU at %d MHz\n", - cpu_clk_mhz); - cpu_clk_mhz = 1944; - } - /* Find target frequency */ - while (pll1_table[i].freq_mhz < cpu_clk_mhz) - i++; - - actual_mhz = pll1_table[i].freq_mhz; - - if (cpu_clk_mhz != actual_mhz) { - printk(BIOS_WARNING, "Parameters for %d MHz not available, " - "setting CPU clock at %d MHz\n", - cpu_clk_mhz, actual_mhz); - } - - /* - * Calculate system clock divisors: - * The minimum clock divisor for APB0 is 2, which guarantees that AHB0 - * will always be in spec, as long as AHB is in spec, although the max - * AHB0 clock we can get is 125 MHz - */ - axi = DIV_ROUND_UP(actual_mhz, 450); /* Max 450 MHz */ - ahb = DIV_ROUND_UP(actual_mhz/axi, 250); /* Max 250 MHz */ - apb0 = 2; /* Max 150 MHz */ - - ahb_exp = log2_ceil(ahb); - ahb = 1 << ahb_exp; - apb0_exp = 1; - - printk(BIOS_INFO, "CPU: %d MHz, AXI %d Mhz, AHB: %d MHz APB0: %d MHz\n", - actual_mhz, - actual_mhz / axi, - actual_mhz / (axi * ahb), - actual_mhz / (axi * ahb * apb0)); - - /* Keep the CPU off PLL1 while we change PLL parameters */ - cpu_clk_src_switch(CPU_CLK_SRC_OSC24M); - /* - * We can't use udelay() here. udelay() relies on timer 0, but timers - * have the habit of not ticking when the CPU is clocked from the main - * oscillator. - */ - spin_delay(8); - - change_sys_divisors(axi, ahb_exp, apb0_exp); - - /* Configure PLL1 at the desired frequency */ - write32(&ccm->pll1_cfg, pll1_table[i].pll1_cfg); - spin_delay(8); - - cpu_clk_src_switch(CPU_CLK_SRC_PLL1); - /* Here, we're running from PLL, so timers will tick */ - udelay(1); -} - -#endif /* __BOOTBLOCK__ */ diff --git a/src/cpu/allwinner/a10/clock.h b/src/cpu/allwinner/a10/clock.h deleted file mode 100644 index 110a6f8ec9..0000000000 --- a/src/cpu/allwinner/a10/clock.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2011 Allwinner Technology Co., Ltd. - * Tom Cubie - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Definitions for clock control and gating on Allwinner CPUs - */ - -#ifndef CPU_ALLWINNER_A10_CLOCK_H -#define CPU_ALLWINNER_A10_CLOCK_H - -#include "memmap.h" -#include - -/* CPU_AHB_APB0 config values */ -#define CPU_CLK_SRC_MASK (3 << 16) -#define CPU_CLK_SRC_OSC24M (1 << 16) -#define CPU_CLK_SRC_PLL1 (2 << 16) -#define APB0_DIV_MASK (3 << 8) -#define APB0_DIV_1 (0 << 8) -#define APB0_DIV_2 (1 << 8) -#define APB0_DIV_4 (2 << 8) -#define APB0_DIV_8 (3 << 8) -#define AHB_DIV_MASK (3 << 4) -#define AHB_DIV_1 (0 << 4) -#define AHB_DIV_2 (1 << 4) -#define AHB_DIV_4 (2 << 4) -#define AHB_DIV_8 (3 << 4) -#define AXI_DIV_MASK (3 << 0) -#define AXI_DIV_1 (0 << 0) -#define AXI_DIV_2 (1 << 0) -#define AXI_DIV_3 (2 << 0) -#define AXI_DIV_4 (3 << 0) - -/* APB1_CLK_DIV values */ -#define APB1_CLK_SRC_MASK (3 << 24) -#define APB1_CLK_SRC_OSC24M (0 << 24) -#define APB1_CLK_SRC_PLL6 (1 << 24) -#define APB1_CLK_SRC_32K (2 << 24) -#define APB1_RAT_N_MASK (3 << 16) -#define APB1_RAT_N(m) (((m) & 0x3) << 16) -#define APB1_RAT_M_MASK (0x1f << 0) -#define APB1_RAT_M(n) (((n) & 0x1f) << 0) - -/* PLL5_CFG values */ -#define PLL5_PLL_ENABLE (1 << 31) -#define PLL5_OUT_BYPASS_EN (1 << 30) -#define PLL5_DDR_CLK_OUT_EN (1 << 29) -#define PLL5_DIV_EXP_P_MASK (0x3 << 16) -#define PLL5_DIV_EXP_P(ep) ((ep << 16) & PLL5_DIV_EXP_P_MASK) -#define PLL5_DIV_P_1 (0x0 << 16) -#define PLL5_DIV_P_2 (0x1 << 16) -#define PLL5_DIV_P_4 (0x2 << 16) -#define PLL5_DIV_P_8 (0x3 << 16) -#define PLL5_FACTOR_N_MASK (0x1f << 8) -#define PLL5_FACTOR_N(n) ((n << 8) & PLL5_FACTOR_N_MASK) -#define PLL5_LDO_EN (1 << 7) -#define PLL5_FACTOR_K_MASK (0x3 << 4) -#define PLL5_FACTOR_K(k) ((((k) - 1) << 4) & PLL5_FACTOR_K_MASK) -#define PLL5_FACTOR_M1_MASK (0x3 << 2) -#define PLL5_FACTOR_M1(m1) (((m1) << 2) & PLL5_FACTOR_M1_MASK) -#define PLL5_FACTOR_M_MASK (0x3 << 0) -#define PLL5_FACTOR_M(m) ((((m) - 1) << 0) & PLL5_FACTOR_M_MASK) - -/* DRAM_CLK values*/ -#define DRAM_CTRL_DCLK_OUT (1 << 15) - -/* SDx_CLK values */ -#define SDx_CLK_GATE (1 << 31) -#define SDx_CLK_SRC_MASK (3 << 24) -#define SDx_CLK_SRC_OSC24M (0 << 24) -#define SDx_CLK_SRC_PLL6 (1 << 24) -#define SDx_CLK_SRC_PLL5 (2 << 24) -#define SDx_RAT_EXP_N_MASK (3 << 16) -#define SDx_RAT_EXP_N(n) (((n) << 16) & SDx_RAT_EXP_N_MASK) -#define SDx_RAT_M_MASK (0xf << 0) -#define SDx_RAT_M(m) ((((m) - 1) << 0) & SDx_RAT_M_MASK) -/** - * \brief Clock gating definitions - * - * The definitions are specified in the form: - * 31:5 register offset from A1X_CCM_BASE for the clock register - * 4:0 bit offset for the given peripheral - * - * The names have the form [periph_type][periph_number] - * - * These definitions are meant to be used with @ref a1x_periph_clock_enable and - * @ref a1x_periph_clock_disable - */ - -enum a1x_clken { - /* AXI module clock gating */ - A1X_CLKEN_DRAM_AXI = (0x5C << 5), - /* AHB0 module clock gating */ - A1X_CLKEN_USB0 = (0x60 << 5), - A1X_CLKEN_EHCI0, - RSVD_0x60_2, - A1X_CLKEN_EHCI1, - RSVD_0x60_4, - A1X_CLKEN_SS, - A1X_CLKEN_DMA, - A1X_CLKEN_BIST, - A1X_CLKEN_MMC0, - A1X_CLKEN_MMC1, - A1X_CLKEN_MMC2, - A1X_CLKEN_MMC3, - A1X_CLKEN_NC, - A1X_CLKEN_NAND, - A1X_CLKEN_SDRAM, - RSVD_0x60_15, - A1X_CLKEN_ACE, - A1X_CLKEN_EMAC, - A1X_CLKEN_TS, - RSVD_0x60_19, - A1X_CLKEN_SPI0, - A1X_CLKEN_SPI1, - A1X_CLKEN_SPI2, - A1X_CLKEN_SPI3, - A1X_CLKEN_PATA, - RSVD_0x60_25, - A1X_CLKEN_GPS, - /* AHB1 module clock gating */ - A1X_CLKEN_DRAM_VE = (0x64 << 5), - A1X_CLKEN_TVD, - A1X_CLKEN_TVE0, - A1X_CLKEN_TVE1, - A1X_CLKEN_LCD0, - A1X_CLKEN_LCD1, - RSVD_0x64_6, - RSVD_0x64_7, - A1X_CLKEN_CSI0, - A1X_CLKEN_CSI1, - RSVD_0x64_10, - A1X_CLKEN_HDMI, - A1X_CLKEN_DE_BE0, - A1X_CLKEN_DE_BE1, - A1X_CLKEN_DE_FE0, - A1X_CLKEN_DE_FE1, - RSVD_0x64_16, - RSVD_0x64_17, - A1X_CLKEN_MP, - RSVD_0x64_19, - A1X_CLKEN_MALI400, - /* APB0 module clock gating */ - A1X_CLKEN_CODEC = (0x68 << 5), - A1X_CLKEN_NC_APB, - A1X_CLKEN_AC97, - A1X_CLKEN_IIS, - RSVD_0x68_4, - A1X_CLKEN_PIO, - A1X_CLKEN_IR0, - A1X_CLKEN_IR1, - RSVD_0x68_8, - RSVD_0x68_9, - A1X_CLKEN_KEYPAD, - /* APB1 module clock gating */ - A1X_CLKEN_TWI0 = (0x6C << 5), - A1X_CLKEN_TWI1, - A1X_CLKEN_TWI2, - RSVD_0x6C_3, - A1X_CLKEN_CAN, - A1X_CLKEN_SCR, - A1X_CLKEN_PS20, - A1X_CLKEN_PS21, - RSVD_0x6C_8, - RSVD_0x6C_9, - RSVD_0x6C_10, - RSVD_0x6C_11, - RSVD_0x6C_12, - RSVD_0x6C_13, - RSVD_0x6C_14, - RSVD_0x6C_15, - A1X_CLKEN_UART0, - A1X_CLKEN_UART1, - A1X_CLKEN_UART2, - A1X_CLKEN_UART3, - A1X_CLKEN_UART4, - A1X_CLKEN_UART5, - A1X_CLKEN_UART6, - A1X_CLKEN_UART7, -}; - -struct a10_ccm { - u32 pll1_cfg; /* 0x00 pll1 control */ - u32 pll1_tun; /* 0x04 pll1 tuning */ - u32 pll2_cfg; /* 0x08 pll2 control */ - u32 pll2_tun; /* 0x0c pll2 tuning */ - u32 pll3_cfg; /* 0x10 pll3 control */ - u8 res0[0x4]; - u32 pll4_cfg; /* 0x18 pll4 control */ - u8 res1[0x4]; - u32 pll5_cfg; /* 0x20 pll5 control */ - u32 pll5_tun; /* 0x24 pll5 tuning */ - u32 pll6_cfg; /* 0x28 pll6 control */ - u32 pll6_tun; /* 0x2c pll6 tuning */ - u32 pll7_cfg; /* 0x30 pll7 control */ - u32 pll1_tun2; /* 0x34 pll5 tuning2 */ - u8 res2[0x4]; - u32 pll5_tun2; /* 0x3c pll5 tuning2 */ - u8 res3[0xc]; - u32 pll_lock_dbg; /* 0x4c pll lock time debug */ - u32 osc24m_cfg; /* 0x50 osc24m control */ - u32 cpu_ahb_apb0_cfg; /* 0x54 CPU, ahb and apb0 divide ratio */ - u32 apb1_clk_div_cfg; /* 0x58 apb1 clock dividor */ - u32 axi_gate; /* 0x5c axi module clock gating */ - u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ - u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ - u32 apb0_gate; /* 0x68 apb0 module clock gating */ - u32 apb1_gate; /* 0x6c apb1 module clock gating */ - u8 res4[0x10]; - u32 nand_sclk_cfg; /* 0x80 nand sub clock control */ - u32 ms_sclk_cfg; /* 0x84 memory stick sub clock control */ - u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ - u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ - u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ - u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ - u32 ts_clk_cfg; /* 0x98 transport stream clock control */ - u32 ss_clk_cfg; /* 0x9c */ - u32 spi0_clk_cfg; /* 0xa0 */ - u32 spi1_clk_cfg; /* 0xa4 */ - u32 spi2_clk_cfg; /* 0xa8 */ - u32 pata_clk_cfg; /* 0xac */ - u32 ir0_clk_cfg; /* 0xb0 */ - u32 ir1_clk_cfg; /* 0xb4 */ - u32 iis_clk_cfg; /* 0xb8 */ - u32 ac97_clk_cfg; /* 0xbc */ - u32 spdif_clk_cfg; /* 0xc0 */ - u32 keypad_clk_cfg; /* 0xc4 */ - u32 sata_clk_cfg; /* 0xc8 */ - u32 usb_clk_cfg; /* 0xcc */ - u32 gps_clk_cfg; /* 0xd0 */ - u32 spi3_clk_cfg; /* 0xd4 */ - u8 res5[0x28]; - u32 dram_clk_cfg; /* 0x100 */ - u32 be0_clk_cfg; /* 0x104 */ - u32 be1_clk_cfg; /* 0x108 */ - u32 fe0_clk_cfg; /* 0x10c */ - u32 fe1_clk_cfg; /* 0x110 */ - u32 mp_clk_cfg; /* 0x114 */ - u32 lcd0_ch0_clk_cfg; /* 0x118 */ - u32 lcd1_ch0_clk_cfg; /* 0x11c */ - u32 csi_isp_clk_cfg; /* 0x120 */ - u8 res6[0x4]; - u32 tvd_clk_reg; /* 0x128 */ - u32 lcd0_ch1_clk_cfg; /* 0x12c */ - u32 lcd1_ch1_clk_cfg; /* 0x130 */ - u32 csi0_clk_cfg; /* 0x134 */ - u32 csi1_clk_cfg; /* 0x138 */ - u32 ve_clk_cfg; /* 0x13c */ - u32 audio_codec_clk_cfg; /* 0x140 */ - u32 avs_clk_cfg; /* 0x144 */ - u32 ace_clk_cfg; /* 0x148 */ - u32 lvds_clk_cfg; /* 0x14c */ - u32 hdmi_clk_cfg; /* 0x150 */ - u32 mali_clk_cfg; /* 0x154 */ - u8 res7[0x4]; - u32 mbus_clk_cfg; /* 0x15c */ -} __packed; - -void a1x_periph_clock_enable(enum a1x_clken periph); -void a1x_periph_clock_disable(enum a1x_clken periph); - -void a1x_pll5_configure(u8 mul_n, u8 mul_k, u8 div_m, u8 exp_div_p); -void a1x_pll5_enable_dram_clock_output(void); -void a1x_ungate_dram_clock_output(void); -void a1x_gate_dram_clock_output(void); - -/* Not available in bootblock */ -void a1x_set_cpu_clock(u16 cpu_clk_mhz); - -#endif /* CPU_ALLWINNER_A10_CLOCK_H */ diff --git a/src/cpu/allwinner/a10/cpu.c b/src/cpu/allwinner/a10/cpu.c deleted file mode 100644 index 09f67662bf..0000000000 --- a/src/cpu/allwinner/a10/cpu.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Ramstage initialization for Allwinner CPUs - * - */ - -#include -#include - -static void cpu_enable_resources(struct device *dev) -{ - ram_resource(dev, 0, (uintptr_t)_dram/KiB, - CONFIG_DRAM_SIZE_MB << 10); - /* TODO: Declare CBFS cache as reserved? There's no guarantee we won't - * overwrite it. It seems to stay intact, being so high in RAM - */ -} - -static void cpu_init(struct device *dev) -{ - /* TODO: Check if anything else needs to be explicitly initialized */ -} - -static struct device_operations cpu_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = cpu_enable_resources, - .init = cpu_init, - .scan_bus = NULL, -}; - -static void a1x_cpu_enable_dev(struct device *dev) -{ - dev->ops = &cpu_ops; -} - -struct chip_operations cpu_allwinner_a10_ops = { - CHIP_NAME("CPU Allwinner A10") - .enable_dev = a1x_cpu_enable_dev, -}; diff --git a/src/cpu/allwinner/a10/dramc.h b/src/cpu/allwinner/a10/dramc.h deleted file mode 100644 index fe50acda69..0000000000 --- a/src/cpu/allwinner/a10/dramc.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2012 Allwinner Technology Co., Ltd. - * Berg Xing - * Tom Cubie - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License.or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Allwinner A10 platform dram register definition. - * - * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c - * and earlier U-Boot Allwiner A10 SPL work - */ - -#ifndef CPU_ALLWINNER_A10_DRAMC_H -#define CPU_ALLWINNER_A10_DRAMC_H - -#include - -#define DRAM_CCR_COMMAND_RATE_1T (0x1 << 5) -#define DRAM_CCR_DQS_GATE (0x1 << 14) -#define DRAM_CCR_DQS_DRIFT_COMP (0x1 << 17) -#define DRAM_CCR_ITM_OFF (0x1 << 28) -#define DRAM_CCR_DATA_TRAINING (0x1 << 30) -#define DRAM_CCR_INIT (0x1 << 31) - -#define DRAM_MEMORY_TYPE_DDR1 1 -#define DRAM_MEMORY_TYPE_DDR2 2 -#define DRAM_MEMORY_TYPE_DDR3 3 -#define DRAM_MEMORY_TYPE_LPDDR2 4 -#define DRAM_MEMORY_TYPE_LPDDR 5 -#define DRAM_DCR_TYPE (0x1 << 0) -#define DRAM_DCR_TYPE_DDR2 0x0 -#define DRAM_DCR_TYPE_DDR3 0x1 -#define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1) -#define DRAM_DCR_IO_WIDTH_MASK DRAM_DCR_IO_WIDTH(0x3) -#define DRAM_DCR_IO_WIDTH_8BIT 0x0 -#define DRAM_DCR_IO_WIDTH_16BIT 0x1 -#define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3) -#define DRAM_DCR_CHIP_DENSITY_MASK DRAM_DCR_CHIP_DENSITY(0x7) -#define DRAM_DCR_CHIP_DENSITY_256M 0x0 -#define DRAM_DCR_CHIP_DENSITY_512M 0x1 -#define DRAM_DCR_CHIP_DENSITY_1024M 0x2 -#define DRAM_DCR_CHIP_DENSITY_2048M 0x3 -#define DRAM_DCR_CHIP_DENSITY_4096M 0x4 -#define DRAM_DCR_CHIP_DENSITY_8192M 0x5 -#define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6) -#define DRAM_DCR_BUS_WIDTH_MASK DRAM_DCR_BUS_WIDTH(0x7) -#define DRAM_DCR_BUS_WIDTH_32BIT 0x3 -#define DRAM_DCR_BUS_WIDTH_16BIT 0x1 -#define DRAM_DCR_BUS_WIDTH_8BIT 0x0 -#define DRAM_DCR_NR_DLLCR_32BIT 5 -#define DRAM_DCR_NR_DLLCR_16BIT 3 -#define DRAM_DCR_NR_DLLCR_8BIT 2 -#define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10) -#define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3) -#define DRAM_DCR_CMD_RANK_ALL (0x1 << 12) -#define DRAM_DCR_MODE(n) (((n) & 0x3) << 13) -#define DRAM_DCR_MODE_MASK DRAM_DCR_MODE(0x3) -#define DRAM_DCR_MODE_SEQ 0x0 -#define DRAM_DCR_MODE_INTERLEAVE 0x1 - -#define DRAM_CSR_FAILED (0x1 << 20) - -#define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0) -#define DRAM_MCR_MODE_NORM_MASK DRAM_MCR_MOD_NORM(0x3) -#define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2) -#define DRAM_MCR_MODE_DQ_OUT_MASK DRAM_MCR_MODE_DQ_OUT(0x3) -#define DRAM_MCR_MODE_ADDR_OUT(n) (((n) & 0x3) << 4) -#define DRAM_MCR_MODE_ADDR_OUT_MASK DRAM_MCR_MODE_ADDR_OUT(0x3) -#define DRAM_MCR_MODE_DQ_IN_OUT(n) (((n) & 0x3) << 6) -#define DRAM_MCR_MODE_DQ_IN_OUT_MASK DRAM_MCR_MODE_DQ_IN_OUT(0x3) -#define DRAM_MCR_MODE_DQ_TURNON_DELAY(n) (((n) & 0x7) << 8) -#define DRAM_MCR_MODE_DQ_TURNON_DELAY_MASK DRAM_MCR_MODE_DQ_TURNON_DELAY(0x7) -#define DRAM_MCR_MODE_ADDR_IN (0x1 << 11) -#define DRAM_MCR_RESET (0x1 << 12) -#define DRAM_MCR_MODE_EN(n) (((n) & 0x3) << 13) -#define DRAM_MCR_MODE_EN_MASK DRAM_MCR_MOD_EN(0x3) -#define DRAM_MCR_DCLK_OUT (0x1 << 16) - -#define DRAM_DLLCR_NRESET (0x1 << 30) -#define DRAM_DLLCR_DISABLE (0x1 << 31) - -#define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20) -#define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff) - -#define DRAM_IOCR_ODT_EN(n) ((((n) & 0x3) << 30) | ((n) & 0x3) << 0) -#define DRAM_IOCR_ODT_EN_MASK DRAM_IOCR_ODT_EN(0x3) - -#define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0) -#define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7) -#define DRAM_MR_CAS_LAT(n) (((n) & 0x7) << 4) -#define DRAM_MR_CAS_LAT_MASK DRAM_MR_CAS_LAT(0x7) -#define DRAM_MR_WRITE_RECOVERY(n) (((n) & 0x7) << 9) -#define DRAM_MR_WRITE_RECOVERY_MASK DRAM_MR_WRITE_RECOVERY(0x7) -#define DRAM_MR_POWER_DOWN (0x1 << 12) - -#define DRAM_CSEL_MAGIC 0x16237495 - -struct a1x_dramc { - u32 ccr; /* 0x00 controller configuration register */ - u32 dcr; /* 0x04 dram configuration register */ - u32 iocr; /* 0x08 i/o configuration register */ - u32 csr; /* 0x0c controller status register */ - u32 drr; /* 0x10 dram refresh register */ - u32 tpr0; /* 0x14 dram timing parameters register 0 */ - u32 tpr1; /* 0x18 dram timing parameters register 1 */ - u32 tpr2; /* 0x1c dram timing parameters register 2 */ - u32 gdllcr; /* 0x20 global dll control register */ - u8 res0[0x28]; - u32 rslr0; /* 0x4c rank system latency register */ - u32 rslr1; /* 0x50 rank system latency register */ - u8 res1[0x8]; - u32 rdgr0; /* 0x5c rank dqs gating register */ - u32 rdgr1; /* 0x60 rank dqs gating register */ - u8 res2[0x34]; - u32 odtcr; /* 0x98 odt configuration register */ - u32 dtr0; /* 0x9c data training register 0 */ - u32 dtr1; /* 0xa0 data training register 1 */ - u32 dtar; /* 0xa4 data training address register */ - u32 zqcr0; /* 0xa8 zq control register 0 */ - u32 zqcr1; /* 0xac zq control register 1 */ - u32 zqsr; /* 0xb0 zq status register */ - u32 idcr; /* 0xb4 initializaton delay configure reg */ - u8 res3[0x138]; - u32 mr; /* 0x1f0 mode register */ - u32 emr; /* 0x1f4 extended mode register */ - u32 emr2; /* 0x1f8 extended mode register */ - u32 emr3; /* 0x1fc extended mode register */ - u32 dllctr; /* 0x200 dll control register */ - u32 dllcr[5]; /* 0x204 dll control register 0(byte 0) */ - /* 0x208 dll control register 1(byte 1) */ - /* 0x20c dll control register 2(byte 2) */ - /* 0x210 dll control register 3(byte 3) */ - /* 0x214 dll control register 4(byte 4) */ - u32 dqtr0; /* 0x218 dq timing register */ - u32 dqtr1; /* 0x21c dq timing register */ - u32 dqtr2; /* 0x220 dq timing register */ - u32 dqtr3; /* 0x224 dq timing register */ - u32 dqstr; /* 0x228 dqs timing register */ - u32 dqsbtr; /* 0x22c dqsb timing register */ - u32 mcr; /* 0x230 mode configure register */ - u8 res[0x8]; - u32 ppwrsctl; /* 0x23c pad power save control */ - u32 apr; /* 0x240 arbiter period register */ - u32 pldtr; /* 0x244 priority level data threshold reg */ - u8 res5[0x8]; - u32 hpcr[32]; /* 0x250 host port configure register */ - u8 res6[0x10]; - u32 csel; /* 0x2e0 controller select register */ -}; - -struct dram_para { - u32 clock; - u32 type; - u32 rank_num; - u32 density; - u32 io_width; - u32 bus_width; - u32 cas; - u32 zq; - u32 odt_en; - u32 size; - u32 tpr0; - u32 tpr1; - u32 tpr2; - u32 tpr3; - u32 tpr4; - u32 tpr5; - u32 emr1; - u32 emr2; - u32 emr3; -}; - -unsigned long dramc_init(struct dram_para *para); - -#endif /* CPU_ALLWINNER_A10_DRAMC_H */ diff --git a/src/cpu/allwinner/a10/gpio.c b/src/cpu/allwinner/a10/gpio.c deleted file mode 100644 index 7f6bbd8549..0000000000 --- a/src/cpu/allwinner/a10/gpio.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Basic GPIO helpers for Allwinner CPUs - */ - -#include "gpio.h" - -#include - -static struct a10_gpio *const gpio = (void *)GPIO_BASE; - -/** - * \brief Set a single output pin - * - * @param[in] port GPIO port of the pin (GPA -> GPS) - * @param[in] pin the pin number in the given port (1 -> 31) - */ -void gpio_set(u8 port, u8 pin) -{ - u32 reg32; - - if ((port > GPS)) - return; - - reg32 = gpio_read(port); - reg32 |= (1 << pin); - gpio_write(port, reg32); -} - -/** - * \brief Clear a single output pin - * - * @param[in] port GPIO port of the pin (GPA -> GPS) - * @param[in] pin the pin number in the given port (1 -> 31) - */ -void gpio_clear(u8 port, u8 pin) -{ - u32 reg32; - if ((port > GPS)) - return; - - reg32 = gpio_read(port); - reg32 &= ~(1 << pin); - gpio_write(port, reg32); -} - -/** - * \brief Get the status of a single input pin - * - * @param[in] port GPIO port of the pin (GPA -> GPS) - * @param[in] pin the pin number in the given port (1 -> 31) - * @return 1 if the pin is high, or 0 if the pin is low - */ -int gpio_get(u8 port, u8 pin) -{ - if ((port > GPS)) - return 0; - - return (gpio_read(port) & (1 << pin)) ? 1 : 0; -} - -/** - * \brief Write to a GPIO port - * - * Write the state of all output pins in the GPIO port. This only affects pins - * configured as output pins. - * - * @param[in] port GPIO port of the pin (GPA -> GPS) - * @param[in] val 32-bit mask indicating which pins to set. For a set bit, the - * corresponding pin will be set. Otherwise, it will be cleared - */ -void gpio_write(u8 port, u32 val) -{ - if ((port > GPS)) - return; - - write32(&gpio->port[port].dat, val); -} - -/** - * \brief Write to a GPIO port - * - * Read the state of all input pins in the GPIO port. - * - * @param[in] port GPIO port of the pin (GPA -> GPS) - * @return 32-bit mask indicating which pins are high. For each set bit, the - * corresponding pin is high. The value of bits corresponding to pins - * which are not configured as inputs is undefined. - */ -u32 gpio_read(u8 port) -{ - if ((port > GPS)) - return 0; - - return read32(&gpio->port[port].dat); -} diff --git a/src/cpu/allwinner/a10/gpio.h b/src/cpu/allwinner/a10/gpio.h deleted file mode 100644 index c05122fea6..0000000000 --- a/src/cpu/allwinner/a10/gpio.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License or (at your option) - * any later version. - * - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Definitions for GPIO and pin multiplexing on Allwinner CPUs - */ - -#ifndef __CPU_ALLWINNER_A10_PINMUX_H -#define __CPU_ALLWINNER_A10_PINMUX_H - -#include - -#define GPIO_BASE 0x01C20800 - -#define GPA 0 -#define GPB 1 -#define GPC 2 -#define GPD 3 -#define GPE 4 -#define GPF 5 -#define GPG 6 -#define GPH 7 -#define GPI 8 -#define GPS 9 - -/* GPIO pad functions valid for all pins */ -#define GPIO_PIN_FUNC_INPUT 0 -#define GPIO_PIN_FUNC_OUTPUT 1 - -struct a10_gpio_port { - u32 cfg[4]; - u32 dat; - u32 drv[2]; - u32 pul[2]; -} __packed; - -struct a10_gpio { - struct a10_gpio_port port[10]; - u8 reserved_0x168[0x98]; - - /* Offset 0x200 */ - u32 int_cfg[4]; - - u32 int_ctl; - u32 int_sta; - u8 reserved_0x21C[4]; - u32 int_deb; - - u32 sdr_pad_drv; - u32 sdr_pad_pul; -} __packed; - -/* gpio.c */ -void gpio_set(u8 port, u8 pin); -void gpio_clear(u8 port, u8 pin); -int gpio_get(u8 port, u8 pin); -void gpio_write(u8 port, u32 val); -u32 gpio_read(u8 port); - -/* pinmux.c */ -void gpio_set_pin_func(u8 port, u8 pin, u8 pad_func); -void gpio_set_multipin_func(u8 port, u32 pin_mask, u8 pad_func); - -#endif /* __CPU_ALLWINNER_A10_PINMUX_H */ diff --git a/src/cpu/allwinner/a10/memmap.h b/src/cpu/allwinner/a10/memmap.h deleted file mode 100644 index 2c02ec87f0..0000000000 --- a/src/cpu/allwinner/a10/memmap.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2011 Allwinner Technology Co., Ltd. - * Tom Cubie - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Memory map definitions for Allwinner A10 CPUs - */ - -#ifndef CPU_ALLWINNER_A10_MEMMAP_H -#define CPU_ALLWINNER_A10_MEMMAP_H - -#define A1X_SRAM_A1_BASE 0x00000000 -#define A1X_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ - -#define A1X_SRAM_A2_BASE 0x00004000 /* 16 kiB */ -#define A1X_SRAM_A3_BASE 0x00008000 /* 13 kiB */ -#define A1X_SRAM_A4_BASE 0x0000b400 /* 3 kiB */ -#define A1X_SRAM_D_BASE 0x01c00000 -#define A1X_SRAM_B_BASE 0x01c00000 /* 64 kiB (secure) */ - -#define A1X_SRAMC_BASE 0x01c00000 -#define A1X_DRAMC_BASE 0x01c01000 -#define A1X_DMA_BASE 0x01c02000 -#define A1X_NFC_BASE 0x01c03000 -#define A1X_TS_BASE 0x01c04000 -#define A1X_SPI0_BASE 0x01c05000 -#define A1X_SPI1_BASE 0x01c06000 -#define A1X_MS_BASE 0x01c07000 -#define A1X_TVD_BASE 0x01c08000 -#define A1X_CSI0_BASE 0x01c09000 -#define A1X_TVE0_BASE 0x01c0a000 -#define A1X_EMAC_BASE 0x01c0b000 -#define A1X_LCD0_BASE 0x01c0C000 -#define A1X_LCD1_BASE 0x01c0d000 -#define A1X_VE_BASE 0x01c0e000 -#define A1X_MMC0_BASE 0x01c0f000 -#define A1X_MMC1_BASE 0x01c10000 -#define A1X_MMC2_BASE 0x01c11000 -#define A1X_MMC3_BASE 0x01c12000 -#define A1X_USB0_BASE 0x01c13000 -#define A1X_USB1_BASE 0x01c14000 -#define A1X_SS_BASE 0x01c15000 -#define A1X_HDMI_BASE 0x01c16000 -#define A1X_SPI2_BASE 0x01c17000 -#define A1X_SATA_BASE 0x01c18000 -#define A1X_PATA_BASE 0x01c19000 -#define A1X_ACE_BASE 0x01c1a000 -#define A1X_TVE1_BASE 0x01c1b000 -#define A1X_USB2_BASE 0x01c1c000 -#define A1X_CSI1_BASE 0x01c1d000 -#define A1X_TZASC_BASE 0x01c1e000 -#define A1X_SPI3_BASE 0x01c1f000 - -#define A1X_CCM_BASE 0x01c20000 -#define A1X_INTC_BASE 0x01c20400 -#define A1X_PIO_BASE 0x01c20800 -#define A1X_TIMER_BASE 0x01c20c00 -#define A1X_SPDIF_BASE 0x01c21000 -#define A1X_AC97_BASE 0x01c21400 -#define A1X_IR0_BASE 0x01c21800 -#define A1X_IR1_BASE 0x01c21c00 - -#define A1X_IIS_BASE 0x01c22400 -#define A1X_LRADC_BASE 0x01c22800 -#define A1X_AD_DA_BASE 0x01c22c00 -#define A1X_KEYPAD_BASE 0x01c23000 -#define A1X_TZPC_BASE 0x01c23400 -#define A1X_SID_BASE 0x01c23800 -#define A1X_SJTAG_BASE 0x01c23c00 - -#define A1X_TP_BASE 0x01c25000 -#define A1X_PMU_BASE 0x01c25400 -#define A1X_CPUCFG_BASE 0x01c25c00 /* sun7i only ? */ - -#define A1X_UART0_BASE 0x01c28000 -#define A1X_UART1_BASE 0x01c28400 -#define A1X_UART2_BASE 0x01c28800 -#define A1X_UART3_BASE 0x01c28c00 -#define A1X_UART4_BASE 0x01c29000 -#define A1X_UART5_BASE 0x01c29400 -#define A1X_UART6_BASE 0x01c29800 -#define A1X_UART7_BASE 0x01c29c00 -#define A1X_PS2_0_BASE 0x01c2a000 -#define A1X_PS2_1_BASE 0x01c2a400 - -#define A1X_TWI0_BASE 0x01c2ac00 -#define A1X_TWI1_BASE 0x01c2b000 -#define A1X_TWI2_BASE 0x01c2b400 - -#define A1X_CAN_BASE 0x01c2bc00 - -#define A1X_SCR_BASE 0x01c2c400 - -#define A1X_GPS_BASE 0x01c30000 -#define A1X_MALI400_BASE 0x01c40000 - -/* module sram */ -#define A1X_SRAM_C_BASE 0x01d00000 - -#define A1X_DE_FE0_BASE 0x01e00000 -#define A1X_DE_FE1_BASE 0x01e20000 -#define A1X_DE_BE0_BASE 0x01e60000 -#define A1X_DE_BE1_BASE 0x01e40000 -#define A1X_MP_BASE 0x01e80000 -#define A1X_AVG_BASE 0x01ea0000 - -/* CoreSight Debug Module */ -#define A1X_CSDM_BASE 0x3f500000 - -#define A1X_DRAM_BASE 0x40000000 /* 2 GiB */ - -#define A1X_BROM_BASE 0xffff0000 /* 32 kiB */ - -#define A1X_CPU_CFG (A1X_TIMER_BASE + 0x13c) - -#endif /* CPU_ALLWINNER_A10_MEMMAP_H */ diff --git a/src/cpu/allwinner/a10/pinmux.c b/src/cpu/allwinner/a10/pinmux.c deleted file mode 100644 index 3415e4fed5..0000000000 --- a/src/cpu/allwinner/a10/pinmux.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * Helpers to multiplex and configure pins on Allwinner SoCs - * - */ - -#include "gpio.h" - -#include - -static struct a10_gpio *const gpio = (void *)GPIO_BASE; - -/** - * \brief Set the pad function of a single pin - * - * @param[in] port GPIO port of the pin (GPA -> GPS) - * @param[in] pin the pin number in the given port (1 -> 31) - * @param[in] pad_func The peripheral function to which to connect this pin - */ -void gpio_set_pin_func(u8 port, u8 pin, u8 pad_func) -{ - u8 reg, bit; - u32 reg32; - - if ((port > GPS)) - return; - - pin &= 0x1f; - reg = pin / 8; - bit = (pin % 8) * 4; - - reg32 = read32(&gpio->port[port].cfg[reg]); - reg32 &= ~(0xf << bit); - reg32 |= (pad_func & 0xf) << bit; - write32(&gpio->port[port].cfg[reg], reg32); -} - -/** - * \brief Set the pad function of a group of pins - * - * Multiplex a group of pins to the same pad function. This is useful for - * peripherals that use the same function number for several pins. This function - * allows those pins to be set with a single call. - * - * Example: - * gpio_set_multipin_func(GPB, (1 << 23) | (1 << 22), 2); - * - * @param[in] port GPIO port of the pin (GPA -> GPS) - * @param[in] pin_mask 32-bit mask indicating which pins to re-multiplex. For - * each set bit, the corresponding pin will be multiplexed. - * @param[in] pad_func The peripheral function to which to connect the pins - */ -void gpio_set_multipin_func(u8 port, u32 pin_mask, u8 pad_func) -{ - int j; - u8 reg, bit; - u32 reg32, mask_offset; - - if ((port > GPS)) - return; - - for (reg = 0; reg < 4; reg++) { - mask_offset = 8 * reg; - /* Don't run the inner loop if we're not touching any pins */ - if (!(pin_mask & (0xff << mask_offset))) - continue; - - reg32 = read32(&gpio->port[port].cfg[reg]); - for (j = 0; j < 8; j++) { - if (!(pin_mask & (1 << (j + mask_offset)))) - continue; - bit = j * 4; - reg32 &= ~(0xf << bit); - reg32 |= (pad_func & 0xf) << bit; - } - write32(&gpio->port[port].cfg[reg], reg32); - } -} diff --git a/src/cpu/allwinner/a10/ram_segs.h b/src/cpu/allwinner/a10/ram_segs.h deleted file mode 100644 index fa915cd203..0000000000 --- a/src/cpu/allwinner/a10/ram_segs.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * How we use DRAM on Allwinner CPUs - */ - -#include - -/* - * Put CBMEM at top of RAM - */ -static inline void *a1x_get_cbmem_top(void) -{ - return _dram + (CONFIG_DRAM_SIZE_MB << 20); -} - -/* - * By CBFS cache, we mean a cached copy, in RAM, of the entire CBFS region. - */ -static inline void *a1x_get_cbfs_cache_top(void) -{ - /* Arbitrary 16 MiB gap for cbmem tables and bouncebuffer */ - return a1x_get_cbmem_top() - (16 << 20); -} - -static inline void *a1x_get_cbfs_cache_base(void) -{ - return a1x_get_cbfs_cache_top() - CONFIG_ROM_SIZE; -} diff --git a/src/cpu/allwinner/a10/raminit.c b/src/cpu/allwinner/a10/raminit.c deleted file mode 100644 index 3c18183a6b..0000000000 --- a/src/cpu/allwinner/a10/raminit.c +++ /dev/null @@ -1,478 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Henrik Nordstrom - * Copyright (C) 2013 Luke Kenneth Casson Leighton - * Copyright (C) 2007-2012 Allwinner Technology Co., Ltd. - * Berg Xing - * Tom Cubie - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Allwinner A10 DRAM controller initialization - * - * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c - * and earlier U-Boot Allwiner A10 SPL work - */ - -#include "clock.h" -#include "dramc.h" -#include "memmap.h" -#include "timer.h" - -#include -#include - -static struct a1x_dramc *const dram = (void *)A1X_DRAMC_BASE; - -static void mctl_ddr3_reset(void) -{ - if (a1x_get_cpu_chip_revision() != A1X_CHIP_REV_A) { - setbits_le32(&dram->mcr, DRAM_MCR_RESET); - udelay(2); - clrbits_le32(&dram->mcr, DRAM_MCR_RESET); - } else { - clrbits_le32(&dram->mcr, DRAM_MCR_RESET); - udelay(2); - setbits_le32(&dram->mcr, DRAM_MCR_RESET); - } -} - -static void mctl_set_drive(void) -{ - clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3), - DRAM_MCR_MODE_EN(0x3) | 0xffc); -} - -static void mctl_itm_disable(void) -{ - clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF); -} - -static void mctl_itm_enable(void) -{ - clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF); -} - -static void mctl_enable_dll0(u32 phase) -{ - clrsetbits_le32(&dram->dllcr[0], 0x3f << 6, - ((phase >> 16) & 0x3f) << 6); - clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET, DRAM_DLLCR_DISABLE); - udelay(2); - - clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE); - udelay(22); - - clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_DISABLE, DRAM_DLLCR_NRESET); - udelay(22); -} - -/* - * Note: This differs from pm/standby in that it checks the bus width - */ -static void mctl_enable_dllx(u32 phase) -{ - u32 i, n, bus_width; - - bus_width = read32(&dram->dcr); - - if ((bus_width & DRAM_DCR_BUS_WIDTH_MASK) == - DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT)) - n = DRAM_DCR_NR_DLLCR_32BIT; - else - n = DRAM_DCR_NR_DLLCR_16BIT; - - for (i = 1; i < n; i++) { - clrsetbits_le32(&dram->dllcr[i], 0x4 << 14, - (phase & 0xf) << 14); - clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET, - DRAM_DLLCR_DISABLE); - phase >>= 4; - } - udelay(2); - - for (i = 1; i < n; i++) - clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET | - DRAM_DLLCR_DISABLE); - udelay(22); - - for (i = 1; i < n; i++) - clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE, - DRAM_DLLCR_NRESET); - udelay(22); -} - -static u32 hpcr_value[32] = { - 0x0301, 0x0301, 0x0301, 0x0301, - 0x0301, 0x0301, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0x1031, 0x1031, 0x0735, 0x1035, - 0x1035, 0x0731, 0x1031, 0x0735, - 0x1035, 0x1031, 0x0731, 0x1035, - 0x1031, 0x0301, 0x0301, 0x0731 -}; - -static void mctl_configure_hostport(void) -{ - u32 i; - - for (i = 0; i < 32; i++) - write32(&dram->hpcr[i], hpcr_value[i]); -} - -static void mctl_setup_dram_clock(u32 clk) -{ - /* setup DRAM PLL */ - a1x_pll5_configure(clk / 24, 2, 2, 1); - - /* FIXME: This bit is not documented for A10, and altering it doesn't - * seem to change anything. - * - * #define CCM_PLL5_CTRL_VCO_GAIN (0x1 << 19) - * reg_val = read32(&ccm->pll5_cfg); - * reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN; // PLL VCO Gain off - * write32(reg_val, &ccm->pll5_cfg); - */ - udelay(5500); - - a1x_pll5_enable_dram_clock_output(); - - /* reset GPS */ - /* FIXME: These bits are also undocumented, and seem to have no effect - * on A10. - * - * #define CCM_GPS_CTRL_RESET (0x1 << 0) - * #define CCM_GPS_CTRL_GATE (0x1 << 1) - * clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE); - */ - a1x_periph_clock_enable(A1X_CLKEN_GPS); - udelay(1); - a1x_periph_clock_disable(A1X_CLKEN_GPS); - - /* setup MBUS clock */ - /* FIXME: The MBUS does not seem to be present or do anything on A10. It - * is documented in the A13 user manual, but changing settings on A10 - * has no effect. - * - * #define CCM_MBUS_CTRL_M(n) (((n) & 0xf) << 0) - * #define CCM_MBUS_CTRL_M_MASK CCM_MBUS_CTRL_M(0xf) - * #define CCM_MBUS_CTRL_M_X(n) ((n) - 1) - * #define CCM_MBUS_CTRL_N(n) (((n) & 0xf) << 16) - * #define CCM_MBUS_CTRL_N_MASK CCM_MBUS_CTRL_N(0xf) - * #define CCM_MBUS_CTRL_N_X(n) (((n) >> 3) ? 3 : (((n) >> 2) ? 2 : (((n) >> 1) ? 1 : 0))) - * #define CCM_MBUS_CTRL_CLK_SRC(n) (((n) & 0x3) << 24) - * #define CCM_MBUS_CTRL_CLK_SRC_MASK CCM_MBUS_CTRL_CLK_SRC(0x3) - * #define CCM_MBUS_CTRL_CLK_SRC_HOSC 0x0 - * #define CCM_MBUS_CTRL_CLK_SRC_PLL6 0x1 - * #define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2 - * #define CCM_MBUS_CTRL_GATE (0x1 << 31) - * reg_val = CCM_MBUS_CTRL_GATE | - * CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) | - * CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) | - * CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2)); - * write32(reg_val, &ccm->mbus_clk_cfg); - */ - /* - * open DRAMC AHB & DLL register clock - * close it first - */ - a1x_periph_clock_disable(A1X_CLKEN_SDRAM); - - udelay(22); - - /* then open it */ - a1x_periph_clock_enable(A1X_CLKEN_SDRAM); - udelay(22); -} - -static int dramc_scan_readpipe(void) -{ - u32 reg32; - - /* data training trigger */ - setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING); - - /* check whether data training process has completed */ - while (read32(&dram->ccr) & DRAM_CCR_DATA_TRAINING); - - /* check data training result */ - reg32 = read32(&dram->csr); - if (reg32 & DRAM_CSR_FAILED) - return -1; - - return 0; -} - -static int dramc_scan_dll_para(void) -{ - const u32 dqs_dly[7] = { 0x3, 0x2, 0x1, 0x0, 0xe, 0xd, 0xc }; - const u32 clk_dly[15] = { 0x07, 0x06, 0x05, 0x04, 0x03, - 0x02, 0x01, 0x00, 0x08, 0x10, - 0x18, 0x20, 0x28, 0x30, 0x38 - }; - u32 clk_dqs_count[15]; - u32 dqs_i, clk_i, cr_i; - u32 max_val, min_val; - u32 dqs_index, clk_index; - - /* Find DQS_DLY Pass Count for every CLK_DLY */ - for (clk_i = 0; clk_i < 15; clk_i++) { - clk_dqs_count[clk_i] = 0; - clrsetbits_le32(&dram->dllcr[0], 0x3f << 6, - (clk_dly[clk_i] & 0x3f) << 6); - for (dqs_i = 0; dqs_i < 7; dqs_i++) { - for (cr_i = 1; cr_i < 5; cr_i++) { - clrsetbits_le32(&dram->dllcr[cr_i], - 0x4f << 14, - (dqs_dly[dqs_i] & 0x4f) << 14); - } - udelay(2); - if (dramc_scan_readpipe() == 0) - clk_dqs_count[clk_i]++; - } - } - /* Test DQS_DLY Pass Count for every CLK_DLY from up to down */ - for (dqs_i = 15; dqs_i > 0; dqs_i--) { - max_val = 15; - min_val = 15; - for (clk_i = 0; clk_i < 15; clk_i++) { - if (clk_dqs_count[clk_i] == dqs_i) { - max_val = clk_i; - if (min_val == 15) - min_val = clk_i; - } - } - if (max_val < 15) - break; - } - - /* Check if Find a CLK_DLY failed */ - if (!dqs_i) - goto fail; - - /* Find the middle index of CLK_DLY */ - clk_index = (max_val + min_val) >> 1; - if ((max_val == (15 - 1)) && (min_val > 0)) - /* if CLK_DLY[MCTL_CLK_DLY_COUNT] is very good, then the middle - * value can be more close to the max_val - */ - clk_index = (15 + clk_index) >> 1; - else if ((max_val < (15 - 1)) && (min_val == 0)) - /* if CLK_DLY[0] is very good, then the middle value can be more - * close to the min_val - */ - clk_index >>= 1; - if (clk_dqs_count[clk_index] < dqs_i) - clk_index = min_val; - - /* Find the middle index of DQS_DLY for the CLK_DLY got above, and Scan - * read pipe again - */ - clrsetbits_le32(&dram->dllcr[0], 0x3f << 6, - (clk_dly[clk_index] & 0x3f) << 6); - max_val = 7; - min_val = 7; - for (dqs_i = 0; dqs_i < 7; dqs_i++) { - clk_dqs_count[dqs_i] = 0; - for (cr_i = 1; cr_i < 5; cr_i++) { - clrsetbits_le32(&dram->dllcr[cr_i], - 0x4f << 14, - (dqs_dly[dqs_i] & 0x4f) << 14); - } - udelay(2); - if (dramc_scan_readpipe() == 0) { - clk_dqs_count[dqs_i] = 1; - max_val = dqs_i; - if (min_val == 7) - min_val = dqs_i; - } - } - - if (max_val < 7) { - dqs_index = (max_val + min_val) >> 1; - if ((max_val == (7 - 1)) && (min_val > 0)) - dqs_index = (7 + dqs_index) >> 1; - else if ((max_val < (7 - 1)) && (min_val == 0)) - dqs_index >>= 1; - if (!clk_dqs_count[dqs_index]) - dqs_index = min_val; - for (cr_i = 1; cr_i < 5; cr_i++) { - clrsetbits_le32(&dram->dllcr[cr_i], - 0x4f << 14, - (dqs_dly[dqs_index] & 0x4f) << 14); - } - udelay(2); - return dramc_scan_readpipe(); - } - -fail: - clrbits_le32(&dram->dllcr[0], 0x3f << 6); - for (cr_i = 1; cr_i < 5; cr_i++) - clrbits_le32(&dram->dllcr[cr_i], 0x4f << 14); - udelay(2); - - return dramc_scan_readpipe(); -} - -static void dramc_set_autorefresh_cycle(u32 clk) -{ - u32 reg32; - u32 tmp_val; - u32 reg_dcr; - - if (clk < 600) { - reg_dcr = read32(&dram->dcr); - if ((reg_dcr & DRAM_DCR_CHIP_DENSITY_MASK) <= - DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_1024M)) - reg32 = (131 * clk) >> 10; - else - reg32 = (336 * clk) >> 10; - - tmp_val = (7987 * clk) >> 10; - tmp_val = tmp_val * 9 - 200; - reg32 |= tmp_val << 8; - reg32 |= 0x8 << 24; - write32(&dram->drr, reg32); - } else { - write32(&dram->drr, 0x0); - } -} - -unsigned long dramc_init(struct dram_para *para) -{ - u32 reg32; - int ret_val; - - /* check input dram parameter structure */ - if (!para) - return 0; - - /* setup DRAM relative clock */ - mctl_setup_dram_clock(para->clock); - - /* reset external DRAM */ - mctl_ddr3_reset(); - - mctl_set_drive(); - - /* dram clock off */ - a1x_gate_dram_clock_output(); - - /* select dram controller 1 */ - write32(&dram->csel, DRAM_CSEL_MAGIC); - - mctl_itm_disable(); - mctl_enable_dll0(para->tpr3); - - /* configure external DRAM */ - reg32 = 0x0; - if (para->type == DRAM_MEMORY_TYPE_DDR3) - reg32 |= DRAM_DCR_TYPE_DDR3; - reg32 |= DRAM_DCR_IO_WIDTH(para->io_width >> 3); - - if (para->density == 256) - reg32 |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_256M); - else if (para->density == 512) - reg32 |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_512M); - else if (para->density == 1024) - reg32 |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_1024M); - else if (para->density == 2048) - reg32 |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_2048M); - else if (para->density == 4096) - reg32 |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_4096M); - else if (para->density == 8192) - reg32 |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_8192M); - else - reg32 |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_256M); - - reg32 |= DRAM_DCR_BUS_WIDTH((para->bus_width >> 3) - 1); - reg32 |= DRAM_DCR_RANK_SEL(para->rank_num - 1); - reg32 |= DRAM_DCR_CMD_RANK_ALL; - reg32 |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE); - write32(&dram->dcr, reg32); - - /* dram clock on */ - a1x_ungate_dram_clock_output(); - - udelay(1); - - while (read32(&dram->ccr) & DRAM_CCR_INIT); - - mctl_enable_dllx(para->tpr3); - - /* set odt impendance divide ratio */ - reg32 = ((para->zq) >> 8) & 0xfffff; - reg32 |= ((para->zq) & 0xff) << 20; - reg32 |= (para->zq) & 0xf0000000; - write32(&dram->zqcr0, reg32); - - /* set I/O configure register */ - reg32 = 0x00cc0000; - reg32 |= (para->odt_en) & 0x3; - reg32 |= ((para->odt_en) & 0x3) << 30; - write32(&dram->iocr, reg32); - - /* set refresh period */ - dramc_set_autorefresh_cycle(para->clock); - - /* set timing parameters */ - write32(&dram->tpr0, para->tpr0); - write32(&dram->tpr1, para->tpr1); - write32(&dram->tpr2, para->tpr2); - - if (para->type == DRAM_MEMORY_TYPE_DDR3) { - reg32 = DRAM_MR_BURST_LENGTH(0x0); - reg32 |= DRAM_MR_CAS_LAT(para->cas - 4); - reg32 |= DRAM_MR_WRITE_RECOVERY(0x5); - } else if (para->type == DRAM_MEMORY_TYPE_DDR2) { - reg32 = DRAM_MR_BURST_LENGTH(0x2); - reg32 |= DRAM_MR_CAS_LAT(para->cas); - reg32 |= DRAM_MR_WRITE_RECOVERY(0x5); - } - write32(&dram->mr, reg32); - - write32(&dram->emr, para->emr1); - write32(&dram->emr2, para->emr2); - write32(&dram->emr3, para->emr3); - - /* set DQS window mode */ - clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE); - - /* reset external DRAM */ - setbits_le32(&dram->ccr, DRAM_CCR_INIT); - while (read32(&dram->ccr) & DRAM_CCR_INIT); - - /* scan read pipe value */ - mctl_itm_enable(); - if (para->tpr3 & (0x1 << 31)) { - ret_val = dramc_scan_dll_para(); - if (ret_val == 0) - para->tpr3 = - (((read32(&dram->dllcr[0]) >> 6) & 0x3f) << 16) | - (((read32(&dram->dllcr[1]) >> 14) & 0xf) << 0) | - (((read32(&dram->dllcr[2]) >> 14) & 0xf) << 4) | - (((read32(&dram->dllcr[3]) >> 14) & 0xf) << 8) | - (((read32(&dram->dllcr[4]) >> 14) & 0xf) << 12); - } else { - ret_val = dramc_scan_readpipe(); - } - - if (ret_val < 0) - return 0; - - /* configure all host port */ - mctl_configure_hostport(); - - return para->size; -} diff --git a/src/cpu/allwinner/a10/timer.c b/src/cpu/allwinner/a10/timer.c deleted file mode 100644 index 87228a06d4..0000000000 --- a/src/cpu/allwinner/a10/timer.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Timer control and delays for Allwinner CPUs - * - */ - -#include -#include - -#include "timer.h" - -struct a1x_timer_module *const timer_module = (void *)A1X_TIMER_BASE; -struct a1x_timer *const tmr0 = - &((struct a1x_timer_module *)A1X_TIMER_BASE)->timer[0]; - -static inline u32 read_timer(void) -{ - return read32(&tmr0->val); -} - -void init_timer(void) -{ - u32 reg32; - /* Load the timer rollover value */ - write32(&tmr0->interval, 0xffffffff); - /* Configure the timer to run from 24MHz oscillator, no prescaler */ - reg32 = TIMER_CTRL_PRESC_DIV_EXP(0); - reg32 |= TIMER_CTRL_CLK_SRC_OSC24M; - reg32 |= TIMER_CTRL_RELOAD; - reg32 |= TIMER_CTRL_TMR_EN; - write32(&tmr0->ctrl, reg32); -} - -void udelay(unsigned usec) -{ - u32 curr_tick, last_tick; - s32 ticks_left; - - last_tick = read_timer(); - /* 24 timer ticks per microsecond (24 MHz, divided by 1) */ - ticks_left = usec * 24; - - /* FIXME: Should we consider timer rollover? - * From when we start the timer, we have almost three minutes before it - * rolls over, so we should be long into having booted our payload. - */ - while (ticks_left > 0) { - curr_tick = read_timer(); - /* Timer value decreases with each tick */ - ticks_left -= last_tick - curr_tick; - last_tick = curr_tick; - } - -} - -/* - * This function has nothing to do with timers; however, the chip revision - * register is in the timer module, so keep this function here. - */ -u8 a1x_get_cpu_chip_revision(void) -{ - write32(&timer_module->cpu_cfg, 0); - return (read32(&timer_module->cpu_cfg) >> 6) & 0x3; -} diff --git a/src/cpu/allwinner/a10/timer.h b/src/cpu/allwinner/a10/timer.h deleted file mode 100644 index b7658da35d..0000000000 --- a/src/cpu/allwinner/a10/timer.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2011 Allwinner Technology Co., Ltd. - * Tom Cubie - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License or (at your option) - * any later version - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Definitions for timer control on Allwinner CPUs - */ - -#ifndef CPU_ALLWINNER_A10_TIMER_H -#define CPU_ALLWINNER_A10_TIMER_H - -#include "memmap.h" -#include - -/* TMRx_CTRL values */ -#define TIMER_CTRL_MODE_SINGLE (1 << 7) -#define TIMER_CTRL_PRESC_MASK (0x7 << 4) -#define TIMER_CTRL_PRESC_DIV_EXP(ep) ((ep << 4) & TIMER_CTRL_PRESC_MASK) -#define TIMER_CTRL_CLK_SRC_MASK (0x3 << 2) -#define TIMER_CTRL_CLK_SRC_LOSC (0x0 << 2) -#define TIMER_CTRL_CLK_SRC_OSC24M (0x1 << 2) -#define TIMER_CTRL_CLK_SRC_PLL6 (0x2 << 2) -#define TIMER_CTRL_RELOAD (1 << 1) -#define TIMER_CTRL_TMR_EN (1 << 0) - -/* Chip revision definitions (found in CPU_CFG register) */ -#define A1X_CHIP_REV_A 0x0 -#define A1X_CHIP_REV_C1 0x1 -#define A1X_CHIP_REV_C2 0x2 -#define A1X_CHIP_REV_B 0x3 - - -/* General purpose timer */ -struct a1x_timer { - u32 ctrl; - u32 interval; - u32 val; - u8 res[4]; -} __packed; - -/* Audio video sync*/ -struct a1x_avs { - u32 ctrl; /* 0x80 */ - u32 cnt0; /* 0x84 */ - u32 cnt1; /* 0x88 */ - u32 div; /* 0x8c */ -} __packed; - -/* Watchdog */ -struct a1x_wdog { - u32 ctrl; /* 0x90 */ - u32 mode; /* 0x94 */ -} __packed; - -/* 64 bit counter */ -struct a1x_64cnt { - u32 ctrl; /* 0xa0 */ - u32 lo; /* 0xa4 */ - u32 hi; /* 0xa8 */ -} __packed; - -/* Rtc */ -struct a1x_rtc { - u32 ctrl; /* 0x100 */ - u32 yymmdd; /* 0x104 */ - u32 hhmmss; /* 0x108 */ -} __packed; - -/* Alarm */ -struct a1x_alarm { - u32 ddhhmmss; /* 0x10c */ - u32 hhmmss; /* 0x110 */ - u32 en; /* 0x114 */ - u32 irq_en; /* 0x118 */ - u32 irq_sta; /* 0x11c */ -} __packed; - -struct a1x_timer_module { - u32 irq_en; /* 0x00 */ - u32 irq_sta; /* 0x04 */ - u8 res1[8]; - struct a1x_timer timer[6]; /* We have 6 timers */ - u8 res2[16]; - struct a1x_avs avs; - struct a1x_wdog wdog; - u8 res3[8]; - struct a1x_64cnt cnt64; - u8 res4[0x58]; - struct a1x_rtc rtc; - struct a1x_alarm alarm; - u32 gp_data[4]; - u8 res5[8]; - u32 cpu_cfg; -} __packed; - -u8 a1x_get_cpu_chip_revision(void); - -#endif /* CPU_ALLWINNER_A10_TIMER_H */ diff --git a/src/cpu/allwinner/a10/twi.c b/src/cpu/allwinner/a10/twi.c deleted file mode 100644 index 01ee5a5c6f..0000000000 --- a/src/cpu/allwinner/a10/twi.c +++ /dev/null @@ -1,217 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Henrik Nordstrom - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Setup helpers for Two Wire Interface (TWI) (I2C) Allwinner CPUs - * - * Only functionality for I2C master is provided. - * Largely based on the uboot-sunxi code. - */ - -#include -#include -#include -#include - -#include "memmap.h" -#include "twi.h" - -#define TWI_BASE(n) (A1X_TWI0_BASE + 0x400 * (n)) - -#define TWI_TIMEOUT (50 * 1000) - -static u8 is_busy(struct a1x_twi *twi) -{ - return (read32(&twi->stat) != TWI_STAT_IDLE); -} - -static enum cb_err wait_until_idle(struct a1x_twi *twi) -{ - u32 i = TWI_TIMEOUT; - while (i-- && is_busy((twi))) - udelay(1); - return i ? CB_SUCCESS : CB_ERR; -} - -/* FIXME: This function is basic, and unintelligent */ -static void configure_clock(struct a1x_twi *twi, u32 speed_hz) -{ - /* FIXME: We assume clock is 24MHz, which may not be the case */ - u32 apb_clk = 24000000, m, n; - - /* Pre-divide the clock by 8 */ - n = 3; - m = (apb_clk >> n) / speed_hz; - write32(&twi->clk, TWI_CLK_M(m) | TWI_CLK_N(n)); -} - -void a1x_twi_init(u8 bus, u32 speed_hz) -{ - u32 i = TWI_TIMEOUT; - struct a1x_twi *twi = (void *)TWI_BASE(bus); - - configure_clock(twi, speed_hz); - - /* Enable the I2C bus */ - write32(&twi->ctl, TWI_CTL_BUS_EN); - /* Issue soft reset */ - write32(&twi->reset, 1); - - while (i-- && read32(&twi->reset)) - udelay(1); -} - -static void clear_interrupt_flag(struct a1x_twi *twi) -{ - write32(&twi->ctl, read32(&twi->ctl) & ~TWI_CTL_INT_FLAG); -} - -static void i2c_send_data(struct a1x_twi *twi, u8 data) -{ - write32(&twi->data, data); - clear_interrupt_flag(twi); -} - -static enum twi_status wait_for_status(struct a1x_twi *twi) -{ - u32 i = TWI_TIMEOUT; - /* Wait until interrupt is asserted again */ - while (i-- && !(read32(&twi->ctl) & TWI_CTL_INT_FLAG)) - udelay(1); - /* A timeout here most likely indicates a bus error */ - return i ? read32(&twi->stat) : TWI_STAT_BUS_ERROR; -} - -static void i2c_send_start(struct a1x_twi *twi) -{ - u32 reg32, i; - - /* Send START condition */ - reg32 = read32(&twi->ctl); - reg32 &= ~TWI_CTL_INT_FLAG; - reg32 |= TWI_CTL_M_START; - write32(&twi->ctl, reg32); - - /* M_START is automatically cleared after condition is transmitted */ - i = TWI_TIMEOUT; - while (i-- && (read32(&twi->ctl) & TWI_CTL_M_START)) - udelay(1); -} - -static void i2c_send_stop(struct a1x_twi *twi) -{ - u32 reg32; - - /* Send STOP condition */ - reg32 = read32(&twi->ctl); - reg32 &= ~TWI_CTL_INT_FLAG; - reg32 |= TWI_CTL_M_STOP; - write32(&twi->ctl, reg32); -} - -static int i2c_read(struct a1x_twi *twi, uint8_t chip, - uint8_t *buf, size_t len) -{ - unsigned count = len; - enum twi_status expected_status; - - /* Send restart for read */ - i2c_send_start(twi); - if (wait_for_status(twi) != TWI_STAT_TX_RSTART) - return CB_ERR; - - /* Send chip address */ - i2c_send_data(twi, chip << 1 | 1); - if (wait_for_status(twi) != TWI_STAT_TX_AR_ACK) - return CB_ERR; - - /* Start ACK-ing received data */ - setbits_le32(&twi->ctl, TWI_CTL_A_ACK); - expected_status = TWI_STAT_RXD_ACK; - - /* Read data */ - while (count > 0) { - if (count == 1) { - /* Do not ACK the last byte */ - clrbits_le32(&twi->ctl, TWI_CTL_A_ACK); - expected_status = TWI_STAT_RXD_NAK; - } - - clear_interrupt_flag(twi); - - if (wait_for_status(twi) != expected_status) - return CB_ERR; - - *buf++ = read32(&twi->data); - count--; - } - - return len; -} - -static int i2c_write(struct a1x_twi *twi, uint8_t chip, - const uint8_t *buf, size_t len) -{ - size_t count = len; - - i2c_send_start(twi); - if (wait_for_status(twi) != TWI_STAT_TX_START) - return CB_ERR; - - /* Send chip address */ - i2c_send_data(twi, chip << 1); - if (wait_for_status(twi) != TWI_STAT_TX_AW_ACK) - return CB_ERR; - - /* Send data */ - while (count > 0) { - i2c_send_data(twi, *buf++); - if (wait_for_status(twi) != TWI_STAT_TXD_ACK) - return CB_ERR; - count--; - } - - return len; -} - -int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments, int count) -{ - int i, ret = CB_SUCCESS; - struct i2c_msg *seg = segments; - struct a1x_twi *twi = (void *)TWI_BASE(bus); - - - if (wait_until_idle(twi) != CB_SUCCESS) - return CB_ERR; - - for (i = 0; i < count; i++) { - seg = segments + i; - - if (seg->flags & I2C_M_RD) { - ret = i2c_read(twi, seg->slave, seg->buf, seg->len); - if (ret < 0) - break; - } else { - ret = i2c_write(twi, seg->slave, seg->buf, seg->len); - if (ret < 0) - break; - } - } - - /* Don't worry about the status. STOP is on a best-effort basis */ - i2c_send_stop(twi); - - return ret; -} diff --git a/src/cpu/allwinner/a10/twi.h b/src/cpu/allwinner/a10/twi.h deleted file mode 100644 index 833b1dc101..0000000000 --- a/src/cpu/allwinner/a10/twi.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Definitions Two Wire Interface (TWI) (I2C) Allwinner CPUs - */ - -#ifndef CPU_ALLWINNER_A10_TWI_H -#define CPU_ALLWINNER_A10_TWI_H - -#include - -/* TWI_CTL values */ -#define TWI_CTL_INT_EN (1 << 7) -#define TWI_CTL_BUS_EN (1 << 6) -#define TWI_CTL_M_START (1 << 5) -#define TWI_CTL_M_STOP (1 << 4) -#define TWI_CTL_INT_FLAG (1 << 3) -#define TWI_CTL_A_ACK (1 << 2) - -/* TWI_STAT values */ -enum twi_status { - TWI_STAT_BUS_ERROR = 0x00, /**< Bus error */ - TWI_STAT_TX_START = 0x08, /**< START sent */ - TWI_STAT_TX_RSTART = 0x10, /**< Repeated START sent */ - TWI_STAT_TX_AW_ACK = 0x18, /**< Sent address+read, ACK */ - TWI_STAT_TX_AW_NAK = 0x20, /**< Sent address+read, NAK */ - TWI_STAT_TXD_ACK = 0x28, /**< Sent data, got ACK */ - TWI_STAT_TXD_NAK = 0x30, /**< Sent data, no ACK */ - TWI_STAT_LOST_ARB = 0x38, /**< Lost arbitration */ - TWI_STAT_TX_AR_ACK = 0x40, /**< Sent address+write, ACK */ - TWI_STAT_TX_AR_NAK = 0x48, /**< Sent address+write, NAK */ - TWI_STAT_RXD_ACK = 0x50, /**< Got data, sent ACK */ - TWI_STAT_RXD_NAK = 0x58, /**< Got data, no ACK */ - TWI_STAT_IDLE = 0xf8, /**< Bus idle*/ -}; - -/* TWI_CLK values */ -#define TWI_CLK_M_MASK (0xf << 3) -#define TWI_CLK_M(m) (((m - 1) << 3) & TWI_CLK_M_MASK) -#define TWI_CLK_N_MASK (0x7 << 0) -#define TWI_CLK_N(n) ((n) & TWI_CLK_N_MASK) - -struct a1x_twi { - u32 addr; /**< 0x00: Slave address */ - u32 xaddr; /**< 0x04: Extended slave address */ - u32 data; /**< 0x08: Data byte */ - u32 ctl; /**< 0x0C: Control register */ - u32 stat; /**< 0x10: Status register */ - u32 clk; /**< 0x14: Clock control register */ - u32 reset; /**< 0x18: Software reset */ - u32 efr; /**< 0x1C: Enhanced Feature register */ - u32 lcr; /**< 0x20: Line control register */ -}; - -void a1x_twi_init(u8 bus, u32 speed_hz); - -#endif /* CPU_ALLWINNER_A10_TWI_H */ diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c deleted file mode 100644 index c721a67b07..0000000000 --- a/src/cpu/allwinner/a10/uart.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Uart setup helpers for Allwinner SoCs - * - * - */ - -#include "uart.h" -#include -#include -#include - -/** - * \brief Configure line control settings for UART - */ -static void a10_uart_configure(struct a10_uart *uart, u32 baud_rate, u8 data_bits, - enum uart_parity parity, u8 stop_bits) -{ - u32 reg32; - u16 div; - - div = (u16) uart_baudrate_divisor(baud_rate, - uart_platform_refclk(), 16); - /* Enable access to Divisor Latch register */ - write32(&uart->lcr, UART8250_LCR_DLAB); - /* Set baudrate */ - write32(&uart->dlh, (div >> 8) & 0xff); - write32(&uart->dll, div & 0xff); - /* Set line control */ - reg32 = (data_bits - 5) & UART8250_LCR_WLS_MSK; - switch (parity) { - case UART_PARITY_ODD: - reg32 |= UART8250_LCR_PEN; - break; - case UART_PARITY_EVEN: - reg32 |= UART8250_LCR_PEN; - reg32 |= UART8250_LCR_EPS; - break; - case UART_PARITY_NONE: /* Fall through */ - default: - break; - } - write32(&uart->lcr, reg32); -} - -static void a10_uart_enable_fifos(struct a10_uart *uart) -{ - write32(&uart->fcr, UART8250_FCR_FIFO_EN); -} - -static int tx_fifo_full(struct a10_uart *uart) -{ - /* This may be a misnomer, or a typo in the datasheet. THRE indicates - * that the TX register is empty, not that the FIFO is not full, but - * this may be due to a datasheet typo. Keep the current name to signal - * intent. */ - return !(read32(&uart->lsr) & UART8250_LSR_THRE); -} - -static int rx_fifo_empty(struct a10_uart *uart) -{ - return !(read32(&uart->lsr) & UART8250_LSR_DR); -} - -/** - * \brief Read a single byte from the UART. - * - * Blocks until at least a byte is available. - */ -static u8 a10_uart_rx_blocking(struct a10_uart *uart) -{ - while (rx_fifo_empty(uart)); - - return read32(&uart->rbr); -} - -/** - * \brief Write a single byte to the UART. - * - * Blocks until there is space in the FIFO. - */ -static void a10_uart_tx_blocking(struct a10_uart *uart, u8 data) -{ - while (tx_fifo_full(uart)); - - return write32(&uart->thr, data); -} - - -void uart_init(int idx) -{ - struct a10_uart *uart_base = uart_platform_baseptr(idx); - - /* Use default 8N1 encoding */ - a10_uart_configure(uart_base, get_uart_baudrate(), - 8, UART_PARITY_NONE, 1); - a10_uart_enable_fifos(uart_base); -} - -unsigned char uart_rx_byte(int idx) -{ - return a10_uart_rx_blocking(uart_platform_baseptr(idx)); -} - -void uart_tx_byte(int idx, unsigned char data) -{ - a10_uart_tx_blocking(uart_platform_baseptr(idx), data); -} - -void uart_tx_flush(int idx) -{ -} diff --git a/src/cpu/allwinner/a10/uart.h b/src/cpu/allwinner/a10/uart.h deleted file mode 100644 index a57fc9c361..0000000000 --- a/src/cpu/allwinner/a10/uart.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Definitions for UART on Allwinner CPUs - * - * The UART on the A10 seems to be 8250-compatible, however, this has not been - * verified. Our 8250mem code is specific to x86, and does not yet work, so we - * have to re-implement it ARM-style for the time being. The register - * definitions are present in , and are not redefined here. - * - */ - -#ifndef CPU_ALLWINNER_A10_UART_H -#define CPU_ALLWINNER_A10_UART_H - -#include - -struct a10_uart { - union { - /* operational mode */ - u32 rbr; /* receiver buffer (read) */ - u32 thr; /* transmit holding (write) */ - /* config mode (DLAB set) */ - u32 dll; /* divisor latches low */ - }; - - union { - /* operational mode */ - u32 ier; /* interrupt enable */ - /* config mode (DLAB set) */ - u32 dlh; /* divisor latches high */ - }; - - union { - u32 iir; /* interrupt ID (read) */ - u32 fcr; /* FIFO control (write) */ - }; - - u32 lcr; /* line control */ - - /* 0x10 */ - u32 mcr; /* modem control */ - u32 lsr; /* line status, read-only */ - u32 msr; /* modem status */ - u32 sch; /* scratch register */ - - u8 reserved_0x20[0x50]; - - /* 0x70 */ - u8 reserved_0x70[0xc]; - u32 usr; /* UART status register */ - - /* 0x80 */ - u32 tfl; /* Transmit FIFO level */ - u32 rfl; /* Receive FIFO level */ - u8 reserved_0x88[0x18]; - - /* 0xa0 */ - u8 reserved_0xa0[4]; - u32 halt; /* Halt register */ - -} __packed; - -enum uart_parity { - UART_PARITY_NONE, - UART_PARITY_EVEN, - UART_PARITY_ODD, -}; - -#endif /* CPU_ALLWINNER_A10_UART_H */ diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c deleted file mode 100644 index 363a41a129..0000000000 --- a/src/cpu/allwinner/a10/uart_console.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Glue to UART code to enable serial console - */ - -#include -#include -#include - -#include "memmap.h" - -uintptr_t uart_platform_base(int idx) -{ - /* UART blocks are mapped 0x400 bytes apart */ - if (idx < 8) - return A1X_UART0_BASE + 0x400 * idx; - else - return 0; -} - -/* FIXME: We assume clock is 24MHz, which may not be the case. */ -unsigned int uart_platform_refclk(void) -{ - return 24000000; -} - -#ifndef __PRE_RAM__ -void uart_fill_lb(void *data) -{ - struct lb_serial serial; - serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - serial.baud = get_uart_baudrate(); - serial.regwidth = 1; - serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = 0; - lb_add_serial(&serial, data); - - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); -} -#endif diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index f9606486c2..d46a422e4a 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -7,12 +7,8 @@ romstage-y += ../car/romstage.c postcar-y += tsc_freq.c ramstage-y += acpi.c -ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c -romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c - smm-y += finalize.c smm-y += tsc_freq.c diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index cd8d5cb52b..cfd9d45690 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -118,15 +118,9 @@ /* Data is passed through bits 31:0 of the data register. */ #define BIOS_MAILBOX_DATA 0x5da0 -/* Region of SMM space is reserved for multipurpose use. It falls below - * the IED region and above the SMM handler. */ -#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE -#define RESERVED_SMM_OFFSET \ - (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE) - /* Sanity check config options. */ -#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)) -# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)" +#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)) +# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)" #endif #if (CONFIG_SMM_TSEG_SIZE < 0x800000) # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 3948cfe519..3a4a0a7830 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -250,7 +250,7 @@ static void fill_in_relocation_params(struct device *dev, params->ied_size = tseg_size - params->smram_size; /* Adjust available SMM handler memory size. */ - params->smram_size -= RESERVED_SMM_SIZE; + params->smram_size -= CONFIG_SMM_RESERVED_SIZE; /* SMRR has 32-bits of valid address aligned to 4KiB. */ params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 089b3fead0..a3a58b65e6 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -21,7 +21,6 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_COMMON select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 9a11b06e4d..1f6d1a22b9 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -19,10 +19,6 @@ ramstage-y += acpi.c smm-y += finalize.c -romstage-y += stage_cache.c -ramstage-y += stage_cache.c -postcar-y += stage_cache.c - cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-25-*) cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index eab2dd5c50..2f3584a67e 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -80,16 +80,9 @@ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); #endif -/* - * Region of SMM space is reserved for multipurpose use. It falls below - * the IED region and above the SMM handler. - */ -#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE -#define RESERVED_SMM_OFFSET (CONFIG_SMM_TSEG_SIZE - RESERVED_SMM_SIZE) - /* Sanity check config options. */ -#if (CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE) -# error "CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE" +#if (CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE) +# error "CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE" #endif #if (CONFIG_SMM_TSEG_SIZE < 0x800000) # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" diff --git a/src/cpu/intel/model_2065x/stage_cache.c b/src/cpu/intel/model_2065x/stage_cache.c deleted file mode 100644 index ab8ac979c1..0000000000 --- a/src/cpu/intel/model_2065x/stage_cache.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include "model_2065x.h" - -void stage_cache_external_region(void **base, size_t *size) -{ - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. - */ - *size = RESERVED_SMM_SIZE; - *base = (void *)((uintptr_t)northbridge_get_tseg_base() - + RESERVED_SMM_OFFSET); -} diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 2af63d6079..ced3340903 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -19,7 +19,6 @@ config CPU_SPECIFIC_OPTIONS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select CPU_INTEL_COMMON - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select PARALLEL_MP select NO_FIXED_XIP_ROM_SIZE diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index f5de8c38fa..e723d74d78 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -24,10 +24,6 @@ smm-y += tsc_freq.c smm-y += finalize.c -romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c - cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*) cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3a-*) diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index c0d2434fe6..2dc929345d 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -81,17 +81,9 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 -/* - * Region of SMM space is reserved for multipurpose use. It falls below - * the IED region and above the SMM handler. - */ -#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE -#define RESERVED_SMM_OFFSET \ - (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE) - /* Sanity check config options. */ -#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)) -# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)" +#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)) +# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)" #endif #if (CONFIG_SMM_TSEG_SIZE < 0x800000) # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 986929c9cb..d8021e6ac2 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -121,7 +121,7 @@ static void fill_in_relocation_params(struct smm_relocation_params *params) } /* Adjust available SMM handler memory size. */ - if (CONFIG(CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) { + if (CONFIG(TSEG_STAGE_CACHE)) { ASSERT(params->smram_size > CONFIG_SMM_RESERVED_SIZE); params->smram_size -= CONFIG_SMM_RESERVED_SIZE; } diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c index 12cbfc0b81..ae97f9a8cf 100644 --- a/src/cpu/intel/turbo/turbo.c +++ b/src/cpu/intel/turbo/turbo.c @@ -50,21 +50,15 @@ static const char *const turbo_state_desc[] = { }; /* - * Determine the current state of Turbo and cache it for later. - * Turbo is a package level config so it does not need to be - * enabled on every core. + * Try to update the global Turbo state. */ -int get_turbo_state(void) +static int update_turbo_state(void) { struct cpuid_result cpuid_regs; int turbo_en, turbo_cap; msr_t msr; int turbo_state = get_global_turbo_state(); - /* Return cached state if available */ - if (turbo_state != TURBO_UNKNOWN) - return turbo_state; - cpuid_regs = cpuid(CPUID_LEAF_PM); turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE); @@ -84,6 +78,22 @@ int get_turbo_state(void) set_global_turbo_state(turbo_state); printk(BIOS_INFO, "Turbo is %s\n", turbo_state_desc[turbo_state]); + + return turbo_state; +} + +/* + * Determine the current state of Turbo and cache it for later. Turbo is package + * level config so it does not need to be enabled on every core. + */ +int get_turbo_state(void) +{ + int turbo_state = get_global_turbo_state(); + + /* Return cached state if available */ + if (turbo_state == TURBO_UNKNOWN) + turbo_state = update_turbo_state(); + return turbo_state; } @@ -102,8 +112,7 @@ void enable_turbo(void) wrmsr(IA32_MISC_ENABLE, msr); /* Update cached turbo state */ - set_global_turbo_state(TURBO_ENABLED); - printk(BIOS_INFO, "Turbo has been enabled\n"); + update_turbo_state(); } } @@ -114,12 +123,14 @@ void disable_turbo(void) { msr_t msr; - /* Set Turbo Disable bit in Misc Enables */ - msr = rdmsr(IA32_MISC_ENABLE); - msr.hi |= H_MISC_DISABLE_TURBO; - wrmsr(IA32_MISC_ENABLE, msr); + /* Only possible if turbo is available and visible */ + if (get_turbo_state() == TURBO_ENABLED) { + /* Set Turbo Disable bit in Misc Enables */ + msr = rdmsr(IA32_MISC_ENABLE); + msr.hi |= H_MISC_DISABLE_TURBO; + wrmsr(IA32_MISC_ENABLE, msr); - /* Update cached turbo state */ - set_global_turbo_state(TURBO_UNAVAILABLE); - printk(BIOS_INFO, "Turbo has been disabled\n"); + /* Update cached turbo state */ + update_turbo_state(); + } } diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index caee5dbd10..a8cf54d89e 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -155,6 +155,14 @@ config X86_AMD_FIXED_MTRRS This option informs the MTRR code to use the RdMem and WrMem fields in the fixed MTRR MSRs. +config X86_AMD_INIT_SIPI + bool + default n + help + This option limits the number of SIPI signals sent during during the + common AP setup. Intel documentation specifies an INIT SIPI SIPI + sequence, however this doesn't work on some AMD platforms. + config MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING def_bool n help diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 9528149627..3658a5b698 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -482,6 +482,9 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps) /* Wait for CPUs to check in up to 200 us. */ wait_for_aps(num_aps, ap_count, 200 /* us */, 15 /* us */); + if (CONFIG(X86_AMD_INIT_SIPI)) + return 0; + /* Send 2nd SIPI */ if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); @@ -910,7 +913,7 @@ static int run_ap_work(struct mp_callback *val, long expire_us) return 0; } while (expire_us <= 0 || !stopwatch_expired(&sw)); - printk(BIOS_ERR, "AP call expired. %d/%d CPUs accepted.\n", + printk(BIOS_CRIT, "CIRTICAL ERROR: AP call expired. %d/%d CPUs accepted.\n", cpus_accepted, global_num_aps); return -1; } diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 02ad85f321..5d7ff2cf45 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -51,6 +52,6 @@ void set_var_mtrr( basem.hi = 0; wrmsr(MTRR_PHYS_BASE(reg), basem); maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; + maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1; wrmsr(MTRR_PHYS_MASK(reg), maskm); } diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 5c7aab3ffc..fe149f140f 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -42,6 +42,10 @@ endif ifeq ($(CONFIG_SMM_TSEG),y) +ramstage-y += stage_cache.c +romstage-y += stage_cache.c +postcar-y += stage_cache.c + smmstub-y += smm_stub.S smm-y += smm_module_handler.c diff --git a/src/drivers/intel/fsp1_1/stage_cache.c b/src/cpu/x86/smm/stage_cache.c similarity index 69% rename from src/drivers/intel/fsp1_1/stage_cache.c rename to src/cpu/x86/smm/stage_cache.c index 2d594e6048..0a816ba732 100644 --- a/src/drivers/intel/fsp1_1/stage_cache.c +++ b/src/cpu/x86/smm/stage_cache.c @@ -1,8 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. + * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,12 +14,18 @@ */ #include -#include +#include #include +#include -void stage_cache_external_region(void **base, size_t *size) +int __weak smm_subregion(int sub, uintptr_t *base, size_t *size) { - if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { + return -1; +} + +void __weak stage_cache_external_region(void **base, size_t *size) +{ + if (smm_subregion(SMM_SUBREGION_CACHE, (uintptr_t *)base, size)) { printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); *base = NULL; *size = 0; diff --git a/src/device/Kconfig b/src/device/Kconfig index 0539062272..e605bc2097 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -255,6 +255,7 @@ menu "Display" config FRAMEBUFFER_SET_VESA_MODE prompt "Set framebuffer graphics resolution" bool + default y if CHROMEOS depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE select HAVE_VBE_LINEAR_FRAMEBUFFER help @@ -407,6 +408,8 @@ endif # FRAMEBUFFER_SET_VESA_MODE choice prompt "Framebuffer mode" + default VBE_LINEAR_FRAMEBUFFER if HAVE_VBE_LINEAR_FRAMEBUFFER && CHROMEOS + default GENERIC_LINEAR_FRAMEBUFFER if HAVE_LINEAR_FRAMEBUFFER && CHROMEOS default VGA_TEXT_FRAMEBUFFER config VGA_TEXT_FRAMEBUFFER diff --git a/src/device/device_const.c b/src/device/device_const.c index c1b0b063ff..c472aeaa79 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -234,6 +234,28 @@ DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn) return pcidev_path_on_root(PCI_DEVFN(dev, fn)); } +DEVTREE_CONST struct device *pcidev_path_on_root_debug(pci_devfn_t devfn, const char *func) +{ + DEVTREE_CONST struct device *dev = pcidev_path_on_root(devfn); + if (dev) + return dev; + + devtree_bug(func, devfn); + + /* FIXME: This can return wrong device. */ + return dev_find_slot(0, devfn); +} + +void devtree_bug(const char *func, pci_devfn_t devfn) +{ + printk(BIOS_ERR, "BUG: %s requests hidden 00:%02x.%u\n", func, devfn >> 3, devfn & 7); +} + +void __noreturn devtree_die(void) +{ + die("DEVTREE: dev or chip_info is NULL\n"); +} + /** * Given an SMBus bus and a device number, find the device structure. * diff --git a/src/device/device_util.c b/src/device/device_util.c index 7ded1df435..38303126bc 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -229,7 +229,7 @@ const char *dev_path(const struct device *dev) dev->path.usb.port_type, dev->path.usb.port_id); break; case DEVICE_PATH_MMIO: - snprintf(buffer, sizeof(buffer), "MMIO: %08x", + snprintf(buffer, sizeof(buffer), "MMIO: %08lx", dev->path.mmio.addr); break; default: @@ -331,7 +331,7 @@ void compact_resources(struct device *dev) * @param index The index of the resource on the device. * @return The resource, if it already exists. */ -struct resource *probe_resource(struct device *dev, unsigned index) +struct resource *probe_resource(const struct device *dev, unsigned index) { struct resource *res; @@ -401,7 +401,7 @@ struct resource *new_resource(struct device *dev, unsigned index) * @param index The index of the resource on the device. * return TODO. */ -struct resource *find_resource(struct device *dev, unsigned index) +struct resource *find_resource(const struct device *dev, unsigned index) { struct resource *resource; diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index a7631a1a84..1a80a000e2 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -18,14 +18,12 @@ #include #include #include -#include #include #include #include #include #include #include -#include #include #include #include @@ -36,6 +34,16 @@ #include "x86.h" +typedef struct { + char signature[4]; + u16 version; + u8 *oem_string_ptr; + u32 capabilities; + u32 video_mode_ptr; + u16 total_memory; + char reserved[236]; +} __packed vbe_info_block; + /* The following symbols cannot be used directly. They need to be fixed up * to point to the correct address location after the code has been copied * to REALMODE_BASE. Absolute symbols are not used because those symbols are @@ -50,11 +58,11 @@ extern unsigned char __realmode_buffer; /* to have a common register file for interrupt handlers */ X86EMU_sysEnv _X86EMU_env; -void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx, +unsigned int (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx, u32 esi, u32 edi) asmlinkage; -void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, - u32 esi, u32 edi) asmlinkage; +unsigned int (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, + u32 edx, u32 esi, u32 edi) asmlinkage; static void setup_realmode_code(void) { @@ -213,7 +221,7 @@ static void setup_realmode_idt(void) } #if CONFIG(FRAMEBUFFER_SET_VESA_MODE) -vbe_mode_info_t mode_info; +static vbe_mode_info_t mode_info; static int mode_info_valid; static int vbe_mode_info_valid(void) @@ -221,6 +229,92 @@ static int vbe_mode_info_valid(void) return mode_info_valid; } +const vbe_mode_info_t *vbe_mode_info(void) +{ + if (!mode_info_valid || !mode_info.vesa.phys_base_ptr) + return NULL; + return &mode_info; +} + +static int vbe_check_for_failure(int ah); + +static void vbe_get_ctrl_info(vbe_info_block *info) +{ + char *buffer = PTR_TO_REAL_MODE(__realmode_buffer); + u16 buffer_seg = (((unsigned long)buffer) >> 4) & 0xff00; + u16 buffer_adr = ((unsigned long)buffer) & 0xffff; + X86_EAX = realmode_interrupt(0x10, VESA_GET_INFO, 0x0000, 0x0000, + 0x0000, buffer_seg, buffer_adr); + /* If the VBE function completed successfully, 0x0 is returned in AH */ + if (X86_AH) + die("\nError: In %s function\n", __func__); + memcpy(info, buffer, sizeof(vbe_info_block)); +} + +static void vbe_oprom_list_supported_mode(uint16_t *video_mode_ptr) +{ + uint16_t mode; + printk(BIOS_DEBUG, "Supported Video Mode list for OpRom:\n"); + do { + mode = *video_mode_ptr++; + if (mode != 0xffff) + printk(BIOS_DEBUG, "%x\n", mode); + } while (mode != 0xffff); +} + +static void vbe_oprom_supported_mode_list(void) +{ + uint16_t segment, offset; + vbe_info_block info; + + vbe_get_ctrl_info(&info); + + offset = info.video_mode_ptr; + segment = info.video_mode_ptr >> 16; + + vbe_oprom_list_supported_mode((uint16_t *)((segment << 4) + offset)); +} +/* + * EAX register is used to indicate the completion status upon return from + * VBE function in real mode. + * + * If the VBE function completed successfully then 0x0 is returned in the AH + * register. Otherwise the AH register is set with the nature of the failure: + * + * AH == 0x00: Function call successful + * AH == 0x01: Function call failed + * AH == 0x02: Function is not supported in the current HW configuration + * AH == 0x03: Function call invalid in current video mode + * + * Return 0 on success else -1 for failure + */ +static int vbe_check_for_failure(int ah) +{ + int status; + + switch (ah) { + case 0x0: + status = 0; + break; + case 1: + printk(BIOS_DEBUG, "VBE: Function call failed!\n"); + status = -1; + break; + case 2: + printk(BIOS_DEBUG, "VBE: Function is not supported!\n"); + status = -1; + break; + case 3: + default: + printk(BIOS_DEBUG, "VBE: Unsupported video mode %x!\n", + CONFIG_FRAMEBUFFER_VESA_MODE); + vbe_oprom_supported_mode_list(); + status = -1; + break; + } + + return status; +} static u8 vbe_get_mode_info(vbe_mode_info_t * mi) { printk(BIOS_DEBUG, "VBE: Getting information about VESA mode %04x\n", @@ -228,8 +322,10 @@ static u8 vbe_get_mode_info(vbe_mode_info_t * mi) char *buffer = PTR_TO_REAL_MODE(__realmode_buffer); u16 buffer_seg = (((unsigned long)buffer) >> 4) & 0xff00; u16 buffer_adr = ((unsigned long)buffer) & 0xffff; - realmode_interrupt(0x10, VESA_GET_MODE_INFO, 0x0000, + X86_EAX = realmode_interrupt(0x10, VESA_GET_MODE_INFO, 0x0000, mi->video_mode, 0x0000, buffer_seg, buffer_adr); + if (vbe_check_for_failure(X86_AH)) + die("\nError: In %s function\n", __func__); memcpy(mi->mode_info_block, buffer, sizeof(mi->mode_info_block)); mode_info_valid = 1; return 0; @@ -242,8 +338,10 @@ static u8 vbe_set_mode(vbe_mode_info_t * mi) mi->video_mode |= (1 << 14); // request clearing of framebuffer mi->video_mode &= ~(1 << 15); - realmode_interrupt(0x10, VESA_SET_MODE, mi->video_mode, + X86_EAX = realmode_interrupt(0x10, VESA_SET_MODE, mi->video_mode, 0x0000, 0x0000, 0x0000, 0x0000); + if (vbe_check_for_failure(X86_AH)) + die("\nError: In %s function\n", __func__); return 0; } @@ -260,6 +358,7 @@ void vbe_set_graphics(void) le16_to_cpu(mode_info.vesa.x_resolution), le16_to_cpu(mode_info.vesa.y_resolution), mode_info.vesa.bits_per_pixel); + printk(BIOS_DEBUG, "VBE: framebuffer: %p\n", framebuffer); if (!framebuffer) { printk(BIOS_DEBUG, "VBE: Mode does not support linear " @@ -268,26 +367,15 @@ void vbe_set_graphics(void) } vbe_set_mode(&mode_info); -#if CONFIG(BOOTSPLASH) - struct jpeg_decdata *decdata; - unsigned char *jpeg = cbfs_boot_map_with_leak("bootsplash.jpg", - CBFS_TYPE_BOOTSPLASH, - NULL); - if (!jpeg) { - printk(BIOS_DEBUG, "VBE: No bootsplash found.\n"); - return; - } - decdata = malloc(sizeof(*decdata)); - int ret = 0; - ret = jpeg_decode(jpeg, framebuffer, 1024, 768, 16, decdata); -#endif } void vbe_textmode_console(void) { delay(2); - realmode_interrupt(0x10, 0x0003, 0x0000, 0x0000, + X86_EAX = realmode_interrupt(0x10, 0x0003, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000); + if (vbe_check_for_failure(X86_AH)) + die("\nError: In %s function\n", __func__); } int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) diff --git a/src/device/oprom/realmode/x86.h b/src/device/oprom/realmode/x86.h index b8cc02a51e..052c9c0dbf 100644 --- a/src/device/oprom/realmode/x86.h +++ b/src/device/oprom/realmode/x86.h @@ -33,11 +33,11 @@ extern unsigned int __idt_handler_size; extern unsigned char __realmode_code; extern unsigned int __realmode_code_size; -extern void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx, - u32 esi, u32 edi) asmlinkage; +extern unsigned int (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, + u32 edx, u32 esi, u32 edi) asmlinkage; -extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, - u32 esi, u32 edi) asmlinkage; +extern unsigned int (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, + u32 edx, u32 esi, u32 edi) asmlinkage; #define FAKE_MEMORY_SIZE (1024*1024) // only 1MB #define INITIAL_EBDA_SEGMENT 0xF600 diff --git a/src/device/oprom/realmode/x86_asm.S b/src/device/oprom/realmode/x86_asm.S index 87348cdc22..ec82e53ec5 100644 --- a/src/device/oprom/realmode/x86_asm.S +++ b/src/device/oprom/realmode/x86_asm.S @@ -43,6 +43,10 @@ __idt_handler_size: .globl __realmode_code __realmode_code: +/* Realmode function return. */ +__realmode_ret = RELOCATED(.) + .long 0 + /* Realmode IDT pointer structure. */ __realmode_idt = RELOCATED(.) .word 1023 /* 16 bit limit */ @@ -167,6 +171,13 @@ __lcall_instr = RELOCATED(.) .word 0x0000, 0x0000 /* ************************************ */ + /* + * Here is end of real mode call and time to go back to protected mode. + * Before that its better to store current eax into some memory address + * so that context persist in protected mode too. + */ + mov %eax, __realmode_ret + /* If we got here, we are just about done. * Need to get back to protected mode. */ @@ -196,7 +207,8 @@ __lcall_instr = RELOCATED(.) popa /* and exit */ - // TODO return AX from OPROM call + /* return AX from OPROM call */ + mov __realmode_ret, %eax ret .globl __realmode_interrupt @@ -291,6 +303,13 @@ __realmode_interrupt: __intXX_instr = RELOCATED(.) .byte 0xcd, 0x00 /* This becomes intXX */ + /* + * Here is end of real mode call and time to go back to protected mode. + * Before that its better to store current eax into some memory address + * so that context persist in protected mode too. + */ + mov %eax, __realmode_ret + /* Ok, the job is done, now go back to protected mode coreboot */ movl %cr0, %eax orl $PE, %eax @@ -314,6 +333,8 @@ __intXX_instr = RELOCATED(.) movl __stack, %esp popf popa + /* return AX from OPROM call */ + mov __realmode_ret, %eax ret /* This is the 16-bit interrupt entry point called by the IDT stub code. diff --git a/src/device/oprom/yabel/io.c b/src/device/oprom/yabel/io.c index e8c41ce24a..051a601569 100644 --- a/src/device/oprom/yabel/io.c +++ b/src/device/oprom/yabel/io.c @@ -184,8 +184,7 @@ my_inb(X86EMU_pioAddr addr) X86EMU_trace_on(); } M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; - //HALT_SYS(); - // no break, intentional fall-through to default!! + // fall-through default: DEBUG_PRINTF_IO ("%s(%04x) reading from bios_device.io_buffer\n", diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index 682bf00ba5..9a7fa045c7 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -34,9 +34,6 @@ #include #include -#if CONFIG(FRAMEBUFFER_SET_VESA_MODE) -#include -#endif #include @@ -52,13 +49,22 @@ #include "interrupt.h" #include "device.h" -#include - #include -#include "../../src/lib/jpeg.h" #include +// these structs only store a subset of the VBE defined fields +// only those needed. +typedef struct { + char signature[4]; + u16 version; + u8 *oem_string_ptr; + u32 capabilities; + u16 video_mode_list[256]; // lets hope we never have more than + // 256 video modes... + u16 total_memory; +} vbe_info_t; + // pointer to VBEInfoBuffer, set by vbe_prepare u8 *vbe_info_buffer = 0; @@ -705,7 +711,14 @@ vbe_get_info(void) } #endif -vbe_mode_info_t mode_info; +static vbe_mode_info_t mode_info; + +const vbe_mode_info_t *vbe_mode_info(void) +{ + if (!mode_info_valid || !mode_info.vesa.phys_base_ptr) + return NULL; + return &mode_info; +} void vbe_set_graphics(void) { @@ -733,34 +746,6 @@ void vbe_set_graphics(void) mode_info.video_mode = (1 << 14) | CONFIG_FRAMEBUFFER_VESA_MODE; vbe_get_mode_info(&mode_info); vbe_set_mode(&mode_info); - -#if CONFIG(BOOTSPLASH) - unsigned char *framebuffer = - (unsigned char *) le32_to_cpu(mode_info.vesa.phys_base_ptr); - DEBUG_PRINTF_VBE("FRAMEBUFFER: 0x%p\n", framebuffer); - - struct jpeg_decdata *decdata; - - /* Switching Intel IGD to 1MB video memory will break this. Who - * cares. */ - // int imagesize = 1024*768*2; - - unsigned char *jpeg = cbfs_boot_map_with_leak("bootsplash.jpg", - CBFS_TYPE_BOOTSPLASH, - NULL); - if (!jpeg) { - DEBUG_PRINTF_VBE("Could not find bootsplash.jpg\n"); - return; - } - DEBUG_PRINTF_VBE("Splash at %p ...\n", jpeg); - dump(jpeg, 64); - - decdata = malloc(sizeof(*decdata)); - int ret = 0; - DEBUG_PRINTF_VBE("Decompressing boot splash screen...\n"); - ret = jpeg_decode(jpeg, framebuffer, 1024, 768, 16, decdata); - DEBUG_PRINTF_VBE("returns %x\n", ret); -#endif } int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 9c47085152..5765529f86 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include @@ -49,6 +50,8 @@ #include #include #include +#include + u8 pci_moving_config8(struct device *dev, unsigned int reg) { @@ -627,11 +630,6 @@ void pci_dev_enable_resources(struct device *dev) pci_write_config16(dev, PCI_COMMAND, command); } -void __noreturn pcidev_die(void) -{ - die("PCI: dev is NULL!\n"); -} - void pci_bus_enable_resources(struct device *dev) { u16 ctrl; @@ -764,9 +762,13 @@ void pci_dev_init(struct device *dev) return; run_bios(dev, (unsigned long)ram); + gfx_set_init_done(1); printk(BIOS_DEBUG, "VGA Option ROM was run\n"); timestamp_add_now(TS_OPROM_END); + + if (CONFIG(BOOTSPLASH)) + set_vesa_bootsplash(); } /** Default device operation for PCI devices */ diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index 96133155be..6f42978e82 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -14,6 +14,7 @@ #define __SIMPLE_DEVICE__ #include +#include #include #include #include @@ -85,3 +86,8 @@ u16 pci_s_find_capability(pci_devfn_t dev, u16 cap) { return pci_s_find_next_capability(dev, cap, 0); } + +void __noreturn pcidev_die(void) +{ + die("PCI: dev is NULL!\n"); +} diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 34a9a81a52..2b2d46d57b 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -192,7 +192,7 @@ static struct rom_header *check_initialized(struct device *dev) return NULL; rom_data = (struct pci_data *)((u8 *)run_rom - + read_le32(&run_rom->data)); + + read_le16(&run_rom->data)); if (read_le32(&rom_data->signature) == PCI_DATA_HDR && read_le16(&rom_data->device) == dev->device diff --git a/src/drivers/crb/Kconfig b/src/drivers/crb/Kconfig new file mode 100644 index 0000000000..bfd8be06d6 --- /dev/null +++ b/src/drivers/crb/Kconfig @@ -0,0 +1,17 @@ +config CRB_TPM + bool + help + CRB TPM driver is enabled! + +config CRB_TPM_BASE_ADDRESS + hex + default 0xfed40000 + help + Base Address of the CRB TPM Command Structure + +config MAINBOARD_HAS_CRB_TPM + bool + default n + select CRB_TPM + help + Mainboard has Command Response Buffer support diff --git a/src/drivers/crb/Makefile.inc b/src/drivers/crb/Makefile.inc new file mode 100644 index 0000000000..3f12b36923 --- /dev/null +++ b/src/drivers/crb/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-$(CONFIG_CRB_TPM) += tis.c tpm.c +verstage-$(CONFIG_CRB_TPM) += tis.c tpm.c +romstage-$(CONFIG_CRB_TPM) += tis.c tpm.c +ramstage-$(CONFIG_CRB_TPM) += tis.c tpm.c +postcar-$(CONFIG_CRB_TPM) += tis.c tpm.c diff --git a/src/soc/amd/picasso/cache_as_ram.S b/src/drivers/crb/chip.h similarity index 69% rename from src/soc/amd/picasso/cache_as_ram.S rename to src/drivers/crb/chip.h index 28690628d6..8e74a68f97 100644 --- a/src/soc/amd/picasso/cache_as_ram.S +++ b/src/drivers/crb/chip.h @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright 2014 Google Inc. All Rights Reserved. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -11,10 +13,10 @@ * GNU General Public License for more details. */ -/* - * TODO: This is a dummy file for making bootblock build and link. At some - * point, this should be removed from picasso since bootblock is - * ignored. - */ -.global bootblock_pre_c_entry -bootblock_pre_c_entry: +#ifndef DRIVERS_CRB_CHIP_H +#define DRIVERS_CRB_CHIP_H + +typedef struct drivers_crb_config { +} tpm_config_t; + +#endif /* DRIVERS_CRB_CHIP_H */ diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c new file mode 100644 index 0000000000..94bfb9ef15 --- /dev/null +++ b/src/drivers/crb/tis.c @@ -0,0 +1,159 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include "tpm.h" +#include "chip.h" + +static unsigned tpm_is_open CAR_GLOBAL; + +static const struct { + uint16_t vid; + uint16_t did; + const char *device_name; +} dev_map[] = { + {0x1ae0, 0x0028, "CR50"}, + {0xa13a, 0x8086, "Intel iTPM"} +}; + +static const char *tis_get_dev_name(struct tpm2_info *info) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(dev_map); i++) + if ((dev_map[i].vid == info->vendor_id) && (dev_map[i].did == info->device_id)) + return dev_map[i].device_name; + return "Unknown"; +} + + +int tis_open(void) +{ + if (car_get_var(tpm_is_open)) { + printk(BIOS_ERR, "%s called twice.\n", __func__); + return -1; + } + + if (CONFIG(HAVE_INTEL_PTT)) { + if (!ptt_active()) { + printk(BIOS_ERR, "%s: Intel PTT is not active.\n", __func__); + return -1; + } + printk(BIOS_DEBUG, "%s: Intel PTT is active.\n", __func__); + } + + return 0; +} + +int tis_close(void) +{ + if (car_get_var(tpm_is_open)) { + + /* + * Do we need to do something here, like waiting for a + * transaction to stop? + */ + car_set_var(tpm_is_open, 0); + } + + return 0; +} + +int tis_init(void) +{ + struct tpm2_info info; + + // Wake TPM up (if necessary) + if (tpm2_init() != 0) + return -1; + + tpm2_get_info(&info); + + printk(BIOS_INFO, "Initialized TPM device %s revision %d\n", tis_get_dev_name(&info), + info.revision); + + return 0; +} + + +int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, uint8_t *recvbuf, size_t *rbuf_len) +{ + int len = tpm2_process_command(sendbuf, sbuf_size, recvbuf, *rbuf_len); + + if (len == 0) + return -1; + + *rbuf_len = len; + + return 0; +} + +#ifdef __RAMSTAGE__ + +static void crb_tpm_fill_ssdt(struct device *dev) +{ + const char *path = acpi_device_path(dev); + if (!path) { + path = "\\_SB_.TPM"; + printk(BIOS_DEBUG, "Using default TPM2 ACPI path: '%s'\n", path); + } + + /* Device */ + acpigen_write_device(path); + + acpigen_write_name_string("_HID", "MSFT0101"); + acpigen_write_name_string("_CID", "MSFT0101"); + + acpigen_write_name_integer("_UID", 1); + + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpigen_write_mem32fixed(1, TPM_CRB_BASE_ADDRESS, 0x5000); + + acpigen_write_resourcetemplate_footer(); + + acpigen_pop_len(); /* Device */ +} + +static const char *crb_tpm_acpi_name(const struct device *dev) +{ + return "TPM"; +} + +static struct device_operations crb_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = crb_tpm_acpi_name, + .acpi_fill_ssdt_generator = crb_tpm_fill_ssdt, +#endif + +}; + +static void enable_dev(struct device *dev) +{ + dev->ops = &crb_ops; +} + +struct chip_operations drivers_crb_ops = {CHIP_NAME("CRB TPM").enable_dev = enable_dev}; + +#endif /* __RAMSTAGE__ */ diff --git a/src/drivers/crb/tpm.c b/src/drivers/crb/tpm.c new file mode 100644 index 0000000000..0393417e74 --- /dev/null +++ b/src/drivers/crb/tpm.c @@ -0,0 +1,280 @@ +/*. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * This is a driver for a CRB Interface. + * + * The general flow looks like this: + * + * TPM starts in IDLE Mode + * + * IDLE --> READY --> Command Receiption + * ^ | + * | v + -- Cmd Complete <-- Command Execution + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tpm.h" + +static struct control_area { + uint32_t request; + uint32_t status; + uint32_t cancel; + uint32_t start; + uint64_t interrupt_control; + uint32_t command_size; + void *command_bfr; + uint32_t response_size; + void *response_bfr; +} control_area; + +static uint8_t cur_loc = 0; + +/* Read Control Area Structure back */ +static void crb_readControlArea(void) +{ + control_area.request = read32(CRB_REG(cur_loc, CRB_REG_REQUEST)); + control_area.status = read32(CRB_REG(cur_loc, CRB_REG_STATUS)); + control_area.cancel = read32(CRB_REG(cur_loc, CRB_REG_CANCEL)); + control_area.interrupt_control = read64(CRB_REG(cur_loc, CRB_REG_INT_CTRL)); + control_area.command_size = read32(CRB_REG(cur_loc, CRB_REG_CMD_SIZE)); + control_area.command_bfr = (void *)(uint32_t)read64(CRB_REG(cur_loc, CRB_REG_CMD_ADDR)); + control_area.response_size = read32(CRB_REG(cur_loc, CRB_REG_RESP_SIZE)); + control_area.response_bfr = + (void *)(uint32_t)read64(CRB_REG(cur_loc, CRB_REG_RESP_ADDR)); +} + +/* Wait for Reg to be expected Value */ +static int crb_wait_for_reg32(const void *addr, uint32_t timeoutMs, uint32_t mask, + uint32_t expectedValue) +{ + uint32_t regValue; + struct stopwatch sw; + + // Set up a timer which breaks the loop after timeout + stopwatch_init_msecs_expire(&sw, timeoutMs); + + while (1) { + // Now check if the TPM is in IDLE mode + regValue = read32(addr); + + if ((regValue & mask) == expectedValue) + return 0; + + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, + "CRB_WAIT: Error - Returning Zero with RegValue: %08x, Mask: %08x, Expected: %08x\n", + regValue, mask, expectedValue); + return -1; + } + } +} + +/* CRB PROBE + * + * Checks if the CRB Interface is ready + */ +static int crb_probe(void) +{ + uint64_t tpmStatus = read64(CRB_REG(cur_loc, CRB_REG_INTF_ID)); + printk(BIOS_SPEW, "Interface ID Reg. %llx\n", tpmStatus); + + if ((tpmStatus & CRB_INTF_REG_CAP_CRB) == 0) { + printk(BIOS_DEBUG, "TPM: CRB Interface is not supported.\n"); + return -1; + } + + if ((tpmStatus & (0xf)) != 1) { + printk(BIOS_DEBUG, + "TPM: CRB Interface is not active. System needs reboot in order to active TPM.\n"); + write32(CRB_REG(cur_loc, CRB_REG_INTF_ID), CRB_INTF_REG_INTF_SEL); + return -1; + } + + write32(CRB_REG(cur_loc, CRB_REG_INTF_ID), CRB_INTF_REG_INTF_SEL); + write32(CRB_REG(cur_loc, CRB_REG_INTF_ID), CRB_INTF_REG_INTF_LOCK); + + return 0; +} + +/* + * Get active Locality + * + * Get the active locality + */ +static uint8_t crb_activate_locality(void) +{ + + uint8_t locality = (read8(CRB_REG(0, CRB_REG_LOC_STATE)) >> 2) & 0x07; + printk(BIOS_SPEW, "Active locality: %i\n", locality); + + int rc = crb_wait_for_reg32(CRB_REG(locality, CRB_REG_LOC_STATE), 750, + LOC_STATE_LOC_ASSIGN, LOC_STATE_LOC_ASSIGN); + if (!rc && (locality == 0)) + return locality; + + if (rc) + write8(CRB_REG(locality, CRB_REG_LOC_CTRL), LOC_CTRL_REQ_ACCESS); + + + rc = crb_wait_for_reg32(CRB_REG(locality, CRB_REG_LOC_STATE), 750, LOC_STATE_LOC_ASSIGN, + LOC_STATE_LOC_ASSIGN); + if (rc) { + printk(BIOS_ERR, "TPM: Error - No Locality has been assigned TPM-wise.\n"); + return 0; + } + + rc = crb_wait_for_reg32(CRB_REG(locality, CRB_REG_LOC_STATE), 1500, + LOC_STATE_REG_VALID_STS, LOC_STATE_REG_VALID_STS); + if (rc) { + printk(BIOS_ERR, "TPM: Error - LOC_STATE Register %u contains errors.\n", + locality); + return 0; + } + + + return locality; +} + +/* Switch Device into a Ready State */ +static int crb_switch_to_ready(void) +{ + /* Transition into ready state */ + write8(CRB_REG(cur_loc, CRB_REG_REQUEST), 0x1); + int rc = crb_wait_for_reg32(CRB_REG(cur_loc, CRB_REG_REQUEST), 200, + CRB_REG_REQUEST_CMD_RDY, 0x0); + if (rc) { + printk(BIOS_ERR, + "TPM: Error - TPM did not transition into ready state in time.\n"); + return -1; + } + + /* Check TPM_CRB_CTRL_STS[0] to be "0" - no unrecoverable error */ + rc = crb_wait_for_reg32(CRB_REG(cur_loc, CRB_REG_STATUS), 500, CRB_REG_STATUS_ERROR, + 0x0); + if (rc) { + printk(BIOS_ERR, "TPM: Fatal Error - Could not recover.\n"); + return -1; + } + + return 0; +} + +/* + * tpm2_init + * + * Even though the TPM does not need an initialization we check + * if the TPM responds and is in IDLE mode, which should be the + * normal bring up mode. + * + */ +int tpm2_init(void) +{ + + + if (crb_probe()) { + printk(BIOS_ERR, "TPM: Probe failed.\n"); + return -1; + } + + /* Read back control area structure */ + crb_readControlArea(); + + /* Good to go. */ + printk(BIOS_SPEW, "TPM: CRB TPM initialized successfully\n"); + + return 0; +} + +/* + * tpm2_process_command + */ +size_t tpm2_process_command(const void *tpm2_command, size_t command_size, void *tpm2_response, + size_t max_response) +{ + int rc; + + if (command_size > control_area.command_size) { + printk(BIOS_ERR, "TPM: Command size is too big.\n"); + return -1; + } + + if (control_area.response_size < max_response) { + printk(BIOS_ERR, "TPM: Response size could be too big.\n"); + return -1; + } + + cur_loc = crb_activate_locality(); + + // Check if CMD bit is cleared. + rc = crb_wait_for_reg32(CRB_REG(0, CRB_REG_START), 250, CRB_REG_START_START, 0x0); + if (rc) { + printk(BIOS_ERR, "TPM: Error - Cmd Bit not cleared.\n"); + return -1; + } + + if (crb_switch_to_ready()) + return -1; + + // Write to Command Buffer + memcpy(control_area.command_bfr, tpm2_command, command_size); + + // Write Start Bit + write8(CRB_REG(cur_loc, CRB_REG_START), 0x1); + + // Poll for Response + rc = crb_wait_for_reg32(CRB_REG(cur_loc, CRB_REG_START), 3500, CRB_REG_START_START, 0); + if (rc) { + printk(BIOS_DEBUG, "TPM: Command Timed out.\n"); + return -1; + } + + // Check for errors + rc = crb_wait_for_reg32(CRB_REG(cur_loc, CRB_REG_STATUS), 200, CRB_REG_STATUS_ERROR, 0); + if (rc) { + printk(BIOS_DEBUG, "TPM: Command errored.\n"); + return -1; + } + + // Get Response Length + uint32_t length = be32_to_cpu(read32(control_area.response_bfr + 2)); + + /* Response has to have at least 6 bytes */ + if (length < 6) + return 1; + + // Copy Response + memcpy(tpm2_response, control_area.response_bfr, length); + + if (crb_switch_to_ready()) { + printk(BIOS_DEBUG, "TPM: Can not transition into ready state again.\n"); + return -1; + } + + return length; +} + +/* + * tp2_get_info + * + * Returns information about the TPM + * + */ +void tpm2_get_info(struct tpm2_info *tpm2_info) +{ + uint64_t interfaceReg = read64(CRB_REG(cur_loc, CRB_REG_INTF_ID)); + + tpm2_info->vendor_id = (interfaceReg >> 48) & 0xFFFF; + tpm2_info->device_id = (interfaceReg >> 32) & 0xFFFF; + tpm2_info->revision = (interfaceReg >> 24) & 0xFF; +} diff --git a/src/drivers/crb/tpm.h b/src/drivers/crb/tpm.h new file mode 100644 index 0000000000..9bbed198f0 --- /dev/null +++ b/src/drivers/crb/tpm.h @@ -0,0 +1,70 @@ +/* + * Copyright 2016 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * This is a driver for a Command Response Buffer Interface + */ + +/* CRB driver */ +/* address of locality 0 (CRB) */ +#define TPM_CRB_BASE_ADDRESS CONFIG_CRB_TPM_BASE_ADDRESS + +#define CRB_REG(LOCTY, REG) \ + (void *)(CONFIG_CRB_TPM_BASE_ADDRESS + (LOCTY << 12) + REG) + +/* hardware registers */ +#define CRB_REG_LOC_STATE 0x00 +#define CRB_REG_LOC_CTRL 0x08 +#define CRB_REG_LOC_STS 0x0C + +/* LOC_CTRL BIT MASKS */ +#define LOC_CTRL_REQ_ACCESS 0x01 + +/* LOC STATE BIT MASKS */ +#define LOC_STATE_LOC_ASSIGN 0x02 +#define LOC_STATE_REG_VALID_STS 0x80 + +/* LOC STS BIT MASKS */ +#define LOC_STS_GRANTED 0x01 + +#define CRB_REG_INTF_ID 0x30 +#define CRB_REG_REQUEST 0x40 +#define CRB_REG_STATUS 0x44 +#define CRB_REG_CANCEL 0x48 +#define CRB_REG_START 0x4C +#define CRB_REG_INT_CTRL 0x50 +#define CRB_REG_CMD_SIZE 0x58 +#define CRB_REG_CMD_ADDR 0x5C +#define CRB_REG_RESP_SIZE 0x64 +#define CRB_REG_RESP_ADDR 0x68 + +/* CRB INTF BIT MASK */ +#define CRB_INTF_REG_CAP_CRB (1<<14) +#define CRB_INTF_REG_INTF_SEL (1<<17) +#define CRB_INTF_REG_INTF_LOCK (1<<19) + + +/*REQUEST Register related */ +#define CRB_REG_REQUEST_CMD_RDY 0x01 +#define CRB_REG_REQUEST_GO_IDLE 0x02 + +/* STATUS Register related */ +#define CRB_REG_STATUS_ERROR 0x01 +#define CRB_REG_STATUS_IDLE 0x02 + +/* START Register related */ +#define CRB_REG_START_START 0x01 + +/* TPM Info Struct */ +struct tpm2_info { + uint16_t vendor_id; + uint16_t device_id; + uint16_t revision; +}; + + +int tpm2_init(void); +void tpm2_get_info(struct tpm2_info *tpm2_info); +size_t tpm2_process_command(const void *tpm2_command, size_t command_size, + void *tpm2_response, size_t max_response); diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index 93b662a63d..760a735380 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -817,14 +817,9 @@ void dw_i2c_acpi_fill_ssdt(struct device *dev) const struct dw_i2c_bus_config *bcfg; uintptr_t dw_i2c_addr; struct dw_i2c_speed_config sgen; - enum i2c_speed speeds[DW_I2C_SPEED_CONFIG_COUNT] = { - I2C_SPEED_STANDARD, - I2C_SPEED_FAST, - I2C_SPEED_FAST_PLUS, - I2C_SPEED_HIGH, - }; - int i, bus; + int bus; const char *path; + unsigned int speed; if (!dev->enabled) return; @@ -847,20 +842,15 @@ void dw_i2c_acpi_fill_ssdt(struct device *dev) if (!path) return; - acpigen_write_scope(path); + /* Ensure a default speed is available */ + speed = (bcfg->speed == 0) ? I2C_SPEED_FAST : bcfg->speed; /* Report timing values for the OS driver */ - for (i = 0; i < DW_I2C_SPEED_CONFIG_COUNT; i++) { - /* Generate speed config. */ - if (dw_i2c_gen_speed_config(dw_i2c_addr, speeds[i], bcfg, - &sgen) < 0) - continue; - - /* Generate ACPI based on selected speed config */ + if (dw_i2c_gen_speed_config(dw_i2c_addr, speed, bcfg, &sgen) >= 0) { + acpigen_write_scope(path); dw_i2c_acpi_write_speed_config(&sgen); + acpigen_pop_len(); } - - acpigen_pop_len(); } static int dw_i2c_dev_transfer(struct device *dev, diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 10877b9482..1372e98565 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -29,7 +29,6 @@ romstage-y += fsp_util.c romstage-y += hob.c romstage-y += raminit.c romstage-y += romstage.c -romstage-y += stage_cache.c romstage-$(CONFIG_MMA) += mma_core.c ramstage-$(CONFIG_RUN_FSP_GOP) += fsp_gop.c @@ -37,13 +36,11 @@ ramstage-y += fsp_relocate.c ramstage-y += fsp_util.c ramstage-y += hob.c ramstage-y += ramstage.c -ramstage-y += stage_cache.c ramstage-$(CONFIG_INTEL_GMA_ADD_VBT) += vbt.c ramstage-$(CONFIG_MMA) += mma_core.c CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include -postcar-y += stage_cache.c ifneq ($(CONFIG_SKIP_FSP_CAR),y) postcar-y += temp_ram_exit.c postcar-y += exit_car.S diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 19eb041eac..1b6f62c351 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -19,9 +19,9 @@ #include #include #include +#include #include #include -#include #include /* platform_enter_postcar() determines the stack to use after diff --git a/src/drivers/intel/fsp1_1/include/fsp/memmap.h b/src/drivers/intel/fsp1_1/include/fsp/memmap.h deleted file mode 100644 index 965bce646e..0000000000 --- a/src/drivers/intel/fsp1_1/include/fsp/memmap.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015-2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _COMMON_MEMMAP_H_ -#define _COMMON_MEMMAP_H_ - -#include - -/* - * mmap_region_granularity must to return a size which is a positive non-zero - * integer multiple of the SMM size when SMM is in use. When not using SMM, - * this value should be set to 8 MiB. - */ -size_t mmap_region_granularity(void); - -/* Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); - -enum { - /* SMM handler area. */ - SMM_SUBREGION_HANDLER, - /* SMM cache region. */ - SMM_SUBREGION_CACHE, - /* Chipset specific area. */ - SMM_SUBREGION_CHIPSET, - /* Total sub regions supported. */ - SMM_SUBREGION_NUM, -}; - -/* Fills in the start and size for the requested SMM subregion. Returns - * 0 on susccess, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); - -#endif /* _COMMON_MEMMAP_H_ */ diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index e71c9a2ddf..7b893d269e 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include /* hexdump */ @@ -53,7 +53,7 @@ void raminit(struct romstage_params *params) UPD_DATA_REGION *upd_ptr; int fsp_verification_failure = 0; EFI_PEI_HOB_POINTERS hob_ptr; - char *smm_base; + uintptr_t smm_base; size_t smm_size; /* @@ -148,9 +148,9 @@ void raminit(struct romstage_params *params) /* Display SMM area */ if (CONFIG(HAVE_SMI_HANDLER)) { - smm_region((void **)&smm_base, &smm_size); + smm_region(&smm_base, &smm_size); printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size); - printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base); + printk(BIOS_DEBUG, "0x%08x: smm_base\n", (unsigned int)smm_base); } /* Migrate CAR data */ @@ -238,7 +238,7 @@ void raminit(struct romstage_params *params) printk(BIOS_ERR, "ERROR - Reserving FSP memory area!\n"); if (CONFIG(HAVE_SMI_HANDLER) && cbmem_root != NULL) { - size_t delta_bytes = (unsigned int)smm_base + size_t delta_bytes = smm_base - cbmem_root->PhysicalStart - cbmem_root->ResourceLength; printk(BIOS_ERR, @@ -259,7 +259,7 @@ void raminit(struct romstage_params *params) /* Locate the memory configuration data to speed up the next reboot */ mrc_hob = get_next_guid_hob(&mrc_guid, hob_list_ptr); - if ((mrc_hob == NULL) && CONFIG(DISPLAY_HOBS)) + if (mrc_hob == NULL) printk(BIOS_DEBUG, "Memory Configuration Data Hob not present\n"); else if (!vboot_recovery_mode_enabled()) { diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 52a886ce30..4b567da188 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include @@ -33,19 +33,19 @@ __weak void soc_after_silicon_init(void) /* Display SMM memory map */ static void smm_memory_map(void) { - void *base; + uintptr_t base; size_t size; int i; printk(BIOS_SPEW, "SMM Memory Map\n"); smm_region(&base, &size); - printk(BIOS_SPEW, "SMRAM : %p 0x%zx\n", base, size); + printk(BIOS_SPEW, "SMRAM : 0x%zx 0x%zx\n", base, size); for (i = 0; i < SMM_SUBREGION_NUM; i++) { if (smm_subregion(i, &base, &size)) continue; - printk(BIOS_SPEW, " Subregion %d: %p 0x%zx\n", i, base, size); + printk(BIOS_SPEW, " Subregion %d: 0x%zx 0x%zx\n", i, base, size); } } diff --git a/src/drivers/intel/fsp2_0/include/fsp/memmap.h b/src/drivers/intel/fsp2_0/include/fsp/memmap.h deleted file mode 100644 index 965bce646e..0000000000 --- a/src/drivers/intel/fsp2_0/include/fsp/memmap.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015-2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _COMMON_MEMMAP_H_ -#define _COMMON_MEMMAP_H_ - -#include - -/* - * mmap_region_granularity must to return a size which is a positive non-zero - * integer multiple of the SMM size when SMM is in use. When not using SMM, - * this value should be set to 8 MiB. - */ -size_t mmap_region_granularity(void); - -/* Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); - -enum { - /* SMM handler area. */ - SMM_SUBREGION_HANDLER, - /* SMM cache region. */ - SMM_SUBREGION_CACHE, - /* Chipset specific area. */ - SMM_SUBREGION_CHIPSET, - /* Total sub regions supported. */ - SMM_SUBREGION_NUM, -}; - -/* Fills in the start and size for the requested SMM subregion. Returns - * 0 on susccess, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); - -#endif /* _COMMON_MEMMAP_H_ */ diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 59a9e8aa5b..75d268723b 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -54,6 +54,9 @@ config INTEL_GMA_SWSMISCI Select this option for Atom-based platforms which use the SWSMISCI register (0xe0) rather than the SWSCI register (0xe8). +config INTEL_GMA_LIBGFXINIT_EDID + bool + config GFX_GMA_ANALOG_I2C_HDMI_B bool @@ -68,8 +71,10 @@ config GFX_GMA depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \ || NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE \ || NORTHBRIDGE_INTEL_HASWELL \ - || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE - depends on MAINBOARD_USE_LIBGFXINIT + || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE \ + || SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE \ + || SOC_INTEL_WHISKEYLAKE + depends on MAINBOARD_USE_LIBGFXINIT || INTEL_GMA_LIBGFXINIT_EDID select RAMSTAGE_LIBHWBASE config GFX_GMA_INTERNAL_IS_EDP @@ -94,7 +99,8 @@ config GFX_GMA_DYN_CPU config GFX_GMA_GENERATION string default "Broxton" if SOC_INTEL_APOLLOLAKE - default "Skylake" if SOC_INTEL_SKYLAKE + default "Skylake" if SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE || \ + SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL default "Ironlake" if NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index e128ad6474..cea319e976 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -50,7 +50,7 @@ CONFIG_GFX_GMA_DEFAULT_MMIO := 0 # dummy, will be overwritten at runtime subdirs-y += ../../../../3rdparty/libgfxinit -ramstage-y += gma.ads +ramstage-y += gma.ads gma.adb ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-gfx_init.ads ifeq ($(CONFIG_LINEAR_FRAMEBUFFER),y) diff --git a/src/drivers/intel/gma/gma.adb b/src/drivers/intel/gma/gma.adb new file mode 100644 index 0000000000..10885e6e09 --- /dev/null +++ b/src/drivers/intel/gma/gma.adb @@ -0,0 +1,37 @@ +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; + +package body GMA is + + function read_edid + (raw_edid : out HW.GFX.EDID.Raw_EDID_Data; + port : in Interfaces.C.int) + return Interfaces.C.int + is + use type Interfaces.C.int; + success : Boolean := true; + begin + if port not in Active_Port_Type'Pos (Active_Port_Type'First) + .. Active_Port_Type'Pos (Active_Port_Type'Last) + then + raw_edid := (others => 0); + return -2; + else + if not HW.GFX.GMA.Is_Initialized then + HW.GFX.GMA.Initialize (Success => success); + end if; + if success then + HW.GFX.GMA.Display_Probing.Read_EDID + (raw_edid, Active_Port_Type'Val (port), success); + end if; + if success then + return 0; + else + return -1; + end if; + end if; + end read_edid; + +end GMA; diff --git a/src/drivers/intel/gma/gma.ads b/src/drivers/intel/gma/gma.ads index a6ce3a4f77..0b4b66bde7 100644 --- a/src/drivers/intel/gma/gma.ads +++ b/src/drivers/intel/gma/gma.ads @@ -1,2 +1,14 @@ +with Interfaces.C; + +with HW.GFX.EDID; + package GMA is + + function read_edid + (raw_edid : out HW.GFX.EDID.Raw_EDID_Data; + Port : in Interfaces.C.int) + return Interfaces.C.int + with + Export, Convention => C, External_Name => "gma_read_edid"; + end GMA; diff --git a/src/drivers/intel/gma/libgfxinit.h b/src/drivers/intel/gma/libgfxinit.h index c67870e4e0..c4a8a5b4d2 100644 --- a/src/drivers/intel/gma/libgfxinit.h +++ b/src/drivers/intel/gma/libgfxinit.h @@ -14,6 +14,19 @@ #ifndef DRIVERS_INTEL_GMA_LIBGFXINIT_H #define DRIVERS_INTEL_GMA_LIBGFXINIT_H +enum { + GMA_PORT_DISABLED, + GMA_PORT_INTERNAL, + GMA_PORT_DP1, + GMA_PORT_DP2, + GMA_PORT_DP3, + GMA_PORT_HDMI1, /* or DVI */ + GMA_PORT_HDMI2, /* or DVI */ + GMA_PORT_HDMI3, /* or DVI */ + GMA_PORT_ANALOG, +}; + void gma_gfxinit(int *lightup_ok); +int gma_read_edid(unsigned char edid[], int port); #endif diff --git a/src/drivers/intel/ptt/Kconfig b/src/drivers/intel/ptt/Kconfig new file mode 100644 index 0000000000..fb70f9a02c --- /dev/null +++ b/src/drivers/intel/ptt/Kconfig @@ -0,0 +1,6 @@ +config HAVE_INTEL_PTT + bool + default n + select VBOOT_MOCK_SECDATA if VBOOT + help + Activate if your platform has Intel Platform Trust Technology like Intel iTPM and you want to use it. diff --git a/src/drivers/intel/ptt/Makefile.inc b/src/drivers/intel/ptt/Makefile.inc new file mode 100644 index 0000000000..fdecc89b9f --- /dev/null +++ b/src/drivers/intel/ptt/Makefile.inc @@ -0,0 +1,4 @@ +romstage-$(CONFIG_HAVE_INTEL_PTT) += ptt.c +ramstage-$(CONFIG_HAVE_INTEL_PTT) += ptt.c +postcar-$(CONFIG_HAVE_INTEL_PTT) += ptt.c +verstage-$(CONFIG_HAVE_INTEL_PTT) += ptt.c diff --git a/src/drivers/intel/ptt/ptt.c b/src/drivers/intel/ptt/ptt.c new file mode 100644 index 0000000000..738de50a8f --- /dev/null +++ b/src/drivers/intel/ptt/ptt.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "ptt.h" + +#define PCI_ME_HFSTS4 0x64 +#define PTT_ENABLE (1 << 19) + +/* Dump Intel ME register */ +static uint32_t read_register(int reg_addr) +{ + if (!PCH_DEV_CSE) + return 0xFFFFFFFF; + + return pci_read_config32(PCH_DEV_CSE, reg_addr); +} + +/* + * ptt_active() + * + * Check if PTT Flag is set - so that PTT is active. + * + * Return true if active, false otherwise. + */ +bool ptt_active(void) +{ + uint32_t fwsts4 = read_register(PCI_ME_HFSTS4); + + if (fwsts4 == 0xFFFFFFFF) + return false; + + if ((fwsts4 & PTT_ENABLE) == 0) { + printk(BIOS_DEBUG, "Intel ME Establishment bit not valid.\n"); + return false; + } + + return true; +} diff --git a/src/northbridge/intel/gm45/stage_cache.c b/src/drivers/intel/ptt/ptt.h similarity index 52% rename from src/northbridge/intel/gm45/stage_cache.c rename to src/drivers/intel/ptt/ptt.h index 47f08c1397..ed5e90f599 100644 --- a/src/northbridge/intel/gm45/stage_cache.c +++ b/src/drivers/intel/ptt/ptt.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google, Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -11,19 +9,19 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * This driver checks if the PTT Bit is set correctly within the FWSTS4 + * register. This is needed in order to use the iTPM, because we have to + * check prior using the interface that this bit is set correctly - otherwise + * it could work unpredictable. The bit should already be set if the Intel ME + * is still in the preboot phase. + * */ - #include -#include -#include - -void stage_cache_external_region(void **base, size_t *size) -{ - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)(northbridge_get_tseg_base() - + CONFIG_SMM_RESERVED_SIZE); -} +/* + * ptt_active + * + * Checks if the Intel PTT is active. If PTT is active, returns true, + * false otherwise. + */ +bool ptt_active(void); diff --git a/src/drivers/ipmi/chip.h b/src/drivers/ipmi/chip.h index eb8b4e6d34..1c5afe7b59 100644 --- a/src/drivers/ipmi/chip.h +++ b/src/drivers/ipmi/chip.h @@ -24,6 +24,17 @@ struct drivers_ipmi_config { u8 gpe_interrupt; u8 have_apic; u32 apic_interrupt; + /* + * Wait for BMC to boot. + * This can be used if the BMC takes a long time to boot after PoR: + * AST2400 on Supermicro X11SSH: 34 s + */ + bool wait_for_bmc; + /* + * The timeout in seconds to wait for the IPMI service to be loaded. + * Will be used if wait_for_bmc is true. + */ + u16 bmc_boot_timeout; }; #endif /* _IMPI_CHIP_H_ */ diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 0cc4e0a965..21102bb74e 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -32,6 +32,7 @@ #endif #include #include +#include #include "ipmi_kcs.h" #include "chip.h" @@ -62,12 +63,37 @@ static void ipmi_kcs_init(struct device *dev) { struct ipmi_devid_rsp rsp; uint32_t man_id = 0, prod_id = 0; + struct drivers_ipmi_config *conf = NULL; if (!dev->enabled) return; + printk(BIOS_DEBUG, "IPMI: PNP KCS 0x%x\n", dev->path.pnp.port); + + if (dev->chip_info) + conf = dev->chip_info; + /* Get IPMI version for ACPI and SMBIOS */ + if (conf && conf->wait_for_bmc && conf->bmc_boot_timeout) { + struct stopwatch sw; + stopwatch_init_msecs_expire(&sw, conf->bmc_boot_timeout * 1000); + printk(BIOS_DEBUG, "IPMI: Waiting for BMC...\n"); + + while (!stopwatch_expired(&sw)) { + if (inb(dev->path.pnp.port) != 0xff) + break; + mdelay(100); + } + if (stopwatch_expired(&sw)) { + printk(BIOS_INFO, "IPMI: Waiting for BMC timed out\n"); + /* Don't write tables if communication failed */ + dev->enabled = 0; + return; + } + } + if (!ipmi_get_device_id(dev, &rsp)) { + /* Queried the IPMI revision from BMC */ ipmi_revision_minor = IPMI_IPMI_VERSION_MINOR(rsp.ipmi_version); ipmi_revision_major = IPMI_IPMI_VERSION_MAJOR(rsp.ipmi_version); diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c index 4e1043edb7..c74fd701c9 100644 --- a/src/drivers/spi/adesto.c +++ b/src/drivers/spi/adesto.c @@ -181,7 +181,8 @@ static int adesto_write(const struct spi_flash *flash, u32 offset, size_t len, goto out; } - ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + ret = spi_flash_cmd_wait_ready(flash, + SPI_FLASH_PROG_TIMEOUT_MS); if (ret) goto out; diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c index b580dc3df0..6e1234baa7 100644 --- a/src/drivers/spi/amic.c +++ b/src/drivers/spi/amic.c @@ -155,7 +155,8 @@ static int amic_write(const struct spi_flash *flash, u32 offset, size_t len, goto out; } - ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + ret = spi_flash_cmd_wait_ready(flash, + SPI_FLASH_PROG_TIMEOUT_MS); if (ret) goto out; diff --git a/src/drivers/spi/atmel.c b/src/drivers/spi/atmel.c index 58a2862eeb..ac7f0d92e7 100644 --- a/src/drivers/spi/atmel.c +++ b/src/drivers/spi/atmel.c @@ -137,7 +137,8 @@ static int atmel_write(const struct spi_flash *flash, u32 offset, size_t len, goto out; } - ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + ret = spi_flash_cmd_wait_ready(flash, + SPI_FLASH_PROG_TIMEOUT_MS); if (ret) goto out; diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index f3cf70ef1b..c6fdba17b8 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -270,7 +270,8 @@ static int eon_write(const struct spi_flash *flash, goto out; } - ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + ret = spi_flash_cmd_wait_ready(flash, + SPI_FLASH_PROG_TIMEOUT_MS); if (ret) { printk(BIOS_WARNING, "SF: EON Page Program timeout\n"); goto out; diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 1ff594a24a..71433cc1ed 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -212,7 +212,8 @@ static int gigadevice_write(const struct spi_flash *flash, u32 offset, goto out; } - ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + ret = spi_flash_cmd_wait_ready(flash, + SPI_FLASH_PROG_TIMEOUT_MS); if (ret) goto out; diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index 5a97b8f794..a41e96f671 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -249,7 +249,8 @@ static int macronix_write(const struct spi_flash *flash, u32 offset, size_t len, break; } - ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + ret = spi_flash_cmd_wait_ready(flash, + SPI_FLASH_PROG_TIMEOUT_MS); if (ret) break; diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index 4a241baf09..c3a071e956 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -264,7 +264,8 @@ static int spansion_write(const struct spi_flash *flash, u32 offset, size_t len, break; } - ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + ret = spi_flash_cmd_wait_ready(flash, + SPI_FLASH_PROG_TIMEOUT_MS); if (ret) break; diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index a81306e386..cfa500e6dd 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -232,7 +232,8 @@ int spi_flash_cmd_erase(const struct spi_flash *flash, u32 offset, size_t len) if (ret) goto out; - ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT); + ret = spi_flash_cmd_wait_ready(flash, + SPI_FLASH_PAGE_ERASE_TIMEOUT_MS); if (ret) goto out; } diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index 4a9e289029..95c51a8b05 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -7,15 +7,6 @@ #ifndef SPI_FLASH_INTERNAL_H #define SPI_FLASH_INTERNAL_H -/* Common parameters -- kind of high, but they should only occur when there - * is a problem (and well your system already is broken), so err on the side - * of caution in case we're dealing with slower SPI buses and/or processors. - */ -#define CONF_SYS_HZ 100 -#define SPI_FLASH_PROG_TIMEOUT (2 * CONF_SYS_HZ) -#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONF_SYS_HZ) -#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONF_SYS_HZ) - /* Common commands */ #define CMD_READ_ID 0x9f diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index abe3f2ace6..429afa095d 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -179,7 +179,7 @@ sst_byte_write(const struct spi_flash *flash, u32 offset, const void *buf) if (ret) return ret; - return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT_MS); } static int sst_write_256(const struct spi_flash *flash, u32 offset, size_t len, @@ -239,7 +239,8 @@ static int sst_write_256(const struct spi_flash *flash, u32 offset, size_t len, break; } - ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + ret = spi_flash_cmd_wait_ready(flash, + SPI_FLASH_PROG_TIMEOUT_MS); if (ret) break; @@ -294,7 +295,8 @@ static int sst_write_ai(const struct spi_flash *flash, u32 offset, size_t len, break; } - ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + ret = spi_flash_cmd_wait_ready(flash, + SPI_FLASH_PROG_TIMEOUT_MS); if (ret) break; diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index 6625764268..98f6e4e5b2 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -331,7 +331,8 @@ static int stmicro_write(const struct spi_flash *flash, goto out; } - ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + ret = spi_flash_cmd_wait_ready(flash, + SPI_FLASH_PROG_TIMEOUT_MS); if (ret) goto out; diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 9e9bb00464..3e0a2669d9 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -326,7 +326,8 @@ static int winbond_write(const struct spi_flash *flash, u32 offset, size_t len, goto out; } - ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + ret = spi_flash_cmd_wait_ready(flash, + SPI_FLASH_PROG_TIMEOUT_MS); if (ret) goto out; diff --git a/src/drivers/xpowers/axp209/Kconfig b/src/drivers/xpowers/axp209/Kconfig deleted file mode 100644 index 684873c127..0000000000 --- a/src/drivers/xpowers/axp209/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -config DRIVER_XPOWERS_AXP209 - bool - default n - help - X-Powers AXP902 Power Management Unit - -if DRIVER_XPOWERS_AXP209 - -config DRIVER_XPOWERS_AXP209_BOOTBLOCK - bool - default n - help - Make AXP209 functionality available in he bootblock. - -endif # DRIVER_XPOWERS_AXP209 diff --git a/src/drivers/xpowers/axp209/Makefile.inc b/src/drivers/xpowers/axp209/Makefile.inc deleted file mode 100644 index e08a8e21a6..0000000000 --- a/src/drivers/xpowers/axp209/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ -ifeq ($(CONFIG_DRIVER_XPOWERS_AXP209),y) - -bootblock-$(CONFIG_DRIVER_XPOWERS_AXP209_BOOTBLOCK) += axp209.c -romstage-y += axp209.c -ramstage-y += axp209.c - -endif diff --git a/src/drivers/xpowers/axp209/axp209.c b/src/drivers/xpowers/axp209/axp209.c deleted file mode 100644 index 93e864dff7..0000000000 --- a/src/drivers/xpowers/axp209/axp209.c +++ /dev/null @@ -1,324 +0,0 @@ -/* - * Driver for X-Powers AXP 209 Power Management Unit - * - * Despite axp209_read/write only working on a byte at a time, there is no such - * limitation in the AXP209. - * - * Copyright (C) 2013 Alexandru Gagniuc - * Subject to the GNU GPL v2, or (at your option) any later version. - */ - -#include -#include -#include -#include - -#include "axp209.h" -#include "chip.h" - -/* Hide these definitions from the rest of the source, so keep them here */ -enum registers { - REG_POWER_STATUS = 0x00, - REG_POWER_MODE = 0x01, - REG_OTG_VBUS = 0x02, - REG_CHIP_ID = 0x03, - REG_CHIP_PWROUT_CTL = 0x12, - REG_DCDC2_VOLTAGE = 0x23, - REG_DCDC2_LDO3_CTL = 0x25, - REG_DCDC3_VOLTAGE = 0x27, - REG_LDO24_VOLTAGE = 0x28, - REG_LDO3_VOLTAGE = 0x29, - REG_VBUS_IPSOUT = 0x30, - REG_PWROFF_VOLTAGE = 0x31, - REG_SHTDWN_SETTING = 0x32, -}; - -/* REG_LDO24_VOLTAGE definitions */ -#define REG_LDO24_VOLTAGE_LDO2_MASK (0xf << 4) -#define REG_LDO24_VOLTAGE_LDO2_VAL(x) ((x << 4) & REG_LDO24_VOLTAGE_LDO2_MASK) -#define REG_LDO24_VOLTAGE_LDO4_MASK (0xf << 0) -#define REG_LDO24_VOLTAGE_LDO4_VAL(x) ((x << 0) & REG_LDO24_VOLTAGE_LDO4_MASK) - -/* - * Read and write accessors. We only work on one register at a time, but there - * is no limitation on the AXP209 as to how many registers we may read or write - * in one transaction. - * These return the number of bytes read/written, or an error code. In this - * case, they return 1 on success, or an error code otherwise. This is done to - * work with I2C drivers that return either 0 on success or the number of bytes - * actually transferred. - */ -static int axp209_read(u8 bus, u8 reg, u8 *val) -{ - if (i2c_readb(bus, AXP209_I2C_ADDR, reg, val) < 0) - return CB_ERR; - return 1; -} - -static int axp209_write(u8 bus, u8 reg, u8 val) -{ - if (i2c_writeb(bus, AXP209_I2C_ADDR, reg, val) < 0) - return CB_ERR; - return 1; -} - -/** - * \brief Identify and initialize an AXP209 on the I2C bus - * - * @param[in] bus I2C bus to which the AXP209 is connected - * @return CB_SUCCES on if an AXP209 is found, or an error code otherwise. - */ -enum cb_err axp209_init(u8 bus) -{ - u8 id; - - if (axp209_read(bus, REG_CHIP_ID, &id) != 1) - return CB_ERR; - - /* From U-Boot code : Low 4 bits is chip version */ - if ((id & 0x0f) != 0x1) { - printk(BIOS_ERR, "[axp209] ID 0x%x does not match\n", id); - return CB_ERR; - } - - return CB_SUCCESS; -} - -/** - * \brief Configure the output voltage of DC-DC2 converter - * - * If the requested voltage is not available, the next lowest voltage will - * be applied. - * Valid values are between 700mV and 2275mV - * - * @param[in] millivolts voltage in mV units. - * @param[in] bus I2C bus to which the AXP209 is connected - * @return CB_SUCCES on success, - * CB_ERR_ARG if voltage is out of range, or an error code otherwise. - */ -enum cb_err axp209_set_dcdc2_voltage(u8 bus, u16 millivolts) -{ - u8 val; - - if (millivolts < 700 || millivolts > 2275) - return CB_ERR_ARG; - - val = (millivolts - 700) / 25; - - if (axp209_write(bus, REG_DCDC2_VOLTAGE, val) != 1) - return CB_ERR; - - return CB_SUCCESS; -} - -/** - * \brief Configure the output voltage of DC-DC3 converter - * - * If the requested voltage is not available, the next lowest voltage will - * be applied. - * Valid values are between 700mV and 3500mV - * - * @param[in] millivolts voltage in mV units. - * @param[in] bus I2C bus to which the AXP209 is connected - * @return CB_SUCCES on success, - * CB_ERR_ARG if voltage is out of range, or an error code otherwise. - */ -enum cb_err axp209_set_dcdc3_voltage(u8 bus, u16 millivolts) -{ - u8 val; - - if (millivolts < 700 || millivolts > 3500) - return CB_ERR_ARG; - - val = (millivolts - 700) / 25; - - if (axp209_write(bus, REG_DCDC3_VOLTAGE, val) != 1) - return CB_ERR; - - return CB_SUCCESS; -} - -/** - * \brief Configure the output voltage of LDO2 regulator - * - * If the requested voltage is not available, the next lowest voltage will - * be applied. - * Valid values are between 700mV and 3300mV - * - * @param[in] millivolts voltage in mV units. - * @param[in] bus I2C bus to which the AXP209 is connected - * @return CB_SUCCES on success, - * CB_ERR_ARG if voltage is out of range, or an error code otherwise. - */ -enum cb_err axp209_set_ldo2_voltage(u8 bus, u16 millivolts) -{ - u8 reg8, val; - - if (millivolts < 1800 || millivolts > 3300) - return CB_ERR_ARG; - - /* Try to read the register first, and stop here on error */ - if (axp209_read(bus, REG_LDO24_VOLTAGE, ®8) != 1) - return CB_ERR; - - val = (millivolts - 1800) / 100; - reg8 &= ~REG_LDO24_VOLTAGE_LDO2_MASK; - reg8 |= REG_LDO24_VOLTAGE_LDO2_VAL(val); - - if (axp209_write(bus, REG_LDO24_VOLTAGE, reg8) != 1) - return CB_ERR; - - return CB_SUCCESS; -} - -/** - * \brief Configure the output voltage of LDO4 regulator - * - * If the requested voltage is not available, the next lowest voltage will - * be applied. - * Valid values are between 700mV and 3500mV. Datasheet lists maximum voltage at - * 2250mV, but hardware samples go as high as 3500mV. - * - * @param[in] millivolts voltage in mV units. - * @param[in] bus I2C bus to which the AXP209 is connected - * @return CB_SUCCES on success, - * CB_ERR_ARG if voltage is out of range, or an error code otherwise. - */ -enum cb_err axp209_set_ldo3_voltage(u8 bus, u16 millivolts) -{ - u8 val; - - /* Datasheet lists 2250 max, but PMU will output up to 3500mV */ - if (millivolts < 700 || millivolts > 3500) - return CB_ERR_ARG; - - val = (millivolts - 700) / 25; - - if (axp209_write(bus, REG_LDO3_VOLTAGE, val) != 1) - return CB_ERR; - - return CB_SUCCESS; -} - -/** - * \brief Configure the output voltage of DC-DC2 converter - * - * If the requested voltage is not available, the next lowest voltage will - * be applied. - * Valid values are between 1250V and 3300mV - * - * @param[in] millivolts voltage in mV units. - * @param[in] bus I2C bus to which the AXP209 is connected - * @return CB_SUCCES on success, - * CB_ERR_ARG if voltage is out of range, or an error code otherwise. - */ -enum cb_err axp209_set_ldo4_voltage(u8 bus, u16 millivolts) -{ - u8 reg8, val; - - if (millivolts < 1250 || millivolts > 3300) - return CB_ERR_ARG; - - /* Try to read the register first, and stop here on error */ - if (axp209_read(bus, REG_LDO24_VOLTAGE, ®8) != 1) - return CB_ERR; - - if (millivolts <= 2000) - val = (millivolts - 1200) / 100; - else if (millivolts <= 2700) - val = 9 + (millivolts - 2500) / 100; - else if (millivolts <= 2800) - val = 11; - else - val = 12 + (millivolts - 3000) / 100; - - reg8 &= ~REG_LDO24_VOLTAGE_LDO4_MASK; - reg8 |= REG_LDO24_VOLTAGE_LDO4_VAL(val); - - if (axp209_write(bus, REG_LDO24_VOLTAGE, reg8) != 1) - return CB_ERR; - - return CB_SUCCESS; -} - -static const struct { - enum cb_err (*set_voltage) (u8 bus, u16 mv); - const char *name; -} vtable[] = { { - .set_voltage = axp209_set_dcdc2_voltage, - .name = "DCDC2", - }, { - .set_voltage = axp209_set_dcdc3_voltage, - .name = "DCDC3", - }, { - .set_voltage = axp209_set_ldo2_voltage, - .name = "LDO2", - }, { - .set_voltage = axp209_set_ldo3_voltage, - .name = "LDO3", - }, { - .set_voltage = axp209_set_ldo4_voltage, - .name = "LDO4", - } -}; - -static enum cb_err set_rail(u8 bus, int idx, u16 mv) -{ - enum cb_err err; - const char *name = vtable[idx].name; - - /* If voltage isn't specified, don't touch the rail */ - if (mv == 0) { - printk(BIOS_DEBUG, "[axp209] Skipping %s configuration\n", - name); - return CB_SUCCESS; - } - - if ((err = vtable[idx].set_voltage(bus, mv) != CB_SUCCESS)) { - printk(BIOS_ERR, "[axp209] Failed to set %s to %u mv\n", - name, mv); - return err; - } - - return CB_SUCCESS; -} - -/** - * \brief Configure all voltage rails - * - * Configure all converters and regulators from devicetree config. If any of the - * voltages are not declared (i.e. are zero), the respective rail will not be - * reconfigured, and retain its powerup voltage. - * - * @param[in] cfg pointer to @ref drivers_xpowers_axp209_config structure - * @param[in] bus I2C bus to which the AXP209 is connected - * @return CB_SUCCES on success, or an error code otherwise. - */ -enum cb_err axp209_set_voltages(u8 bus, const struct - drivers_xpowers_axp209_config *cfg) -{ - enum cb_err err; - - /* Don't worry about what the error is. Console prints that */ - err = set_rail(bus, 0, cfg->dcdc2_voltage_mv); - err |= set_rail(bus, 1, cfg->dcdc3_voltage_mv); - err |= set_rail(bus, 2, cfg->ldo2_voltage_mv); - err |= set_rail(bus, 3, cfg->ldo3_voltage_mv); - err |= set_rail(bus, 4, cfg->ldo4_voltage_mv); - - if (err != CB_SUCCESS) - return CB_ERR; - - return CB_SUCCESS; -} - -/* - * Usually, the AXP209 is enabled and configured in romstage, so there is no - * need for a full ramstage driver. Hence .enable_dev is NULL. - */ -#ifndef __PRE_RAM__ -struct chip_operations drivers_xpowers_axp209_config = { - CHIP_NAME("X-Powers AXP 209 Power Management Unit") - .enable_dev = NULL, -}; -#endif /* __PRE_RAM__ */ diff --git a/src/drivers/xpowers/axp209/axp209.h b/src/drivers/xpowers/axp209/axp209.h deleted file mode 100644 index c9cdd7efba..0000000000 --- a/src/drivers/xpowers/axp209/axp209.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Definitions for X-Powers AXP 209 Power Management Unit - * - * Copyright (C) 2013 Alexandru Gagniuc - * Subject to the GNU GPL v2, or (at your option) any later version. - */ - -#include -#include "chip.h" - -#define AXP209_I2C_ADDR (0x68 >> 1) - -enum cb_err axp209_init(u8 bus); -enum cb_err axp209_set_dcdc2_voltage(u8 bus, u16 millivolts); -enum cb_err axp209_set_dcdc3_voltage(u8 bus, u16 millivolts); -enum cb_err axp209_set_ldo2_voltage(u8 bus, u16 millivolts); -enum cb_err axp209_set_ldo3_voltage(u8 bus, u16 millivolts); -enum cb_err axp209_set_ldo4_voltage(u8 bus, u16 millivolts); -enum cb_err axp209_set_voltages(u8 bus, const struct - drivers_xpowers_axp209_config *cfg); diff --git a/src/drivers/xpowers/axp209/chip.h b/src/drivers/xpowers/axp209/chip.h deleted file mode 100644 index c19253d6b5..0000000000 --- a/src/drivers/xpowers/axp209/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * X-Powers AXP 209 devicetree.cb interface - * - * Copyright (C) 2013 Alexandru Gagniuc - * Subject to the GNU GPL v2, or (at your option) any later version. - */ - -#ifndef AXP209_CHIP_H -#define AXP209_CHIP_H - -#include - -struct drivers_xpowers_axp209_config { - u16 dcdc2_voltage_mv; /**< DCDC2 converter voltage output */ - u16 dcdc3_voltage_mv; /**< DCDC3 converter voltage output */ - u16 ldo2_voltage_mv; /**< LDO2 regulator voltage output */ - u16 ldo3_voltage_mv; /**< LDO3 regulator voltage output */ - u16 ldo4_voltage_mv; /**< LDO4 regulator voltage output */ -}; - -#endif /* AXP209_CHIP_H */ diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl index 1ff50991c0..025339540f 100644 --- a/src/ec/google/chromeec/acpi/battery.asl +++ b/src/ec/google/chromeec/acpi/battery.asl @@ -194,7 +194,7 @@ Method (BBST, 4, Serialized) Store (Local1, Index (Arg1, 0)) // Notify if battery state has changed since last time - If (LNotEqual (Local1, Arg2)) { + If (LNotEqual (Local1, DeRefOf (Arg2))) { Store (Local1, Arg2) If (LEqual(Arg0, 0)) { Notify (BAT0, 0x80) @@ -326,7 +326,7 @@ Device (BAT0) Method (_BST, 0, Serialized) { - Return (BBST (0, PBST, BSTP, BFWK)) + Return (BBST (0, PBST, RefOf (BSTP), BFWK)) } } @@ -416,7 +416,7 @@ Device (BAT1) Method (_BST, 0, Serialized) { - Return (BBST (1, PBST, BSTP, BFWK)) + Return (BBST (1, PBST, RefOf (BSTP), BFWK)) } } #endif diff --git a/src/ec/google/wilco/Kconfig b/src/ec/google/wilco/Kconfig index 4202c1d7b5..25d7cfafc2 100644 --- a/src/ec/google/wilco/Kconfig +++ b/src/ec/google/wilco/Kconfig @@ -6,6 +6,8 @@ config EC_GOOGLE_WILCO help Google Wilco Embedded Controller interface. +if EC_GOOGLE_WILCO + config EC_BASE_ACPI_DATA hex default 0x930 @@ -46,3 +48,5 @@ config EC_BASE_PACKET mailbox interface data region. This data buffer is used along with the host command and data registers to drive the EC mailbox interface. This is also the MEC EMI base address. + +endif # EC_GOOGLE_WILCO diff --git a/src/include/bootmem.h b/src/include/bootmem.h index c935cb919f..2e33fcdf76 100644 --- a/src/include/bootmem.h +++ b/src/include/bootmem.h @@ -37,6 +37,7 @@ enum bootmem_type { BM_MEM_NVS, /* ACPI NVS Memory */ BM_MEM_UNUSABLE, /* Unusable address space */ BM_MEM_VENDOR_RSVD, /* Vendor Reserved */ + BM_MEM_OPENSBI, /* Risc-V OpenSBI */ BM_MEM_BL31, /* Arm64 BL31 exectuable */ BM_MEM_TABLE, /* Ram configuration tables are kept in */ /* Tags below this point are ignored for the OS table. */ diff --git a/src/include/bootsplash.h b/src/include/bootsplash.h new file mode 100644 index 0000000000..84ba34cc90 --- /dev/null +++ b/src/include/bootsplash.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Johanna Schander + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BOOTSPLASH_H__ +#define __BOOTSPLASH_H__ + +#include + +/** + * Wraps bootsplash setup for vesa + */ +void set_vesa_bootsplash(void); + + +/** + * Sets up the framebuffer with the bootsplash.jpg from cbfs. + * Returns 0 on success + * CB_ERR on cbfs errors + * and >0 on jpeg errors. + */ +void set_bootsplash(unsigned char *framebuffer, unsigned int x_resolution, + unsigned int y_resolution, unsigned int fb_resolution); + +#endif diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 3071106080..b8b99ecdab 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -583,4 +583,25 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params); void *backup_default_smm_area(void); void restore_default_smm_area(void *smm_save_area); +/* + * Fills in the arguments for the entire SMM region covered by chipset + * protections. e.g. TSEG. + */ +void smm_region(uintptr_t *start, size_t *size); + +enum { + /* SMM handler area. */ + SMM_SUBREGION_HANDLER, + /* SMM cache region. */ + SMM_SUBREGION_CACHE, + /* Chipset specific area. */ + SMM_SUBREGION_CHIPSET, + /* Total sub regions supported. */ + SMM_SUBREGION_NUM, +}; + +/* Fills in the start and size for the requested SMM subregion. Returns + * 0 on success, < 0 on failure. */ +int smm_subregion(int sub, uintptr_t *start, size_t *size); + #endif /* CPU_X86_SMM_H */ diff --git a/src/include/device/device.h b/src/include/device/device.h index 676da65263..8e1e62aa7c 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -126,7 +126,6 @@ struct device { unsigned int on_mainboard : 1; unsigned int disable_pcie_aspm : 1; unsigned int hidden : 1; /* set if we should hide from UI */ - struct pci_irq_info pci_irq_info[4]; u8 command; /* Base registers for this device. I/O, MEM and Expansion ROM */ @@ -138,6 +137,7 @@ struct device { DEVTREE_CONST struct bus *link_list; #if !DEVTREE_EARLY + struct pci_irq_info pci_irq_info[4]; struct device_operations *ops; struct chip_operations *chip_ops; const char *name; @@ -275,8 +275,6 @@ void mmconf_resource(struct device *dev, unsigned long index); void tolm_test(void *gp, struct device *dev, struct resource *new); u32 find_pci_tolm(struct bus *bus); -DEVTREE_CONST struct device *dev_find_slot(unsigned int bus, - unsigned int devfn); DEVTREE_CONST struct device *dev_find_next_pci_device( DEVTREE_CONST struct device *previous_dev); DEVTREE_CONST struct device *dev_find_slot_on_smbus(unsigned int bus, @@ -292,6 +290,34 @@ DEVTREE_CONST struct device *pcidev_path_on_bus(unsigned int bus, pci_devfn_t de DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn); DEVTREE_CONST struct bus *pci_root_bus(void); +/* To be deprecated, avoid using. */ +DEVTREE_CONST struct device *dev_find_slot(unsigned int bus, unsigned int devfn); +DEVTREE_CONST struct device *pcidev_path_on_root_debug(pci_devfn_t devfn, const char *func); + +/* Robust discovery of chip_info. */ +void devtree_bug(const char *func, pci_devfn_t devfn); +void __noreturn devtree_die(void); + +static inline DEVTREE_CONST void *config_of(const struct device *dev) +{ + if (dev && dev->chip_info) + return dev->chip_info; + + devtree_die(); +} + +static inline DEVTREE_CONST void *config_of_path(pci_devfn_t devfn) +{ + const struct device *dev = pcidev_path_on_root(devfn); + if (dev) + return config_of(dev); + + devtree_bug(__func__, devfn); + + dev = dev_find_slot(0, devfn); + return config_of(dev); +} + void scan_smbus(struct device *bus); void scan_generic_bus(struct device *bus); void scan_static_bus(struct device *bus); diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 0c846c64d9..1aac48e9aa 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -292,18 +292,19 @@ #define PCI_DEVICE_ID_ATI_RADEON_RC 0x5146 #define PCI_DEVICE_ID_ATI_RADEON_RD 0x5147 +#define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200 #define PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT 0x1600 #define PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_HT 0x1400 #define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_HT 0x141A -#define PCI_DEVICE_ID_AMD_16H_MODEL_000F_NB_HT 0x1536 -#define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_HT 0x1566 #define PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT 0x1570 #define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT 0x15B0 -#define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200 -#define PCI_DEVICE_ID_AMD_15H_NB_IOMMU 0x1419 +#define PCI_DEVICE_ID_AMD_16H_MODEL_000F_NB_HT 0x1536 +#define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_HT 0x1566 +#define PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB 0x15d0 +#define PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_IOMMU 0x1419 #define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU 0x1423 -#define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU 0x1567 #define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU 0x1577 +#define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU 0x1567 #define PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB_IOMMU 0x15d1 #define PCI_DEVICE_ID_ATI_SB600_LPC 0x438D @@ -2698,16 +2699,17 @@ #define PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE 0x9d43 #define PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM 0x9d48 #define PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM 0x9d46 +#define PCI_DEVICE_ID_INTEL_SPT_H_H110 0xa143 #define PCI_DEVICE_ID_INTEL_SPT_H_H170 0xa144 #define PCI_DEVICE_ID_INTEL_SPT_H_Z170 0xa145 #define PCI_DEVICE_ID_INTEL_SPT_H_Q170 0xa146 #define PCI_DEVICE_ID_INTEL_SPT_H_Q150 0xa147 #define PCI_DEVICE_ID_INTEL_SPT_H_B150 0xa148 #define PCI_DEVICE_ID_INTEL_SPT_H_C236 0xa149 -#define PCI_DEVICE_ID_INTEL_SPT_H_CM236 0xa150 -#define PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM 0xa14e -#define PCI_DEVICE_ID_INTEL_SPT_H_H110 0xa143 +#define PCI_DEVICE_ID_INTEL_SPT_H_C232 0xa14a #define PCI_DEVICE_ID_INTEL_SPT_H_QM170 0xa14d +#define PCI_DEVICE_ID_INTEL_SPT_H_HM170 0xa14e +#define PCI_DEVICE_ID_INTEL_SPT_H_CM236 0xa150 #define PCI_DEVICE_ID_INTEL_SPT_H_HM175 0xa152 #define PCI_DEVICE_ID_INTEL_SPT_H_QM175 0xa153 #define PCI_DEVICE_ID_INTEL_SPT_H_CM238 0xa154 @@ -2728,8 +2730,15 @@ #define PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC 0x9d85 #define PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC 0x9d84 #define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83 +#define PCI_DEVICE_ID_INTEL_CNP_H_LPC_H310 0xa303 +#define PCI_DEVICE_ID_INTEL_CNP_H_LPC_H370 0xa304 +#define PCI_DEVICE_ID_INTEL_CNP_H_LPC_Z390 0xa305 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370 0xa306 +#define PCI_DEVICE_ID_INTEL_CNP_H_LPC_B360 0xa308 +#define PCI_DEVICE_ID_INTEL_CNP_H_LPC_C246 0xa309 +#define PCI_DEVICE_ID_INTEL_CNP_H_LPC_C242 0xa30a #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370 0xa30c +#define PCI_DEVICE_ID_INTEL_CNP_H_LPC_HM370 0xa30d #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_CM246 0xa30e #define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI 0x3480 #define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0 0x3481 @@ -3002,6 +3011,10 @@ #define PCI_DEVICE_ID_INTEL_CNL_SPI1 0x9dab #define PCI_DEVICE_ID_INTEL_CNL_SPI2 0x9dfb #define PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI 0x9da4 +#define PCI_DEVICE_ID_INTEL_CNP_H_SPI0 0xa32a +#define PCI_DEVICE_ID_INTEL_CNP_H_SPI1 0xa32b +#define PCI_DEVICE_ID_INTEL_CNP_H_SPI2 0xa37b +#define PCI_DEVICE_ID_INTEL_CNP_H_HWSEQ_SPI 0xa324 #define PCI_DEVICE_ID_INTEL_ICP_SPI0 0x34aa #define PCI_DEVICE_ID_INTEL_ICP_SPI1 0x34ab #define PCI_DEVICE_ID_INTEL_ICP_SPI2 0x34fb @@ -3042,11 +3055,14 @@ #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4 0x5A4A #define PCI_DEVICE_ID_INTEL_CFL_GT2_ULT 0x3EA5 #define PCI_DEVICE_ID_INTEL_CFL_H_GT2 0x3e9b -#define PCI_DEVICE_ID_INTEL_CFL_S_GT2 0x3e92 #define PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2 0x3e94 -#define PCI_DEVICE_ID_INTEL_ICL_GT0_ULT 0x8A70 +#define PCI_DEVICE_ID_INTEL_CFL_S_GT2_1 0x3e92 +#define PCI_DEVICE_ID_INTEL_CFL_S_GT2_2 0x3e98 +#define PCI_DEVICE_ID_INTEL_CFL_S_GT2_3 0x3e9a +#define PCI_DEVICE_ID_INTEL_CFL_S_GT2_4 0x3e91 +#define PCI_DEVICE_ID_INTEL_ICL_GT0_ULT 0x8A70 #define PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT 0x8A71 -#define PCI_DEVICE_ID_INTEL_ICL_GT1_ULT 0x8A40 +#define PCI_DEVICE_ID_INTEL_ICL_GT1_ULT 0x8A40 #define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_0 0x8A50 #define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_1 0x8A5D #define PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_1 0x8A5B @@ -3059,7 +3075,7 @@ #define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_5 0x8A55 #define PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_5 0x8A56 #define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_6 0x8A57 -#define PCI_DEVICE_ID_INTEL_ICL_GT3_ULT 0x8A62 +#define PCI_DEVICE_ID_INTEL_ICL_GT3_ULT 0x8A62 #define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1 0x9B21 #define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2 0x9B2A #define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1 0x9B41 @@ -3080,43 +3096,47 @@ #define PCI_DEVICE_ID_INTEL_CML_GT2_H_2 0x9B42 /* Intel Northbridge Ids */ -#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 -#define PCI_DEVICE_ID_INTEL_GLK_NB 0x31f0 -#define PCI_DEVICE_ID_INTEL_SKL_ID_U 0x1904 -#define PCI_DEVICE_ID_INTEL_SKL_ID_Y 0x190c -#define PCI_DEVICE_ID_INTEL_SKL_ID_ULX 0x1924 -#define PCI_DEVICE_ID_INTEL_SKL_ID_H_2 0x1900 -#define PCI_DEVICE_ID_INTEL_SKL_ID_H 0x1910 -#define PCI_DEVICE_ID_INTEL_SKL_ID_S_2 0x190f -#define PCI_DEVICE_ID_INTEL_SKL_ID_S_4 0x191f -#define PCI_DEVICE_ID_INTEL_KBL_ID_S 0x590f -#define PCI_DEVICE_ID_INTEL_SKL_ID_H_EM 0x1918 -#define PCI_DEVICE_ID_INTEL_SKL_ID_DT 0x191f -#define PCI_DEVICE_ID_INTEL_KBL_ID_U 0x5904 -#define PCI_DEVICE_ID_INTEL_KBL_ID_Y 0x590c -#define PCI_DEVICE_ID_INTEL_KBL_ID_H 0x5910 -#define PCI_DEVICE_ID_INTEL_KBL_U_R 0x5914 -#define PCI_DEVICE_ID_INTEL_KBL_ID_DT_2 0x5918 -#define PCI_DEVICE_ID_INTEL_KBL_ID_DT 0x591f -#define PCI_DEVICE_ID_INTEL_CNL_ID_U 0x5A04 -#define PCI_DEVICE_ID_INTEL_CNL_ID_Y 0x5A02 -#define PCI_DEVICE_ID_INTEL_WHL_ID_Wx4 0x3E34 -#define PCI_DEVICE_ID_INTEL_WHL_ID_Wx2 0x3E35 -#define PCI_DEVICE_ID_INTEL_CFL_ID_U 0x3ED0 -#define PCI_DEVICE_ID_INTEL_CFL_ID_H 0x3ec4 -#define PCI_DEVICE_ID_INTEL_CFL_ID_S 0x3ec2 -#define PCI_DEVICE_ID_INTEL_ICL_ID_U 0x8A12 +#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 +#define PCI_DEVICE_ID_INTEL_GLK_NB 0x31f0 +#define PCI_DEVICE_ID_INTEL_SKL_ID_U 0x1904 +#define PCI_DEVICE_ID_INTEL_SKL_ID_Y 0x190c +#define PCI_DEVICE_ID_INTEL_SKL_ID_ULX 0x1924 +#define PCI_DEVICE_ID_INTEL_SKL_ID_H_2 0x1900 +#define PCI_DEVICE_ID_INTEL_SKL_ID_H 0x1910 +#define PCI_DEVICE_ID_INTEL_SKL_ID_S_2 0x190f +#define PCI_DEVICE_ID_INTEL_SKL_ID_S_4 0x191f +#define PCI_DEVICE_ID_INTEL_KBL_ID_S 0x590f +#define PCI_DEVICE_ID_INTEL_SKL_ID_H_EM 0x1918 +#define PCI_DEVICE_ID_INTEL_SKL_ID_DT 0x191f +#define PCI_DEVICE_ID_INTEL_KBL_ID_U 0x5904 +#define PCI_DEVICE_ID_INTEL_KBL_ID_Y 0x590c +#define PCI_DEVICE_ID_INTEL_KBL_ID_H 0x5910 +#define PCI_DEVICE_ID_INTEL_KBL_U_R 0x5914 +#define PCI_DEVICE_ID_INTEL_KBL_ID_DT_2 0x5918 +#define PCI_DEVICE_ID_INTEL_KBL_ID_DT 0x591f +#define PCI_DEVICE_ID_INTEL_CNL_ID_U 0x5A04 +#define PCI_DEVICE_ID_INTEL_CNL_ID_Y 0x5A02 +#define PCI_DEVICE_ID_INTEL_WHL_ID_W_4 0x3E34 +#define PCI_DEVICE_ID_INTEL_WHL_ID_W_2 0x3E35 +#define PCI_DEVICE_ID_INTEL_CFL_ID_U 0x3ED0 +#define PCI_DEVICE_ID_INTEL_CFL_ID_H 0x3ec4 +#define PCI_DEVICE_ID_INTEL_CFL_ID_H_8 0x3e20 +#define PCI_DEVICE_ID_INTEL_CFL_ID_S 0x3ec2 +#define PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4 0x3e1f +#define PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8 0x3e30 +#define PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8 0x3e31 +#define PCI_DEVICE_ID_INTEL_ICL_ID_U 0x8A12 #define PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2 0x8A02 -#define PCI_DEVICE_ID_INTEL_ICL_ID_Y 0x8A10 -#define PCI_DEVICE_ID_INTEL_ICL_ID_Y_2 0x8A00 -#define PCI_DEVICE_ID_INTEL_CML_ULT 0x9B61 -#define PCI_DEVICE_ID_INTEL_CML_ULT_2_2 0x9B71 -#define PCI_DEVICE_ID_INTEL_CML_ULT_6_2 0x9B51 -#define PCI_DEVICE_ID_INTEL_CML_ULX 0x9B60 -#define PCI_DEVICE_ID_INTEL_CML_S 0x9B55 -#define PCI_DEVICE_ID_INTEL_CML_S_10_2 0x9B35 -#define PCI_DEVICE_ID_INTEL_CML_H 0x9B54 -#define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44 +#define PCI_DEVICE_ID_INTEL_ICL_ID_Y 0x8A10 +#define PCI_DEVICE_ID_INTEL_ICL_ID_Y_2 0x8A00 +#define PCI_DEVICE_ID_INTEL_CML_ULT 0x9B61 +#define PCI_DEVICE_ID_INTEL_CML_ULT_2_2 0x9B71 +#define PCI_DEVICE_ID_INTEL_CML_ULT_6_2 0x9B51 +#define PCI_DEVICE_ID_INTEL_CML_ULX 0x9B60 +#define PCI_DEVICE_ID_INTEL_CML_S 0x9B55 +#define PCI_DEVICE_ID_INTEL_CML_S_10_2 0x9B35 +#define PCI_DEVICE_ID_INTEL_CML_H 0x9B54 +#define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44 /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 9a9c575e3c..5cc803c737 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -23,22 +23,7 @@ #include #include -#ifdef __SIMPLE_DEVICE__ - -/* Avoid name collisions as different stages have different signature - * for these functions. The _s_ stands for simple, fundamental IO or - * MMIO variant. - */ -#define pci_read_config8 pci_s_read_config8 -#define pci_read_config16 pci_s_read_config16 -#define pci_read_config32 pci_s_read_config32 -#define pci_write_config8 pci_s_write_config8 -#define pci_write_config16 pci_s_write_config16 -#define pci_write_config32 pci_s_write_config32 -#else - -#include - +#ifndef __ROMCC__ void __noreturn pcidev_die(void); static __always_inline pci_devfn_t pcidev_bdf(const struct device *dev) @@ -52,6 +37,21 @@ static __always_inline pci_devfn_t pcidev_assert(const struct device *dev) pcidev_die(); return pcidev_bdf(dev); } +#endif + +#ifdef __SIMPLE_DEVICE__ + +/* Avoid name collisions as different stages have different signature + * for these functions. The _s_ stands for simple, fundamental IO or + * MMIO variant. + */ +#define pci_read_config8 pci_s_read_config8 +#define pci_read_config16 pci_s_read_config16 +#define pci_read_config32 pci_s_read_config32 +#define pci_write_config8 pci_s_write_config8 +#define pci_write_config16 pci_s_write_config16 +#define pci_write_config32 pci_s_write_config32 +#else static __always_inline u8 pci_read_config8(const struct device *dev, u16 reg) diff --git a/src/include/device/resource.h b/src/include/device/resource.h index eefaf96e28..1d04e9a1c8 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -62,9 +62,11 @@ struct resource { struct device; struct bus; extern void compact_resources(struct device *dev); -extern struct resource *probe_resource(struct device *dev, unsigned int index); +extern struct resource *probe_resource(const struct device *dev, + unsigned int index); extern struct resource *new_resource(struct device *dev, unsigned int index); -extern struct resource *find_resource(struct device *dev, unsigned int index); +extern struct resource *find_resource(const struct device *dev, + unsigned int index); extern resource_t resource_end(struct resource *resource); extern resource_t resource_max(struct resource *resource); extern void report_resource_stored(struct device *dev, diff --git a/src/include/edid.h b/src/include/edid.h index d567115744..e5f7d98926 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -17,6 +17,7 @@ #define EDID_H #include +#include "commonlib/coreboot_tables.h" enum edid_modes { EDID_MODE_640x480_60Hz, @@ -107,6 +108,7 @@ int decode_edid(unsigned char *edid, int size, struct edid *out); void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp, int row_byte_alignment); void set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr); +void set_vbe_framebuffer_orientation(enum lb_fb_orientation orientation); int set_display_mode(struct edid *edid, enum edid_modes mode); #endif /* EDID_H */ diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 5ac74bf238..6dec1920b8 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -38,6 +38,7 @@ enum prog_type { PROG_BL31, PROG_BL32, PROG_POSTCAR, + PROG_OPENSBI, }; /* diff --git a/src/include/ramdetect.h b/src/include/ramdetect.h new file mode 100644 index 0000000000..b63cdf14cf --- /dev/null +++ b/src/include/ramdetect.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Probe an area if it's read/writable. + * Primary use case is the detection of DRAM amount on emulators. + * + * @param dram_start Physical address of DRAM start + * @param probe_size Maximum size in MiB to probe for + * @return The detected DRAM size in MiB + */ +size_t probe_ramsize(const uintptr_t dram_start, const size_t probe_size); diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index d0f957f1f9..ffd3d2d008 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -16,6 +16,14 @@ #ifndef _SPI_GENERIC_H_ #define _SPI_GENERIC_H_ +/* Common parameters -- kind of high, but they should only occur when there + * is a problem (and well your system already is broken), so err on the side + * of caution in case we're dealing with slower SPI buses and/or processors. + */ +#define SPI_FLASH_PROG_TIMEOUT_MS 200 +#define SPI_FLASH_PAGE_ERASE_TIMEOUT_MS 500 +#define SPI_FLASH_SECTOR_ERASE_TIMEOUT_MS 1000 + #include #include #include diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h index 192cfb9014..3c7d9face0 100644 --- a/src/include/stage_cache.h +++ b/src/include/stage_cache.h @@ -32,21 +32,25 @@ enum { STAGE_S3_DATA, }; -#if CONFIG(CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) \ - || CONFIG(RELOCATABLE_RAMSTAGE) +#if CONFIG(TSEG_STAGE_CACHE) || CONFIG(CBMEM_STAGE_CACHE) /* Cache the loaded stage provided according to the parameters. */ void stage_cache_add(int stage_id, const struct prog *stage); /* Load the cached stage at given location returning the stage entry point. */ void stage_cache_load_stage(int stage_id, struct prog *stage); -#else /* CONFIG_NO_STAGE_CACHE */ -static inline void stage_cache_add(int stage_id, const struct prog *stage) {} -static inline void stage_cache_load_stage(int stage_id, struct prog *stage) {} -#endif - /* Cache non-specific data or code. */ void stage_cache_add_raw(int stage_id, const void *base, const size_t size); /* Get a pointer to cached raw data and its size. */ void stage_cache_get_raw(int stage_id, void **base, size_t *size); + +#else /* CONFIG_NO_STAGE_CACHE */ + +static inline void stage_cache_add(int stage_id, const struct prog *stage) {} +static inline void stage_cache_load_stage(int stage_id, struct prog *stage) {} +static inline void stage_cache_add_raw(int stage_id, const void *base, const size_t size) {} +static inline void stage_cache_get_raw(int stage_id, void **base, size_t *size) {} + +#endif + /* Fill in parameters for the external stage cache, if utilized. */ void stage_cache_external_region(void **base, size_t *size); diff --git a/src/include/symbols.h b/src/include/symbols.h index b67286ac2d..cc27275f88 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -56,6 +56,7 @@ DECLARE_REGION(dma_coherent) DECLARE_REGION(soc_registers) DECLARE_REGION(framebuffer) DECLARE_REGION(pdpt) +DECLARE_REGION(opensbi) DECLARE_REGION(bl31) /* diff --git a/src/include/vbe.h b/src/include/vbe.h index 2c40d0507e..cfae7e4025 100644 --- a/src/include/vbe.h +++ b/src/include/vbe.h @@ -34,18 +34,6 @@ typedef struct { u8 color_depth; } __packed screen_info_input_t; -// these structs only store a subset of the VBE defined fields -// only those needed. -typedef struct { - char signature[4]; - u16 version; - u8 *oem_string_ptr; - u32 capabilities; - u16 video_mode_list[256]; // lets hope we never have more than - // 256 video modes... - u16 total_memory; -} vbe_info_t; - typedef struct { u16 mode_attributes; // 00 u8 win_a_attributes; // 02 @@ -114,4 +102,10 @@ typedef struct { void vbe_set_graphics(void); void vbe_textmode_console(void); +/** + * Returns the mode_info struct from the vbe context, + * if initialized. NULL on invalid mode_infos. + */ +const vbe_mode_info_t *vbe_mode_info(void); + #endif // VBE_H diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index f0738eef4e..e5678ffdf1 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -32,10 +32,7 @@ decompressor-y += memcmp.c decompressor-y += prog_ops.c decompressor-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c -ifneq ($(CONFIG_BOOTBLOCK_CUSTOM),y) bootblock-y += bootblock.c -endif - bootblock-y += prog_loaders.c bootblock-y += prog_ops.c bootblock-y += cbfs.c @@ -60,6 +57,7 @@ verstage-y += halt.c verstage-y += fmap.c verstage-y += libgcc.c verstage-y += memcmp.c +verstage-y += string.c verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c verstage-y += boot_device.c verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c @@ -67,6 +65,7 @@ verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c verstage-$(CONFIG_GENERIC_UDELAY) += timer.c verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c +romstage-$(CONFIG_VENDOR_EMULATION) += ramdetect.c romstage-y += prog_loaders.c romstage-y += prog_ops.c romstage-y += memchr.c @@ -107,6 +106,7 @@ endif romstage-$(CONFIG_GENERIC_UDELAY) += timer.c +ramstage-$(CONFIG_VENDOR_EMULATION) += ramdetect.c ramstage-y += prog_loaders.c ramstage-y += prog_ops.c ramstage-y += hardwaremain.c @@ -127,6 +127,7 @@ ramstage-y += stack.c ramstage-y += hexstrtobin.c ramstage-y += wrdd.c ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c +ramstage-$(CONFIG_BOOTSPLASH) += bootsplash.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c postcar-$(CONFIG_TRACE) += trace.c @@ -156,6 +157,7 @@ ramstage-y += cbmem_common.c ramstage-y += imd_cbmem.c ramstage-y += imd.c +postcar-$(CONFIG_VENDOR_EMULATION) += ramdetect.c postcar-y += cbmem_common.c postcar-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c postcar-y += imd_cbmem.c @@ -174,16 +176,13 @@ verstage-$(CONFIG_REG_SCRIPT) += reg_script.c romstage-$(CONFIG_REG_SCRIPT) += reg_script.c ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c -ifeq ($(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM),y) -ramstage-y += ext_stage_cache.c -romstage-y += ext_stage_cache.c -postcar-y += ext_stage_cache.c -else -ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c -romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c -postcar-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c -endif +ramstage-$(CONFIG_TSEG_STAGE_CACHE) += ext_stage_cache.c +romstage-$(CONFIG_TSEG_STAGE_CACHE) += ext_stage_cache.c +postcar-$(CONFIG_TSEG_STAGE_CACHE) += ext_stage_cache.c +ramstage-$(CONFIG_CBMEM_STAGE_CACHE) += cbmem_stage_cache.c +romstage-$(CONFIG_CBMEM_STAGE_CACHE) += cbmem_stage_cache.c +postcar-$(CONFIG_CBMEM_STAGE_CACHE) += cbmem_stage_cache.c romstage-y += boot_device.c ramstage-y += boot_device.c diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c index 01ad3e841b..45f7fe261d 100644 --- a/src/lib/bootmem.c +++ b/src/lib/bootmem.c @@ -59,6 +59,8 @@ static uint32_t bootmem_to_lb_tag(const enum bootmem_type tag) return LB_MEM_UNUSABLE; case BM_MEM_VENDOR_RSVD: return LB_MEM_VENDOR_RSVD; + case BM_MEM_OPENSBI: + return LB_MEM_RESERVED; case BM_MEM_BL31: return LB_MEM_RESERVED; case BM_MEM_TABLE: @@ -147,6 +149,7 @@ static const struct range_strings type_strings[] = { { BM_MEM_UNUSABLE, "UNUSABLE" }, { BM_MEM_VENDOR_RSVD, "VENDOR RESERVED" }, { BM_MEM_BL31, "BL31" }, + { BM_MEM_OPENSBI, "OPENSBI" }, { BM_MEM_TABLE, "CONFIGURATION TABLES" }, { BM_MEM_RAMSTAGE, "RAMSTAGE" }, { BM_MEM_PAYLOAD, "PAYLOAD" }, diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 083fd9d49d..2465966b3a 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -2,7 +2,6 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2019 Intel Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -34,7 +33,8 @@ void gfx_set_init_done(int done) int display_init_required(void) { - if (CONFIG(VBOOT_MAY_SKIP_DISPLAY_INIT)) { + /* For vboot, always honor VBOOT_WD_FLAG_DISPLAY_INIT. */ + if (CONFIG(VBOOT)) { /* Must always select MUST_REQUEST_DISPLAY when using this function. */ if (!CONFIG(VBOOT_MUST_REQUEST_DISPLAY)) diff --git a/src/lib/bootsplash.c b/src/lib/bootsplash.c new file mode 100644 index 0000000000..5527b233f5 --- /dev/null +++ b/src/lib/bootsplash.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Johanna Schander + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include "jpeg.h" + +void set_vesa_bootsplash(void) +{ + const vbe_mode_info_t *mode_info = vbe_mode_info(); + if (mode_info != NULL) { + printk(BIOS_INFO, "Setting up bootsplash\n"); + unsigned int x_resolution = le16_to_cpu(mode_info->vesa.x_resolution); + unsigned int y_resolution = le16_to_cpu(mode_info->vesa.y_resolution); + unsigned int fb_resolution = mode_info->vesa.bits_per_pixel; + unsigned char *framebuffer = + (unsigned char *)le32_to_cpu(mode_info->vesa.phys_base_ptr); + + set_bootsplash(framebuffer, x_resolution, y_resolution, fb_resolution); + } else { + printk(BIOS_ERR, "VBE modeinfo invalid\n"); + } +} + + +void set_bootsplash(unsigned char *framebuffer, unsigned int x_resolution, + unsigned int y_resolution, unsigned int fb_resolution) +{ + struct jpeg_decdata *decdata; + unsigned char *jpeg = + cbfs_boot_map_with_leak("bootsplash.jpg", CBFS_TYPE_BOOTSPLASH, NULL); + if (!jpeg) { + printk(BIOS_ERR, "Could not find bootsplash.jpg\n"); + return; + } + + decdata = malloc(sizeof(*decdata)); + int ret = jpeg_decode(jpeg, framebuffer, x_resolution, y_resolution, fb_resolution, + decdata); + if (ret != 0) { + printk(BIOS_ERR, "Bootsplash could not be decoded. jpeg_decode returned %d.\n", + ret); + return; + } + printk(BIOS_INFO, "Bootsplash loaded\n"); +} diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index df756983d0..95c2ae6e24 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -209,22 +209,6 @@ static void lb_vbnv(struct lb_header *header) } #endif /* CONFIG_CHROMEOS */ -static void lb_vboot_handoff(struct lb_header *header) -{ - void *addr; - uint32_t size; - struct lb_range *vbho; - - if (vboot_get_handoff_info(&addr, &size)) - return; - - vbho = (struct lb_range *)lb_new_record(header); - vbho->tag = LB_TAG_VBOOT_HANDOFF; - vbho->size = sizeof(*vbho); - vbho->range_start = (intptr_t)addr; - vbho->range_size = size; -} - static void lb_vboot_workbuf(struct lb_header *header) { struct lb_range *vbwb; @@ -563,9 +547,6 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) #endif if (CONFIG(VBOOT)) { - /* pass along the vboot_handoff address. */ - lb_vboot_handoff(head); - /* pass along the vboot workbuf address. */ lb_vboot_workbuf(head); } diff --git a/src/lib/edid.c b/src/lib/edid.c index e2f213c5b0..3b81b5c30a 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -1207,14 +1207,16 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) switch (edid[0x13]) { case 4: c.claims_one_point_four = 1; + /* fall through */ case 3: c.claims_one_point_three = 1; + /* fall through */ case 2: c.claims_one_point_two = 1; + /* fall through */ default: - break; + c.claims_one_point_oh = 1; } - c.claims_one_point_oh = 1; } /* display section */ diff --git a/src/lib/edid_fill_fb.c b/src/lib/edid_fill_fb.c index 210c727224..1b38ead596 100644 --- a/src/lib/edid_fill_fb.c +++ b/src/lib/edid_fill_fb.c @@ -81,6 +81,11 @@ void set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr) fb_valid = 1; } +void set_vbe_framebuffer_orientation(enum lb_fb_orientation orientation) +{ + edid_fb.orientation = orientation; +} + int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) { if (!fb_valid) diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c index a4d370540e..1b6c9860f0 100644 --- a/src/lib/fit_payload.c +++ b/src/lib/fit_payload.c @@ -51,6 +51,11 @@ static bool extract(struct region *region, struct fit_image_node *node) const char *comp_name; size_t true_size = 0; + if (node->size == 0) { + printk(BIOS_ERR, "ERROR: The %s size is 0\n", node->name); + return true; + } + switch (node->compression) { case CBFS_COMPRESS_NONE: comp_name = "Relocating uncompressed"; diff --git a/src/lib/hexdump.c b/src/lib/hexdump.c index 1e689e3e53..2c9e483d1d 100644 --- a/src/lib/hexdump.c +++ b/src/lib/hexdump.c @@ -19,14 +19,13 @@ void hexdump(const void *memory, size_t length) { - int i; + size_t i, j; uint8_t *line; int all_zero = 0; int all_one = 0; size_t num_bytes; for (i = 0; i < length; i += 16) { - int j; num_bytes = MIN(length - i, 16); line = ((uint8_t *)memory) + i; @@ -65,7 +64,7 @@ void hexdump(const void *memory, size_t length) void hexdump32(char LEVEL, const void *d, size_t len) { - int count = 0; + size_t count = 0; while (len > 0) { if (count % 8 == 0) { diff --git a/src/lib/ramdetect.c b/src/lib/ramdetect.c new file mode 100644 index 0000000000..5416a580dd --- /dev/null +++ b/src/lib/ramdetect.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#define OVERLAP(a, b, s, e) ((b) > (s) && (a) < (e)) + +static int probe_mb(const uintptr_t dram_start, const uintptr_t size) +{ + uintptr_t addr = dram_start + (size * MiB) - sizeof(uint32_t); + static const uint32_t patterns[] = { + 0x55aa55aa, + 0x12345678 + }; + void *ptr = (void *) addr; + size_t i; + + /* Don't accidentally clober oneself. */ + if (OVERLAP(addr, addr + sizeof(uint32_t), (uintptr_t)_program, (uintptr_t) _eprogram)) + return 1; + + uint32_t old = read32(ptr); + for (i = 0; i < ARRAY_SIZE(patterns); i++) { + write32(ptr, patterns[i]); + if (read32(ptr) != patterns[i]) + break; + } + + write32(ptr, old); + return i == ARRAY_SIZE(patterns); +} + +/* - 20 as probe_size is in MiB, - 1 as i is signed */ +#define MAX_ADDRESSABLE_SPACE (sizeof(size_t) * 8 - 20 - 1) + +/* Probe an area if it's read/writable. */ +size_t probe_ramsize(const uintptr_t dram_start, const size_t probe_size) +{ + ssize_t i; + size_t msb = 0; + size_t discovered = 0; + + static size_t saved_result; + if (saved_result) + return saved_result; + + /* Find the MSB + 1. */ + size_t tmp = probe_size; + do { + msb++; + } while (tmp >>= 1); + + /* Limit search to accessible address space */ + msb = MIN(msb, MAX_ADDRESSABLE_SPACE); + + /* Compact binary search. */ + for (i = msb; i >= 0; i--) + if (probe_mb(dram_start, (discovered | (1ULL << i)))) + discovered |= (1ULL << i); + + saved_result = discovered; + printk(BIOS_DEBUG, "RAMDETECT: Found %zu MiB RAM\n", discovered); + return discovered; +} diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index 267ecb15fd..15ec61e717 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -38,7 +38,6 @@ chip northbridge/intel/sandybridge register "gen3_dec" = "0x001c0301" register "gen4_dec" = "0x00fc0701" register "gpi7_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/apple/macbookair4_2/gpio.c b/src/mainboard/apple/macbookair4_2/gpio.c index d92269b0dd..485ca9520d 100644 --- a/src/mainboard/apple/macbookair4_2/gpio.c +++ b/src/mainboard/apple/macbookair4_2/gpio.c @@ -12,7 +12,7 @@ */ #include -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, @@ -47,7 +47,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio31 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -82,7 +82,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio31 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, .gpio1 = GPIO_LEVEL_HIGH, .gpio2 = GPIO_LEVEL_HIGH, @@ -117,7 +117,7 @@ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio31 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set1 pch_gpio_set1_reset = { +static const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio0 = GPIO_RESET_PWROK, .gpio1 = GPIO_RESET_PWROK, .gpio2 = GPIO_RESET_PWROK, @@ -152,7 +152,7 @@ const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio31 = GPIO_RESET_PWROK, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio0 = GPIO_NO_INVERT, .gpio1 = GPIO_INVERT, .gpio2 = GPIO_NO_INVERT, @@ -187,7 +187,7 @@ const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio31 = GPIO_NO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { .gpio0 = GPIO_NO_BLINK, .gpio1 = GPIO_NO_BLINK, .gpio2 = GPIO_NO_BLINK, @@ -222,7 +222,7 @@ const struct pch_gpio_set1 pch_gpio_set1_blink = { .gpio31 = GPIO_NO_BLINK, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, @@ -257,7 +257,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio63 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_OUTPUT, .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_OUTPUT, @@ -292,7 +292,7 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio63 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_LOW, .gpio33 = GPIO_LEVEL_LOW, .gpio34 = GPIO_LEVEL_HIGH, @@ -327,7 +327,7 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio63 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set2 pch_gpio_set2_reset = { +static const struct pch_gpio_set2 pch_gpio_set2_reset = { .gpio32 = GPIO_RESET_PWROK, .gpio33 = GPIO_RESET_PWROK, .gpio34 = GPIO_RESET_PWROK, @@ -362,7 +362,7 @@ const struct pch_gpio_set2 pch_gpio_set2_reset = { .gpio63 = GPIO_RESET_PWROK, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, .gpio65 = GPIO_MODE_GPIO, .gpio66 = GPIO_MODE_GPIO, @@ -377,7 +377,7 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio75 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_INPUT, .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, @@ -392,7 +392,7 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio75 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_LOW, .gpio65 = GPIO_LEVEL_LOW, .gpio66 = GPIO_LEVEL_LOW, @@ -407,7 +407,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio75 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set3 pch_gpio_set3_reset = { +static const struct pch_gpio_set3 pch_gpio_set3_reset = { .gpio64 = GPIO_RESET_PWROK, .gpio65 = GPIO_RESET_PWROK, .gpio66 = GPIO_RESET_PWROK, diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 9eba6fca82..32438a102f 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -58,7 +58,6 @@ chip northbridge/intel/sandybridge register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0241" register "gen3_dec" = "0x000c0251" - register "p_cnt_throttling_supported" = "0" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "0" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index 4b80f393f6..0c25d4d91a 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -40,7 +40,6 @@ chip northbridge/intel/sandybridge chip southbridge/intel/bd82x6x register "c2_latency" = "101" register "gen1_dec" = "0x00000295" # Super I/O HWM - register "p_cnt_throttling_supported" = "1" register "sata_port_map" = "0x3f" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index de63da2a5d..972dc5dc1f 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -50,7 +50,6 @@ chip northbridge/intel/i945 register "gpe0_en" = "0" - register "ide_legacy_combined" = "0x0" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" diff --git a/src/mainboard/asus/p5gc-mx/gpio.c b/src/mainboard/asus/p5gc-mx/gpio.c index 55c2b3f0dc..d225ba00c5 100644 --- a/src/mainboard/asus/p5gc-mx/gpio.c +++ b/src/mainboard/asus/p5gc-mx/gpio.c @@ -15,7 +15,7 @@ #include -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio6 = GPIO_MODE_GPIO, .gpio7 = GPIO_MODE_GPIO, @@ -39,7 +39,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio28 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_OUTPUT, .gpio6 = GPIO_DIR_INPUT, .gpio7 = GPIO_DIR_INPUT, @@ -63,7 +63,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio28 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_LOW, .gpio11 = GPIO_LEVEL_HIGH, .gpio16 = GPIO_LEVEL_LOW, @@ -76,15 +76,15 @@ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio28 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio13 = GPIO_INVERT, .gpio14 = GPIO_INVERT, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_NATIVE, .gpio34 = GPIO_MODE_NATIVE, @@ -95,7 +95,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio39 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_OUTPUT, .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_OUTPUT, @@ -106,7 +106,7 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio39 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_HIGH, .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_LOW, diff --git a/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c b/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c index 0c191353b1..90fd9e4265 100644 --- a/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c +++ b/src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c @@ -15,7 +15,7 @@ #include -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_NATIVE, .gpio2 = GPIO_MODE_NATIVE, @@ -50,7 +50,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio31 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_OUTPUT, @@ -85,7 +85,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio31 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, .gpio6 = GPIO_LEVEL_HIGH, .gpio7 = GPIO_LEVEL_LOW, @@ -108,12 +108,12 @@ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio28 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio10 = GPIO_INVERT, .gpio13 = GPIO_INVERT, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_GPIO, .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, @@ -124,7 +124,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio39 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_OUTPUT, .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_OUTPUT, @@ -135,7 +135,7 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio39 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_HIGH, .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_LOW, diff --git a/src/mainboard/asus/p8h61-m_lx/devicetree.cb b/src/mainboard/asus/p8h61-m_lx/devicetree.cb index ef8071fabb..27705b91f7 100644 --- a/src/mainboard/asus/p8h61-m_lx/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_lx/devicetree.cb @@ -40,7 +40,6 @@ chip northbridge/intel/sandybridge chip southbridge/intel/bd82x6x register "c2_latency" = "101" register "gen1_dec" = "0x00000295" # Super I/O HWM - register "p_cnt_throttling_supported" = "1" register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index d3f1795f91..e791d70976 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -34,7 +34,6 @@ chip northbridge/intel/sandybridge register "c2_latency" = "0x0065" register "docking_supported" = "0" register "gen1_dec" = "0x000c0291" # HWM - register "p_cnt_throttling_supported" = "0" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" diff --git a/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc b/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc index be35511cff..72736255f8 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc +++ b/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc @@ -29,10 +29,10 @@ verstage-y += memlayout.ld MB_DIR = src/mainboard/$(MAINBOARDDIR) LINUX_DTB = sff8104-linux.dtb -build/$(LINUX_DTB): +$(obj)/$(LINUX_DTB): # FIXME: why isn't this producing the correct size DTB? - dtc -p 4096 -I dts -O dtb -o build/$(LINUX_DTB) -i $(MB_DIR) $(MB_DIR)/$(patsubst %.dtb,%.dts,$(LINUX_DTB)) + dtc -p 4096 -I dts -O dtb -o $(obj)/$(LINUX_DTB) -i $(MB_DIR) $(MB_DIR)/$(patsubst %.dtb,%.dts,$(LINUX_DTB)) cbfs-files-y += $(LINUX_DTB) -$(LINUX_DTB)-file := build/$(LINUX_DTB) +$(LINUX_DTB)-file := $(obj)/$(LINUX_DTB) $(LINUX_DTB)-type := raw diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index a6bcb1d7aa..6fa9e8357d 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -48,7 +48,6 @@ chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did register "gen3_dec" = "0x000406f1" register "gen4_dec" = "0x000c06a1" register "gpi7_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/cubietech/Kconfig b/src/mainboard/cubietech/Kconfig deleted file mode 100644 index c0e9cc1357..0000000000 --- a/src/mainboard/cubietech/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -if VENDOR_CUBIETECH - -# Auto select common options -choice - prompt "Mainboard model" - -source "src/mainboard/cubietech/*/Kconfig.name" - -endchoice - -source "src/mainboard/cubietech/*/Kconfig" - -config MAINBOARD_VENDOR - string - default "Cubietech" - -endif # VENDOR_CUBIETECH diff --git a/src/mainboard/cubietech/Kconfig.name b/src/mainboard/cubietech/Kconfig.name deleted file mode 100644 index 0ebc0885be..0000000000 --- a/src/mainboard/cubietech/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config VENDOR_CUBIETECH - bool "Cubietech" diff --git a/src/mainboard/cubietech/cubieboard/Kconfig b/src/mainboard/cubietech/cubieboard/Kconfig deleted file mode 100644 index 9ef5797044..0000000000 --- a/src/mainboard/cubietech/cubieboard/Kconfig +++ /dev/null @@ -1,30 +0,0 @@ -if BOARD_CUBIETECH_CUBIEBOARD - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_ALLWINNER_A10 - select BOARD_ROMSIZE_KB_4096 - select DRIVER_XPOWERS_AXP209 - select MISSING_BOARD_RESET - -config MAINBOARD_DIR - string - default cubietech/cubieboard - -config MAINBOARD_PART_NUMBER - string - default "Cubieboard A10" - -config MAX_CPUS - int - default 1 - -config DRAM_SIZE_MB - int - default 1024 - -config UART_FOR_CONSOLE - int - default 0 - -endif # BOARD_CUBIETECH_CUBIEBOARD diff --git a/src/mainboard/cubietech/cubieboard/Kconfig.name b/src/mainboard/cubietech/cubieboard/Kconfig.name deleted file mode 100644 index 3a011819b4..0000000000 --- a/src/mainboard/cubietech/cubieboard/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_CUBIETECH_CUBIEBOARD - bool "Cubieboard" diff --git a/src/mainboard/cubietech/cubieboard/Makefile.inc b/src/mainboard/cubietech/cubieboard/Makefile.inc deleted file mode 100644 index f3a6de237d..0000000000 --- a/src/mainboard/cubietech/cubieboard/Makefile.inc +++ /dev/null @@ -1,6 +0,0 @@ -bootblock-y += bootblock.c -romstage-y += romstage.c - -bootblock-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld diff --git a/src/mainboard/cubietech/cubieboard/board_info.txt b/src/mainboard/cubietech/cubieboard/board_info.txt deleted file mode 100644 index c67b641a94..0000000000 --- a/src/mainboard/cubietech/cubieboard/board_info.txt +++ /dev/null @@ -1 +0,0 @@ -Category: sbc diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c deleted file mode 100644 index 05e3847d39..0000000000 --- a/src/mainboard/cubietech/cubieboard/bootblock.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Minimal bootblock for Cubieboard - * It sets up CPU clock, and enables the bootblock console. - */ - -#include -#include -#include -#include -#include -#include -#include - -#define CPU_AHB_APB0_DEFAULT \ - CPU_CLK_SRC_OSC24M \ - | APB0_DIV_1 \ - | AHB_DIV_2 \ - | AXI_DIV_1 - -#define GPH_STATUS_LEDS (1 << 20) | (1 << 21) -#define GPH_LED1_PIN_NO 21 -#define GPH_LED2_PIN_NO 20 - -#define GPB_UART0_FUNC 2 -#define GPB_UART0_PINS ((1 << 22) | (1 << 23)) - -#define GPF_SD0_FUNC 2 -#define GPF_SD0_PINS 0x3f /* PF0 thru PF5 */ -#define GPH1_SD0_DET_FUNC 5 - -static void cubieboard_set_sys_clock(void) -{ - u32 reg32; - struct a10_ccm *ccm = (void *)A1X_CCM_BASE; - - /* Switch CPU clock to main oscillator */ - write32(&ccm->cpu_ahb_apb0_cfg, CPU_AHB_APB0_DEFAULT); - - /* Configure the PLL1. The value is the same one used by u-boot - * P = 1, N = 16, K = 1, M = 1 --> Output = 384 MHz - */ - write32(&ccm->pll1_cfg, 0xa1005000); - - /* FIXME: Delay to wait for PLL to lock */ - u32 wait = 1000; - while (--wait); - - /* Switch CPU to PLL clock */ - reg32 = read32(&ccm->cpu_ahb_apb0_cfg); - reg32 &= ~CPU_CLK_SRC_MASK; - reg32 |= CPU_CLK_SRC_PLL1; - write32(&ccm->cpu_ahb_apb0_cfg, reg32); -} - -static void cubieboard_setup_clocks(void) -{ - struct a10_ccm *ccm = (void *)A1X_CCM_BASE; - - cubieboard_set_sys_clock(); - /* Configure the clock source for APB1. This drives our UART */ - write32(&ccm->apb1_clk_div_cfg, - APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0)); - - /* Configure the clock for SD0 */ - write32(&ccm->sd0_clk_cfg, - SDx_CLK_GATE | SDx_CLK_SRC_OSC24M | SDx_RAT_EXP_N(0) | SDx_RAT_M(1)); - - /* Enable clock to SD0 */ - a1x_periph_clock_enable(A1X_CLKEN_MMC0); - -} - -static void cubieboard_setup_gpios(void) -{ - /* Mux Status LED pins */ - gpio_set_multipin_func(GPH, GPH_STATUS_LEDS, GPIO_PIN_FUNC_OUTPUT); - /* Turn on green LED to let user know we're executing coreboot code */ - gpio_set(GPH, GPH_LED2_PIN_NO); - - /* Mux UART pins */ - gpio_set_multipin_func(GPB, GPB_UART0_PINS, GPB_UART0_FUNC); - - /* Mux SD pins */ - gpio_set_multipin_func(GPF, GPF_SD0_PINS, GPF_SD0_FUNC); - gpio_set_pin_func(GPH, 1, GPH1_SD0_DET_FUNC); -} - -static void cubieboard_enable_uart(void) -{ - a1x_periph_clock_enable(A1X_CLKEN_UART0); -} - -static void cubieboard_raminit(void) -{ - struct dram_para dram_para = { - .clock = 480, - .type = 3, - .rank_num = 1, - .density = 4096, - .io_width = 16, - .bus_width = 32, - .cas = 6, - .zq = 123, - .odt_en = 0, - .size = 1024, - .tpr0 = 0x30926692, - .tpr1 = 0x1090, - .tpr2 = 0x1a0c8, - .tpr3 = 0, - .tpr4 = 0, - .tpr5 = 0, - .emr1 = 0, - .emr2 = 0, - .emr3 = 0, - }; - - dramc_init(&dram_para); - - /* FIXME: ram_check does not compile for ARM, - * and we didn't init console yet - */ - ////void *const test_base = (void *)A1X_DRAM_BASE; - ////ram_check((u32)test_base, (u32)test_base + 0x1000); -} - -void bootblock_mainboard_early_init(void) -{ - /* A10 Timer init uses the 24MHz clock, not PLLs, so we can init it very - * early on to get udelay, which is used almost everywhere else. - */ - init_timer(); - - cubieboard_setup_clocks(); - cubieboard_setup_gpios(); - cubieboard_enable_uart(); -} - -void bootblock_mainboard_init(void) -{ - cubieboard_raminit(); -} diff --git a/src/mainboard/cubietech/cubieboard/devicetree.cb b/src/mainboard/cubietech/cubieboard/devicetree.cb deleted file mode 100644 index 033a89e628..0000000000 --- a/src/mainboard/cubietech/cubieboard/devicetree.cb +++ /dev/null @@ -1,12 +0,0 @@ -chip cpu/allwinner/a10 - device cpu_cluster 0 on end - - chip drivers/xpowers/axp209 # AXP209 is on I2C 0 - device i2c 0x34 on end - register "dcdc2_voltage_mv" = "1400" # Vcore - register "dcdc3_voltage_mv" = "1250" # DLL Vdd - register "ldo2_voltage_mv" = "3000" # AVCC - register "ldo3_voltage_mv" = "2800" # NC? - register "ldo4_voltage_mv" = "2800" # CSI1-IO-2V8 - end -end diff --git a/src/mainboard/cubietech/cubieboard/romstage.c b/src/mainboard/cubietech/cubieboard/romstage.c deleted file mode 100644 index bfb5e029d6..0000000000 --- a/src/mainboard/cubietech/cubieboard/romstage.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Basic romstage for Cubieboard - * - * Set up system voltages, then increase the CPU clock, before turning control - * to ramstage. The CPU VDD needs to be properly set before it can run at full - * speed. Setting the CPU at full speed helps lzma-decompress ramstage a lot - * faster. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define GPB_TWI0_FUNC 2 -#define GPB_TWI0_PINS ((1 << 0) | (1 << 1)) - -#define AXP209_BUS 0 - -static enum cb_err cubieboard_setup_power(void) -{ - enum cb_err err; - const struct device * pmu; - const struct drivers_xpowers_axp209_config *cfg; - - /* Find the AXP209 in devicetree */ - pmu = dev_find_slot_on_smbus(AXP209_BUS, AXP209_I2C_ADDR); - if (!pmu) { - printk(BIOS_ERR, "AXP209 not found in devicetree.cb\n"); - return CB_ERR; - } - - cfg = pmu->chip_info; - - /* Mux TWI0 pins */ - gpio_set_multipin_func(GPB, GPB_TWI0_PINS, GPB_TWI0_FUNC); - /* Enable TWI0 */ - a1x_periph_clock_enable(A1X_CLKEN_TWI0); - a1x_twi_init(AXP209_BUS, 400000); - - if ((err = axp209_init(AXP209_BUS)) != CB_SUCCESS) { - printk(BIOS_ERR, "PMU initialization failed\n"); - return err; - } - - if ((err = axp209_set_voltages(AXP209_BUS, cfg)) != CB_SUCCESS) { - printk(BIOS_WARNING, "Power setup incomplete: " - "CPU may hang when increasing clock\n"); - return err; - } - - printk(BIOS_SPEW, "VDD CPU (DCDC2): %imv\n", cfg->dcdc2_voltage_mv); - printk(BIOS_SPEW, "VDD DLL (DCDC3): %imv\n", cfg->dcdc3_voltage_mv); - printk(BIOS_SPEW, "AVCC (LDO2) : %imv\n", cfg->ldo2_voltage_mv); - printk(BIOS_SPEW, "CSI1-IO (LDO4) : %imv\n", cfg->ldo4_voltage_mv); - printk(BIOS_SPEW, "(LDO3) : %imv\n", cfg->ldo3_voltage_mv); - - return CB_SUCCESS; -} - -void main(void) -{ - enum cb_err err; - - console_init(); - - /* Configure power rails */ - err = cubieboard_setup_power(); - - if (err == CB_SUCCESS) { - /* TODO: Get this clock from devicetree.cb */ - a1x_set_cpu_clock(1008); - } else { - /* cubieboard_setup_power() prints more details */ - printk(BIOS_WARNING, "Will run CPU at reduced speed\n"); - a1x_set_cpu_clock(384); - } - - run_ramstage(); -} diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig b/src/mainboard/emulation/qemu-aarch64/Kconfig new file mode 100644 index 0000000000..7d8d7b2f00 --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/Kconfig @@ -0,0 +1,51 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Asami Doi . +# +# SPDX-License-Identifier: GPL-2.0-or-later + +# Emulation for QEMU 2.8 ARM Virtual Machine (alias of virt-2.8) +# https://wiki.qemu.org/Documentation/Platforms/ARM + +if BOARD_EMULATION_QEMU_AARCH64 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARM64_USE_ARCH_TIMER + select BOARD_ROMSIZE_KB_4096 + select BOOTBLOCK_CONSOLE + select BOOTBLOCK_CUSTOM + select BOOT_DEVICE_NOT_SPI_FLASH + select CONSOLE_SERIAL + select DRIVERS_UART_PL011 + select HAVE_LINEAR_FRAMEBUFFER + select MAINBOARD_FORCE_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MISSING_BOARD_RESET + +config MAINBOARD_DIR + string + default emulation/qemu-aarch64 + +config MAINBOARD_PART_NUMBER + string + default "QEMU AArch64" + +config MAX_CPUS + int + default 2 + +config MAINBOARD_VENDOR + string + default "QEMU" + +config DRAM_SIZE_MB + int + default 1024 + +endif # BOARD_EMULATION_QEMU_AARCH64 diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig.name b/src/mainboard/emulation/qemu-aarch64/Kconfig.name new file mode 100644 index 0000000000..8c14fc1907 --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/Kconfig.name @@ -0,0 +1,5 @@ +config BOARD_EMULATION_QEMU_AARCH64 + bool "QEMU AArch64 (virt)" + help + To execute, do: + qemu-system-aarch64 -bios ./build/coreboot.rom -M virt,secure=on,virtualization=on -cpu cortex-a53 -nographic -m 8192M diff --git a/src/mainboard/emulation/qemu-aarch64/Makefile.inc b/src/mainboard/emulation/qemu-aarch64/Makefile.inc new file mode 100644 index 0000000000..38ecdd1a7b --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/Makefile.inc @@ -0,0 +1,25 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Asami Doi +# +# SPDX-License-Identifier: GPL-2.0-or-later + +romstage-y += cbmem.c +ramstage-y += cbmem.c + +bootblock-y += media.c +romstage-y += media.c +ramstage-y += media.c + +bootblock-y += mmio.c +romstage-y += mmio.c +ramstage-y += mmio.c + +bootblock-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld + +bootblock-y += bootblock_custom.S + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/emulation/qemu-aarch64/board_info.txt b/src/mainboard/emulation/qemu-aarch64/board_info.txt new file mode 100644 index 0000000000..92fafa5c8f --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/board_info.txt @@ -0,0 +1,3 @@ +Board name: QEMU AArch64 (virt) +Category: emulation +Board URL: http://wiki.qemu.org/Main_Page diff --git a/src/mainboard/emulation/qemu-aarch64/bootblock_custom.S b/src/mainboard/emulation/qemu-aarch64/bootblock_custom.S new file mode 100644 index 0000000000..f9e85d0efc --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/bootblock_custom.S @@ -0,0 +1,36 @@ +/* + * Early initialization code for aarch64 (a.k.a. armv8) + * + * Copyright 2019 Asami Doi + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include + +ENTRY(_start) + /* Setup CPU. */ + bl arm64_init_cpu + + /* Get code positions. */ + ldr x1, =_flash + ldr x0, =_bootblock + + /* Calculate bootblock size. */ + ldr x2, =_ebootblock + sub x2, x2, x0 + + /* Call memcpy in arch/arm64/memcpy.S */ + bl memcpy + dmb sy + + /* Calculate relocation offset between bootblock in flash and in DRAM. */ + ldr x0, =_flash + ldr x1, =_bootblock + sub x1, x1, x0 + + /* Jump to main() in DRAM. */ + adr x0, main + add x0, x0, x1 + blr x0 +ENDPROC(_start) diff --git a/src/mainboard/emulation/qemu-aarch64/cbmem.c b/src/mainboard/emulation/qemu-aarch64/cbmem.c new file mode 100644 index 0000000000..c50254df29 --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/cbmem.c @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Asami Doi + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include + +void *cbmem_top(void) +{ + return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); +} diff --git a/src/mainboard/emulation/qemu-aarch64/devicetree.cb b/src/mainboard/emulation/qemu-aarch64/devicetree.cb new file mode 100644 index 0000000000..010cae8e91 --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/devicetree.cb @@ -0,0 +1,11 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Asami Doi . +# +# SPDX-License-Identifier: GPL-2.0-or-later + +# This file exists only to avoid a compile error. It needs a devicetree.cb that is not empty. +chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # Fake component for testing +end diff --git a/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h new file mode 100644 index 0000000000..6f0c80257b --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Asami Doi + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +/* + * Memory map for QEMU virt machine since + * a578cdfbdd8f9beff5ced52b7826ddb1669abbbf (June 2019): + * + * 0..128MiB (0x0000_0000..0x0080_0000) is the space for a flash device. + * 128MiB..256MiB (0x0080_0000..0x0100_0000) is used for miscellaneous device I/O. + * 256MiB..1GiB (0x0100_0000..0x4000_0000) is reserved for possible future PCI support. + * 1GiB.. (0x4000_0000) is RAM and the size depends on initial RAM and device memory settings + * + * 0x0000_0000..0x0080_0000: Flash memory + * 0x0900_0000..0x0900_1000: UART (PL011) + * 0x0901_0000..0x0901_1000: RTC (PL031) + * 0x0903_0000..0x0903_1000: GPIO (PL061) + * 0x0904_0000..0x0904_1000: Secure UART (PL011) + * 0x0905_0000..0x0907_0000: SMMU (smmu-v3) + * 0x0a00_0000..0x0a00_0200: MMIO (virtio) + * 0x0c00_0000..0x0e00_0000: Platform bus + * 0x4000_0000..: RAM + */ +#define VIRT_UART_BASE 0x09000000 +#define VIRT_RTC_BASE 0x09010000 +#define VIRT_GPIO_BASE 0x09030000 +#define VIRT_SECURE_UART_BASE 0x09040000 +#define VIRT_SMMU_BASE 0x09050000 +#define VIRT_MMIO_BASE 0x0a000000 +#define VIRT_PLATFORM_BUS_BASE 0x0c000000 diff --git a/src/mainboard/emulation/qemu-aarch64/mainboard.c b/src/mainboard/emulation/qemu-aarch64/mainboard.c new file mode 100644 index 0000000000..573545532a --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/mainboard.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Asami Doi + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include + +static void mainboard_enable(struct device *dev) +{ + int ram_size_mb = probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB); + ram_resource(dev, 0, (uintptr_t)_dram / KiB, ram_size_mb * KiB); +} + +struct chip_operations mainboard_ops = { + .name = "qemu_aarch64", + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/emulation/qemu-aarch64/media.c b/src/mainboard/emulation/qemu-aarch64/media.c new file mode 100644 index 0000000000..03f0eb1bf8 --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/media.c @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Asami Doi + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include + +/* Maps directly to NOR flash up to ROM size. */ +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_RO_INIT((void *)0x0, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} diff --git a/src/mainboard/emulation/qemu-aarch64/memlayout.ld b/src/mainboard/emulation/qemu-aarch64/memlayout.ld new file mode 100644 index 0000000000..0b52d31052 --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/memlayout.ld @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Asami Doi + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include + +/* + * Memory map for QEMU virt machine since + * a578cdfbdd8f9beff5ced52b7826ddb1669abbbf (June 2019): + * + * 0..128MiB (0x0000_0000..0x0080_0000) is the space for a flash device. + * 128MiB..256MiB (0x0080_0000..0x0100_0000) is used for miscellaneous device I/O. + * 256MiB..1GiB (0x0100_0000..0x4000_0000) is reserved for possible future PCI support. + * 1GiB.. (0x4000_0000) is RAM and the size depends on initial RAM and device memory settings. + */ +SECTIONS +{ + REGION(flash, 0x00000000, CONFIG_ROM_SIZE, 8) + + DRAM_START(0x40000000) + BOOTBLOCK(0x60010000, 64K) + STACK(0x60020000, 64K) + ROMSTAGE(0x60030000, 128K) + RAMSTAGE(0x60070000, 16M) + + TTB(0x61100000, 16K) + POSTRAM_CBFS_CACHE(0x61110000, 1M) +} diff --git a/src/mainboard/emulation/qemu-aarch64/mmio.c b/src/mainboard/emulation/qemu-aarch64/mmio.c new file mode 100644 index 0000000000..717d8581d2 --- /dev/null +++ b/src/mainboard/emulation/qemu-aarch64/mmio.c @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Asami Doi . + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include + +uintptr_t uart_platform_base(int idx) +{ + return VIRT_UART_BASE; +} diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index fc770cf27d..73b2d5dede 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -53,4 +53,8 @@ config MAINBOARD_VENDOR string default "ARM Ltd." +config DRAM_SIZE_MB + int + default 1024 + endif # BOARD_EMULATION_QEMU_ARMV7 diff --git a/src/mainboard/emulation/qemu-armv7/cbmem.c b/src/mainboard/emulation/qemu-armv7/cbmem.c index 927bd42d54..542e08d05e 100644 --- a/src/mainboard/emulation/qemu-armv7/cbmem.c +++ b/src/mainboard/emulation/qemu-armv7/cbmem.c @@ -11,55 +11,11 @@ * GNU General Public License for more details. */ -#include #include #include -#include -#include "mainboard.h" - -#define PATTERN1 0x55 -#define PATTERN2 0xaa - -/* Returns 1 if mebibyte mb is present and 0 otherwise. */ -static int probe_mb(int mb) -{ - char *ptr = (char *) 0x60000000 + (mb << 20) + 0xfffff; - char old; - if (ptr < (char *) &_eprogram) { - /* Don't probe below _end to avoid accidentally clobering - oneself. */ - return 1; - } - - old = read8(ptr); - write8(ptr, PATTERN1); - if (read8(ptr) != PATTERN1) - return 0; - write8(ptr, PATTERN2); - if (read8(ptr) != PATTERN2) - return 0; - write8(ptr, old); - return 1; -} - -int probe_ramsize(void) -{ - int i; - int discovered = 0; - static int saved_result; - if (saved_result) - return saved_result; - /* Compact binary search. */ - /* 1 GiB is the largest supported RAM by this machine. */ - for (i = 9; i >= 0; i--) - if (probe_mb(discovered | (1 << i))) - discovered |= (1 << i); - discovered++; - saved_result = discovered; - return discovered; -} +#include void *cbmem_top(void) { - return _dram + (probe_ramsize() << 20); + return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/src/mainboard/emulation/qemu-armv7/mainboard.c b/src/mainboard/emulation/qemu-armv7/mainboard.c index cc14dd8e7b..338cff9321 100644 --- a/src/mainboard/emulation/qemu-armv7/mainboard.c +++ b/src/mainboard/emulation/qemu-armv7/mainboard.c @@ -18,9 +18,10 @@ #include #include #include -#include "mainboard.h" #include #include +#include +#include static void init_gfx(void) { @@ -57,7 +58,7 @@ static void mainboard_enable(struct device *dev) halt(); } - discovered = probe_ramsize(); + discovered = probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB); printk(BIOS_DEBUG, "%d MiB of RAM discovered\n", discovered); ram_resource(dev, 0, 0x60000000 >> 10, discovered << 10); cbmem_recovery(0); diff --git a/src/mainboard/emulation/qemu-armv7/mainboard.h b/src/mainboard/emulation/qemu-armv7/mainboard.h deleted file mode 100644 index 87fa3beee6..0000000000 --- a/src/mainboard/emulation/qemu-armv7/mainboard.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 or, at your option, any later - * version of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef QEMU_ARMV7_MAINBOARD_H -#define QEMU_ARMV7_MAINBOARD_H - -/* Returns RAM size in mebibytes. */ -int probe_ramsize(void); - -#endif diff --git a/src/mainboard/emulation/qemu-power8/Kconfig b/src/mainboard/emulation/qemu-power8/Kconfig index c3a9904986..0496178bd9 100644 --- a/src/mainboard/emulation/qemu-power8/Kconfig +++ b/src/mainboard/emulation/qemu-power8/Kconfig @@ -22,8 +22,10 @@ config BOARD_SPECIFIC_OPTIONS select CPU_QEMU_POWER8 select BOARD_ROMSIZE_KB_4096 select ARCH_BOOTBLOCK_PPC64 + select ARCH_VERSTAGE_PPC64 + select ARCH_ROMSTAGE_PPC64 + select ARCH_RAMSTAGE_PPC64 select HAVE_UART_SPECIAL - select ARCH_PPC64 select BOOT_DEVICE_NOT_SPI_FLASH select MISSING_BOARD_RESET diff --git a/src/mainboard/emulation/qemu-power8/bootblock.c b/src/mainboard/emulation/qemu-power8/bootblock.c index bf918cfa9f..ec30c879f1 100644 --- a/src/mainboard/emulation/qemu-power8/bootblock.c +++ b/src/mainboard/emulation/qemu-power8/bootblock.c @@ -17,10 +17,12 @@ #include #include +void qemu_power8_main(void); + /* The qemu part of all this is very, very non-hardware like. * So it gets its own bootblock. */ -void main(void) +void qemu_power8_main(void) { if (CONFIG(BOOTBLOCK_CONSOLE)) { console_init(); diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index f0f658d0d9..fa6dccc94c 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -40,6 +40,7 @@ config BOARD_SPECIFIC_OPTIONS select BOOT_DEVICE_NOT_SPI_FLASH select MISSING_BOARD_RESET select DRIVERS_UART_8250MEM + select RISCV_HAS_OPENSBI config MAINBOARD_DIR string @@ -57,4 +58,26 @@ config DRAM_SIZE_MB int default 32768 +config OPENSBI_PLATFORM + string + default "qemu/virt" + +# ugly, but CBFS is placed in DRAM... +config OPENSBI_TEXT_START + hex + default 0x80010000 if COREBOOT_ROMSIZE_KB_64 + default 0x80020000 if COREBOOT_ROMSIZE_KB_128 + default 0x80040000 if COREBOOT_ROMSIZE_KB_256 + default 0x80080000 if COREBOOT_ROMSIZE_KB_512 + default 0x80100000 if COREBOOT_ROMSIZE_KB_1024 + default 0x80200000 if COREBOOT_ROMSIZE_KB_2048 + default 0x80400000 if COREBOOT_ROMSIZE_KB_4096 + default 0x80600000 if COREBOOT_ROMSIZE_KB_6144 + default 0x80800000 if COREBOOT_ROMSIZE_KB_8192 + default 0x80a00000 if COREBOOT_ROMSIZE_KB_10240 + default 0x80c00000 if COREBOOT_ROMSIZE_KB_12288 + default 0x81000000 if COREBOOT_ROMSIZE_KB_16384 + default 0x82000000 if COREBOOT_ROMSIZE_KB_32768 + default 0x84000000 if COREBOOT_ROMSIZE_KB_65536 + endif # BOARD_EMULATION_QEMU_RISCV diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c index 4b428aa486..88898087f4 100644 --- a/src/mainboard/emulation/qemu-riscv/mainboard.c +++ b/src/mainboard/emulation/qemu-riscv/mainboard.c @@ -17,15 +17,19 @@ #include #include #include +#include static void mainboard_enable(struct device *dev) { + size_t dram_mb_detected; if (!dev) { die("No dev0; die\n"); } - ram_resource(dev, 0, (uintptr_t)_dram / KiB, CONFIG_DRAM_SIZE_MB * KiB); + dram_mb_detected = probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB); + ram_resource(dev, 0, (uintptr_t)_dram / KiB, dram_mb_detected * MiB / KiB); + cbmem_recovery(0); } diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index 7f8ec3dd6a..b29bc14fa9 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -17,16 +17,26 @@ #include #include -//Stages start after CBFS in DRAM +// Stages start after CBFS in DRAM #define STAGES_START (QEMU_VIRT_DRAM + CONFIG_ROM_SIZE) SECTIONS { - DRAM_START(QEMU_VIRT_DRAM) + // the virt target doesn't emulate flash and just puts the CBFS into DRAM. + // fake SRAM where CBFS resides. It's only done for better integration. + SRAM_START(QEMU_VIRT_DRAM) BOOTBLOCK(QEMU_VIRT_DRAM, 64K) // CBFS goes here - STACK(STAGES_START, 4K) - ROMSTAGE(STAGES_START + 64K, 128K) - PRERAM_CBMEM_CONSOLE(STAGES_START + 192K, 8K) + SRAM_END(STAGES_START) + DRAM_START(STAGES_START) + +#if ENV_ROMSTAGE + ROMSTAGE(STAGES_START, 128K) +#endif +#if ENV_RAMSTAGE + REGION(opensbi, STAGES_START, 128K, 4K) +#endif + PRERAM_CBMEM_CONSOLE(STAGES_START + 128K, 8K) RAMSTAGE(STAGES_START + 200K, 16M) + STACK(STAGES_START + 200K + 16M, 4K) } diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv/rom_media.c index bac19846c5..79e5ca8f54 100644 --- a/src/mainboard/emulation/qemu-riscv/rom_media.c +++ b/src/mainboard/emulation/qemu-riscv/rom_media.c @@ -19,7 +19,7 @@ /* This assumes that the CBFS resides at start of dram, which is true for the * default configuration. */ static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(_dram, CONFIG_ROM_SIZE); + MEM_REGION_DEV_RO_INIT(_sram, CONFIG_ROM_SIZE); const struct region_device *boot_device_ro(void) { diff --git a/src/mainboard/esd/atom15/gpio.c b/src/mainboard/esd/atom15/gpio.c index b9c7829fb1..bc33517d41 100644 --- a/src/mainboard/esd/atom15/gpio.c +++ b/src/mainboard/esd/atom15/gpio.c @@ -155,8 +155,8 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_NC, /* GPIO_S0_SC[089] - No Connect */ GPIO_FUNC1, /* GPIO_S0_SC[090] - EXP_I2C_SDA */ GPIO_FUNC1, /* GPIO_S0_SC[091] - EXP_I2C_SCL */ - GPIO_FUNC1, /* GPIO_S0_SC[092] - 0R GND? */ - GPIO_FUNC1, /* GPIO_S0_SC[093] - 0R GND? */ + GPIO_FUNC1, /* GPIO_S0_SC[092] - 0R GND? */ + GPIO_FUNC1, /* GPIO_S0_SC[093] - 0R GND? */ GPIO_FUNC1, /* GPIO_S0_SC[094] - SOC_PWM0 */ GPIO_FUNC1, /* GPIO_S0_SC[095] - SOC_PWM1 */ GPIO_NC, /* GPIO_S0_SC[096] - No Connect */ @@ -200,7 +200,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[27] - SW450-1 */ GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[28] - SW450-2 */ GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[29] - SW450-3 */ - GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[30] - SW450-4 */ + GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[30] - SW450-4 */ GPIO_NC, /* GPIO_S5[31] - No Connect */ GPIO_NC, /* GPIO_S5[32] - No Connect */ GPIO_NC, /* GPIO_S5[33] - No Connect */ diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index 95d8f6caae..177393e749 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_FSP_BIN select CACHE_MRC_SETTINGS select DISABLE_HPET + select INTEL_GMA_HAVE_VBT select GENERIC_SPD_BIN choice diff --git a/src/mainboard/facebook/fbg1701/data.vbt b/src/mainboard/facebook/fbg1701/data.vbt new file mode 100644 index 0000000000..39eba56e71 Binary files /dev/null and b/src/mainboard/facebook/fbg1701/data.vbt differ diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index 57e2911f63..59c28768d5 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -70,7 +70,7 @@ static long acpi_create_ecdt(acpi_ecdt_t * ecdt) ecdt->gpe_bit = 23; // SCI interrupt within GPEx_STS - strncpy((char *)ecdt->ec_id, ec_id, strlen(ec_id)); + memcpy(ecdt->ec_id, ec_id, sizeof(ec_id)); header->checksum = acpi_checksum((void *) ecdt, ecdt_len); diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index c99455322b..81ee9b17aa 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -19,21 +19,21 @@ chip northbridge/intel/i945 register "gfx.ndid" = "2" register "gfx.did" = "{ 0x80000100, 0x80000410, 0x80000320, 0x80000410, 0x00000005 }" - device cpu_cluster 0 on - chip cpu/intel/socket_m - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/intel/socket_m + device lapic 0 on end + end + end register "pci_mmio_size" = "768" - device domain 0 on - device pci 00.0 on end # host bridge + device domain 0 on + device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port device pci 02.0 on end # vga controller device pci 02.1 on end # display controller - chip southbridge/intel/i82801gx + chip southbridge/intel/i82801gx register "pirqa_routing" = "0x0a" register "pirqb_routing" = "0x0a" register "pirqc_routing" = "0x0a" @@ -54,9 +54,9 @@ chip northbridge/intel/i945 register "gpe0_en" = "0x00800106" register "alt_gp_smi_en" = "0x0100" - register "ide_legacy_combined" = "0x1" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" register "c3_latency" = "85" register "docking_supported" = "1" @@ -81,8 +81,8 @@ chip northbridge/intel/i945 end # PCI bridge device pci 1e.2 off end # AC'97 Audio device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge - chip superio/smsc/fdc37n972 + device pci 1f.0 on # LPC bridge + chip superio/smsc/fdc37n972 device pnp 2e.0 off # Floppy end device pnp 2e.1 off # ACPI PM @@ -93,11 +93,11 @@ chip northbridge/intel/i945 irq 0x70 = 5 end device pnp 2e.4 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 off end - device pnp 2e.5 off - end #device pnp 2e.6 on # RTC # io 0x60 = 0x70 # io 0x62 = 0x74 @@ -109,19 +109,19 @@ chip northbridge/intel/i945 end #device pnp 2e.9 on # Mailbox #end - end - chip superio/smsc/sio10n268 - device pnp 4e.0 off # Floppy + end + chip superio/smsc/sio10n268 + device pnp 4e.0 off # Floppy end device pnp 4e.1 off # Parport end #device pnp 4e.2 on # COM3 - # io 0x60 = 0x3e8 - # irq 0x70 = 6 + # io 0x60 = 0x3e8 + # irq 0x70 = 6 #end #device pnp 4e.3 on # COM4 - # io 0x60 = 0x2e8 - # irq 0x70 = 6 + # io 0x60 = 0x2e8 + # irq 0x70 = 6 #end device pnp 4e.5 on # Keyboard io 0x60 = 0x60 @@ -139,12 +139,12 @@ chip northbridge/intel/i945 end chip ec/acpi end - end + end - end + end device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - end - end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + end + end end diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index 1c69613cbe..f7e8ccc9a6 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -73,7 +73,6 @@ chip northbridge/intel/i945 register "gpe0_en" = "0" - register "ide_legacy_combined" = "0x0" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" register "c3_latency" = "85" diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index ceb9279365..57b4960a12 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -39,7 +39,6 @@ chip northbridge/intel/sandybridge register "sata_interface_speed_support" = "0x3" register "pcie_port_coalesce" = "0" - register "p_cnt_throttling_supported" = "0" register "docking_supported" = "0" register "c2_latency" = "0x0065" diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index d24eb5d6ac..7045dbf8e1 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -45,7 +45,6 @@ chip northbridge/intel/x4x # Northbridge register "pirqf_routing" = "0x0b" register "pirqg_routing" = "0x0b" register "pirqh_routing" = "0x0b" - register "ide_legacy_combined" = "0x0" # Combined mode broken register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" register "sata_ports_implemented" = "0x3" diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index e695ab5f08..1039707ec3 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -27,9 +28,6 @@ #define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1 -#if ENV_RAMSTAGE -#include - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -43,36 +41,23 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif int get_write_protect_state(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; } int get_recovery_mode_switch(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; } void init_bootmode_straps(void) { u32 flags = 0; -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ if (get_gpio(GPIO_SPI_WP)) @@ -84,7 +69,7 @@ void init_bootmode_straps(void) /* Developer: Virtual */ - pci_write_config32(dev, SATA_SP, flags); + pci_s_write_config32(dev, SATA_SP, flags); } static const struct cros_gpio cros_gpios[] = { diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 7f72ad24bf..2825aae553 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -30,9 +31,6 @@ #define DEVMODE_GPIO 54 #define FORCE_RECOVERY_MODE 0 -#if ENV_RAMSTAGE -#include - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -53,7 +51,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif int get_write_protect_state(void) { diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index d8a0ee1c31..3c08b8bb60 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -66,7 +66,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 diff --git a/src/mainboard/google/butterfly/gpio.c b/src/mainboard/google/butterfly/gpio.c index 2d14699ef6..2630177cf1 100644 --- a/src/mainboard/google/butterfly/gpio.c +++ b/src/mainboard/google/butterfly/gpio.c @@ -15,7 +15,7 @@ #include -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_NONE, /* Unused */ .gpio1 = GPIO_MODE_NONE, /* Unused */ .gpio2 = GPIO_MODE_NONE, /* Unused */ @@ -50,7 +50,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio31 = GPIO_MODE_NONE, /* Unused */ }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, /* Unused */ .gpio1 = GPIO_DIR_INPUT, /* Unused */ .gpio2 = GPIO_DIR_INPUT, /* Unused */ @@ -85,7 +85,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio31 = GPIO_DIR_INPUT, /* Unused */ }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_LOW, /* Unused */ .gpio1 = GPIO_LEVEL_LOW, /* Unused */ .gpio2 = GPIO_LEVEL_LOW, /* Unused */ @@ -120,12 +120,12 @@ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio31 = GPIO_LEVEL_LOW, /* Unused */ }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio11 = GPIO_INVERT, /* invert touchpad wakeup pin */ .gpio13 = GPIO_INVERT, /* invert EC SCI pin */ }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, /* Native - Connect to EC Clock Run */ .gpio33 = GPIO_MODE_GPIO, /* Input - (Google protect BIOS ROM) */ .gpio34 = GPIO_MODE_NONE, /* Unused */ @@ -160,7 +160,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio63 = GPIO_MODE_NATIVE, /* Native - SLP_S5 */ }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, /* Native */ .gpio33 = GPIO_DIR_INPUT, /* Input */ .gpio34 = GPIO_DIR_INPUT, /* Unused */ @@ -195,7 +195,7 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio63 = GPIO_DIR_INPUT, /* Native */ }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_LOW, /* Native */ .gpio33 = GPIO_LEVEL_LOW, /* Input */ .gpio34 = GPIO_LEVEL_LOW, /* Unused */ @@ -230,7 +230,7 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio63 = GPIO_LEVEL_LOW, /* Native */ }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_NONE, /* Unused */ .gpio65 = GPIO_MODE_NONE, /* Unused */ .gpio66 = GPIO_MODE_NONE, /* Unused */ @@ -245,7 +245,7 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio75 = GPIO_MODE_GPIO, /* Input - SMB_ME1_DAT */ }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_INPUT, /* Unused */ .gpio65 = GPIO_DIR_INPUT, /* Unused */ .gpio66 = GPIO_DIR_INPUT, /* Unused */ @@ -260,7 +260,7 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio75 = GPIO_DIR_INPUT, /* Input */ }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_LOW, /* Unused */ .gpio65 = GPIO_LEVEL_LOW, /* Unused */ .gpio66 = GPIO_LEVEL_LOW, /* Unused */ diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 5d5bc556e5..154b913c4c 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -25,9 +26,6 @@ #define WP_GPIO GP_E_22 -#if ENV_RAMSTAGE -#include - #define ACTIVE_LOW 0 #define ACTIVE_HIGH 1 @@ -41,7 +39,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */ int get_write_protect_state(void) { diff --git a/src/mainboard/google/dragonegg/chromeos.c b/src/mainboard/google/dragonegg/chromeos.c index 7132b04698..3b69bff47d 100644 --- a/src/mainboard/google/dragonegg/chromeos.c +++ b/src/mainboard/google/dragonegg/chromeos.c @@ -15,15 +15,13 @@ #include #include +#include #include #include #include #include -#if ENV_RAMSTAGE -#include - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -36,7 +34,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */ int get_write_protect_state(void) { diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb index b3b93f55ca..bcad954885 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb @@ -148,6 +148,7 @@ chip soc/intel/icelake #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | + #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ @@ -165,6 +166,7 @@ chip soc/intel/icelake .sda_hold = 36, } }, + .pch_thermal_trip = 77, }" # GPIO PM programming @@ -181,7 +183,7 @@ chip soc/intel/icelake device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 04.0 off end # SA Thermal device - device pci 12.0 off end # Thermal Subsystem + device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 device pci 14.0 on diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig new file mode 100644 index 0000000000..deeca1503f --- /dev/null +++ b/src/mainboard/google/drallion/Kconfig @@ -0,0 +1,106 @@ + +config BOARD_GOOGLE_BASEBOARD_DRALLION + def_bool n + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_INTEL_ISH + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select EC_GOOGLE_WILCO + select GENERIC_SPD_BIN + select GOOGLE_SMBIOS_MAINBOARD_VERSION + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_I2C_TPM_CR50 + select MAINBOARD_HAS_TPM2 + select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + select TPM2 + select MAINBOARD_USES_IFD_EC_REGION + select MAINBOARD_USES_IFD_GBE_REGION + select USE_SAR + select SAR_ENABLE + +if BOARD_GOOGLE_BASEBOARD_DRALLION + +config CHROMEOS + bool + default y + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_DEV_BOOT_LEGACY + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config DRIVER_TPM_I2C_BUS + hex + default 0x4 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x50 + +config TPM_TIS_ACPI_INTERRUPT + int + default 82 # GPE0_DW2_18 (GPP_D18) + +config POWER_OFF_ON_CR50_UPDATE + bool + default n + +config GBB_HWID + string + depends on CHROMEOS + default "DRALLION TEST 3556" + +config MAINBOARD_DIR + string + default "google/drallion" + +config MAINBOARD_FAMILY + string + default "Google_Drallion" + +config MAINBOARD_PART_NUMBER + string + default "Drallion" + +config MAINBOARD_VENDOR + string + default "Google" + +config MAX_CPUS + int + default 8 + +config UART_FOR_CONSOLE + int + default 2 + +config VARIANT_DIR + string + default "drallion" + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config VBOOT + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + select VBOOT_LID_SWITCH + +endif # BOARD_GOOGLE_BASEBOARD_DRALLION diff --git a/src/mainboard/google/drallion/Kconfig.name b/src/mainboard/google/drallion/Kconfig.name new file mode 100644 index 0000000000..bd5d9032d2 --- /dev/null +++ b/src/mainboard/google/drallion/Kconfig.name @@ -0,0 +1,5 @@ +comment "Drallion" + +config BOARD_GOOGLE_DRALLION + bool "-> Drallion" + select BOARD_GOOGLE_BASEBOARD_DRALLION diff --git a/src/mainboard/google/drallion/Makefile.inc b/src/mainboard/google/drallion/Makefile.inc new file mode 100644 index 0000000000..c16e7d203d --- /dev/null +++ b/src/mainboard/google/drallion/Makefile.inc @@ -0,0 +1,38 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2018 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c + +ramstage-y += ramstage.c +ramstage-y += sku.c + +romstage-y += romstage.c + +smm-y += smihandler.c + +bootblock-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c + +bootblock-y += ec.c +ramstage-y += ec.c +romstage-y += ec.c +verstage-y += ec.c + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/drallion/acpi_tables.c b/src/mainboard/google/drallion/acpi_tables.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/google/drallion/board_info.txt b/src/mainboard/google/drallion/board_info.txt new file mode 100644 index 0000000000..dfc194bd0f --- /dev/null +++ b/src/mainboard/google/drallion/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Drallion +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/drallion/bootblock.c b/src/mainboard/google/drallion/bootblock.c new file mode 100644 index 0000000000..bee9b1ad7a --- /dev/null +++ b/src/mainboard/google/drallion/bootblock.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +static void early_config_gpio(void) +{ + const struct pad_config *early_gpio_table; + size_t num_gpios = 0; + + early_gpio_table = variant_early_gpio_table(&num_gpios); + gpio_configure_pads(early_gpio_table, num_gpios); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); + wilco_ec_early_init(); +} diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c new file mode 100644 index 0000000000..7aaf4015b5 --- /dev/null +++ b/src/mainboard/google/drallion/chromeos.c @@ -0,0 +1,127 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +enum rec_mode_state { + REC_MODE_UNINITIALIZED, + REC_MODE_NOT_REQUESTED, + REC_MODE_REQUESTED, +}; + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {GPIO_PCH_WP, ACTIVE_HIGH, get_write_protect_state(), + "write protect"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {-1, ACTIVE_HIGH, 0, "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +static int cros_get_gpio_value(int type) +{ + const struct cros_gpio *cros_gpios; + size_t i, num_gpios = 0; + + cros_gpios = variant_cros_gpios(&num_gpios); + + for (i = 0; i < num_gpios; i++) { + const struct cros_gpio *gpio = &cros_gpios[i]; + if (gpio->type == type) { + int state = gpio_get(gpio->gpio_num); + if (gpio->polarity == CROS_GPIO_ACTIVE_LOW) + return !state; + else + return state; + } + } + return 0; +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *cros_gpios; + size_t num_gpios = 0; + + cros_gpios = variant_cros_gpios(&num_gpios); + + chromeos_acpi_gpio_generate(cros_gpios, num_gpios); +} + +int get_write_protect_state(void) +{ + return cros_get_gpio_value(CROS_GPIO_WP); +} + +int get_recovery_mode_switch(void) +{ + static enum rec_mode_state saved_rec_mode = REC_MODE_UNINITIALIZED; + enum rec_mode_state state = REC_MODE_NOT_REQUESTED; + uint8_t cr50_state = 0; + + /* Check cached state, since TPM will only tell us the first time */ + if (saved_rec_mode != REC_MODE_UNINITIALIZED) + return saved_rec_mode == REC_MODE_REQUESTED; + + /* + * Read one-time recovery request from cr50 in verstage only since + * the TPM driver won't be set up in time for other stages like romstage + * and the value from the TPM would be wrong anyway since the verstage + * read would have cleared the value on the TPM. + * + * The TPM recovery request is passed between stages through the + * vboot_get_shared_data or cbmem depending on stage. + */ + if (ENV_VERSTAGE && + tlcl_cr50_get_recovery_button(&cr50_state) == TPM_SUCCESS && + cr50_state) + state = REC_MODE_REQUESTED; + + /* Read state from the GPIO controlled by servo. */ + if (cros_get_gpio_value(CROS_GPIO_REC)) + state = REC_MODE_REQUESTED; + + /* Store the state in case this is called again in verstage. */ + saved_rec_mode = state; + + return state == REC_MODE_REQUESTED; +} + +int get_lid_switch(void) +{ + return 1; +} + +void mainboard_prepare_cr50_reset(void) +{ +#if ENV_RAMSTAGE + /* Ensure system powers up after CR50 reset */ + pmc_set_afterg3(MAINBOARD_POWER_STATE_ON); +#endif +} diff --git a/src/mainboard/google/drallion/chromeos.fmd b/src/mainboard/google/drallion/chromeos.fmd new file mode 100644 index 0000000000..ece0eda099 --- /dev/null +++ b/src/mainboard/google/drallion/chromeos.fmd @@ -0,0 +1,49 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x400000 { + SI_DESC@0x0 0x1000 + SI_EC@0x1000 0x100000 + SI_GBE(PRESERVE)@0x101000 0x2000 + SI_ME@0x103000 0x2f9000 + SI_PDR(PRESERVE)@0x3fc000 0x4000 + } + SI_BIOS@0x400000 0x1c00000 { + RW_DIAG@0x0 0x12d0000 { + RW_LEGACY(CBFS)@0x0 0x12c0000 + DIAG_NVRAM@0x12c0000 0x10000 + } + RW_SECTION_A@0x12d0000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x26ffc0 + RW_FWID_A@0x27ffc0 0x40 + } + RW_SECTION_B@0x1550000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x26ffc0 + RW_FWID_B@0x27ffc0 0x40 + } + RW_MISC@0x17d0000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x28000 0x2000 + RW_NVRAM(PRESERVE)@0x2a000 0x6000 + } + WP_RO@0x1800000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_UNUSED@0x4000 0xc000 + RO_SECTION@0x10000 0x3f0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x300000 + } + } + } +} diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl new file mode 100644 index 0000000000..2568800f91 --- /dev/null +++ b/src/mainboard/google/drallion/dsdt.asl @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + /* Some generic macros */ + #include + + /* global NVS and variables */ + #include + + /* CPU */ + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + } + /* Per board variant mainboard hooks. */ + #include + } + +#if CONFIG(CHROMEOS) + /* Chrome OS specific */ + #include + /* VPD support */ + #include + /* MAC address passthru */ + #include +#endif + + /* Chipset specific sleep states */ + #include + + /* Low power idle table */ + #include + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include + /* ACPI code for EC functions */ + #include + } + + /* Dynamic Platform Thermal Framework */ + Scope (\_SB) + { + /* Per board variant specific definitions. */ + #include + /* Include soc specific DPTF changes */ + #include + /* Include common dptf ASL files */ + #include + } +} diff --git a/src/mainboard/google/drallion/ec.c b/src/mainboard/google/drallion/ec.c new file mode 100644 index 0000000000..fd8e84fbc8 --- /dev/null +++ b/src/mainboard/google/drallion/ec.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +void mainboard_post(uint8_t value) +{ + wilco_ec_save_post_code(value); +} diff --git a/src/cpu/allwinner/a10/chip.h b/src/mainboard/google/drallion/hda_verb.c similarity index 51% rename from src/cpu/allwinner/a10/chip.h rename to src/mainboard/google/drallion/hda_verb.c index af419ea99b..9ab4778274 100644 --- a/src/cpu/allwinner/a10/chip.h +++ b/src/mainboard/google/drallion/hda_verb.c @@ -1,23 +1,16 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Alexandru Gagniuc + * Copyright (C) 2018 Intel Corporation * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License or (at your option) - * any later version. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * Allwinnwer A10 devicetree config struct - * */ -#include - -struct cpu_allwinner_a10_config { -}; +#include "variant/hda_verb.h" diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c new file mode 100644 index 0000000000..b3bf10296a --- /dev/null +++ b/src/mainboard/google/drallion/ramstage.c @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define VPD_KEY_SYSTEM_SERIAL "serial_number" +#define VPD_KEY_MAINBOARD_SERIAL "mlb_serial_number" +#define VPD_SERIAL_LEN 64 + +const char *smbios_system_serial_number(void) +{ + static char serial[VPD_SERIAL_LEN]; + if (vpd_gets(VPD_KEY_SYSTEM_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) + return serial; + return ""; +} + +const char *smbios_mainboard_serial_number(void) +{ + static char serial[VPD_SERIAL_LEN]; + if (vpd_gets(VPD_KEY_MAINBOARD_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) + return serial; + return ""; +} + +/* mainboard silk screen shows DIMM-A and DIMM-B */ +void smbios_fill_dimm_locator(const struct dimm_info *dimm, + struct smbios_type17 *t) +{ + switch (dimm->channel_num) { + case 0: + t->device_locator = smbios_add_string(t->eos, "DIMM-A"); + break; + case 1: + t->device_locator = smbios_add_string(t->eos, "DIMM-B"); + break; + default: + t->device_locator = smbios_add_string(t->eos, "UNKNOWN"); + break; + } +} + +static const struct pad_config gpio_unused[] = { +/* SUSWARN# */ PAD_NC(GPP_A13, NONE), +/* SUSACK# */ PAD_NC(GPP_A15, NONE), +/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE), +/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), +}; + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + const struct pad_config *gpio_table; + size_t num_gpios; + + gpio_table = variant_gpio_table(&num_gpios); + cnl_configure_pads(gpio_table, num_gpios); + + /* Disable unused pads for devices with board ID > 2 */ + if (board_id() > 2) + gpio_configure_pads(gpio_unused, ARRAY_SIZE(gpio_unused)); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c new file mode 100644 index 0000000000..20eee7f34b --- /dev/null +++ b/src/mainboard/google/drallion/romstage.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +static const struct cnl_mb_cfg memcfg = { + /* Access memory info through SMBUS. */ + .spd[0] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa0}, + }, + .spd[1] = {.read_type = NOT_EXISTING}, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa4}, + }, + .spd[3] = {.read_type = NOT_EXISTING}, + + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = {0, 1, 4, 5, 2, 3, 6, 7}, + .dqs_map[DDR_CH1] = {0, 1, 4, 5, 2, 3, 6, 7}, + + /* Baseboard uses 121, 81 and 100 rcomp resistors */ + .rcomp_resistor = {121, 81, 100}, + + /* + * Baseboard Rcomp target values. + */ + .rcomp_targets = {100, 40, 20, 20, 26}, + + /* Disable Early Command Training */ + .ect = 0, + + /* Base on board design */ + .vref_ca_config = 2, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + wilco_ec_romstage_init(); + + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); +} diff --git a/src/cpu/intel/model_206ax/stage_cache.c b/src/mainboard/google/drallion/sku.c similarity index 56% rename from src/cpu/intel/model_206ax/stage_cache.c rename to src/mainboard/google/drallion/sku.c index 26dc5e03f9..d0b48f0572 100644 --- a/src/cpu/intel/model_206ax/stage_cache.c +++ b/src/mainboard/google/drallion/sku.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google, Inc. + * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,16 +13,23 @@ * GNU General Public License for more details. */ -#include -#include -#include "model_206ax.h" +#include +#include +#include +#include -void stage_cache_external_region(void **base, size_t *size) +uint32_t sku_id(void) { - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. - */ - *size = RESERVED_SMM_SIZE; - *base = (void *)((uintptr_t)cbmem_top() + RESERVED_SMM_OFFSET); + if (wilco_ec_signed_fw()) + return VARIANT_SKU_ID_SIGNED_EC; + else + return VARIANT_SKU_ID; +} + +const char *smbios_system_sku(void) +{ + if (wilco_ec_signed_fw()) + return VARIANT_SKU_NAME_SIGNED_EC; + else + return VARIANT_SKU_NAME; } diff --git a/src/mainboard/google/drallion/smihandler.c b/src/mainboard/google/drallion/smihandler.c new file mode 100644 index 0000000000..0efcaa9ef1 --- /dev/null +++ b/src/mainboard/google/drallion/smihandler.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +void mainboard_smi_espi_handler(void) +{ + wilco_ec_smi_espi(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + wilco_ec_smi_sleep(slp_typ); +} + +int mainboard_smi_apmc(u8 apmc) +{ + wilco_ec_smi_apmc(apmc); + return 0; +} diff --git a/src/mainboard/google/hatch/variants/hatch_whl/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc similarity index 69% rename from src/mainboard/google/hatch/variants/hatch_whl/Makefile.inc rename to src/mainboard/google/drallion/variants/drallion/Makefile.inc index ecf5c2fbdb..2bf028eb1f 100644 --- a/src/mainboard/google/hatch/variants/hatch_whl/Makefile.inc +++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc @@ -1,6 +1,7 @@ +## ## This file is part of the coreboot project. ## -## Copyright 2019 Google LLC +## Copyright 2018 Google LLC ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -12,11 +13,7 @@ ## GNU General Public License for more details. ## -SPD_SOURCES = 4G_2400 # 0b000 -SPD_SOURCES += empty_ddr4 # 0b001 -SPD_SOURCES += empty_ddr4 # 0b010 -SPD_SOURCES += empty_ddr4 # 0b011 -SPD_SOURCES += empty_ddr4 # 0b100 -SPD_SOURCES += 8G_2666 # 0b101 - +bootblock-y += gpio.c ramstage-y += gpio.c +romstage-y += gpio.c +verstage-y += gpio.c diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb new file mode 100644 index 0000000000..575b61014b --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -0,0 +1,393 @@ +chip soc/intel/cannonlake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "PMC_GPP_A" + register "gpe0_dw1" = "PMC_GPP_C" + register "gpe0_dw2" = "PMC_GPP_D" + + # EC host command ranges + register "gen1_dec" = "0x00040931" # 0x930-0x937 + register "gen2_dec" = "0x00040941" # 0x940-0x947 + register "gen3_dec" = "0x000c0951" # 0x950-0x95f + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "HeciEnabled" = "0" + register "SataSalpSupport" = "1" + register "SataMode" = "Sata_AHCI" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[2]" = "1" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "4" # 4s + register "PchPmSlpSusMinAssert" = "4" # 4s + register "PchPmSlpAMinAssert" = "4" # 2s + register "PchUnlockGpioPads" = "1" + + register "speed_shift_enable" = "1" + register "psys_pmax" = "140" + register "s0ix_enable" = "1" + register "dptf_enable" = "1" + register "dmipwroptimize" = "1" + register "satapwroptimize" = "1" + register "tdp_pl1_override" = "25" + register "tdp_pl2_override" = "51" + register "Device4Enable" = "1" + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" + register "SlowSlewRateForSa" = "0" + register "SlowSlewRateForFivr" = "2" + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + # Enable DDC for DDI port B + register "DdiPortBDdc" = "1" + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 6A | 70A | 31A | 31A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #| DcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #+----------------+-------+-------+-------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(6), + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(70), + .voltage_limit = 1520, + .ac_loadline = 180, + .dc_loadline = 180, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + # Intel Common SoC Config + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port + register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Left Type-A Port + register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port + register "usb2_ports[3]" = "USB2_PORT_EMPTY" + register "usb2_ports[4]" = "USB2_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera + register "usb2_ports[6]" = "{ + .enable = 1, \ + .ocpin = OC_SKIP, \ + .tx_bias = USB2_BIAS_0MV, \ + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_28P15MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ + }" # WWAN + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Left Type-A Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN + register "usb3_ports[4]" = "USB3_PORT_EMPTY" + register "usb3_ports[5]" = "USB3_PORT_EMPTY" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| I2C0 | Touchscreen | + #| I2C1 | Touchpad | + #| I2C4 | H1 TPM | + #+-------------------+---------------------------+ + + register "tcc_offset" = "1" + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 52, + .fall_time_ns = 110, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 52, + .fall_time_ns = 110, + .data_hold_time_ns = 330, + }, + .i2c[4] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 36, + .fall_time_ns = 99, + }, + }" + + # PCIe port 10 for M.2 2230 WLAN + register "PcieRpEnable[9]" = "1" + register "PcieClkSrcUsage[2]" = "9" + register "PcieClkSrcClkReq[2]" = "2" + + # PCIe port 11 for card reader + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + register "PcieClkSrcUsage[1]" = "10" + register "PcieClkSrcClkReq[1]" = "1" + + # PCIe port 13 for M.2 2280 SSD + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[4]" = "12" + register "PcieClkSrcClkReq[4]" = "4" + + # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | + MISCCFG_GPRTCDLCGEN | + MISCCFG_GSXSLCGEN | + MISCCFG_GPDPCGEN | + MISCCFG_GPDLCGEN" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 on # Integrated Sensor Hub + chip drivers/intel/ish + register "firmware_name" = ""drallion_ish.bin"" + device generic 0 on end + end + end + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""USH"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.7 on end + end + chip drivers/usb/acpi + register "desc" = ""Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.8 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H15)" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.3 on end + end + end + end + end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + chip drivers/intel/wifi + register "wake" = "PME_B0_EN_BIT" + device pci 14.3 on end # CNVi wifi + end + device pci 14.5 off end # SDCard + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM48E2"" + register "generic.desc" = ""Wacom Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "generic.reset_delay_ms" = "20" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "generic.enable_delay_ms" = "55" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0A on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "probed" = "1" + device i2c 2c on end + end + end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)" + device i2c 50 on end + end + end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Port 1 (USB) + device pci 1c.1 off end # PCI Express Port 2 (USB) + device pci 1c.2 off end # PCI Express Port 3 (USB) + device pci 1c.3 off end # PCI Express Port 4 (USB) + device pci 1c.4 off end # PCI Express Port 5 (USB) + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" + end # PCI Express Port 9 + device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.2 on end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 on + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + end # PCI Express Port 13 (x4) + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on + chip ec/google/wilco + device pnp 0c09.0 on end + end + end # LPC/eSPI + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c new file mode 100644 index 0000000000..ff0240c991 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -0,0 +1,279 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { +/* RCIN# */ PAD_NC(GPP_A0, NONE), +/* ESPI_IO0 */ +/* ESPI_IO1 */ +/* ESPI_IO2 */ +/* ESPI_IO3 */ +/* ESPI_CS# */ +/* SERIRQ */ +/* PIRQA# */ PAD_NC(GPP_A7, NONE), +/* CLKRUN# */ PAD_NC(GPP_A8, NONE), +/* ESPI_CLK */ +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), +/* PME# */ PAD_NC(GPP_A11, NONE), + /* ISH_LID_CL#_TAB */ +/* ISH_GP6 */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF2), +/* SUSWARN# */ PAD_NC(GPP_A13, NONE), +/* ESPI_RESET# */ +/* SUSACK# */ PAD_NC(GPP_A15, NONE), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), + /* ISH_ACC1_INT# */ +/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* ISH_ACC2_INT# */ +/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), + /* ISH_NB_MODE */ +/* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), + /* ISH_LID_CL#_NB */ +/* ISH_GP5 */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + +/* CORE_VID0 */ +/* CORE_VID1 */ +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ +/* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ + /* LAN_CLKREQ_CPU_N */ +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* CARD_CLKREQ_CPU_N */ +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* WLAN_CLKREQ_CPU_N */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* WWAN_CLKREQ_CPU_N */ +/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* SSD_CKLREQ_CPU_N */ +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* TBT_CLKREQ_CPU_N (nostuff) */ +/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */ +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), /* PRIM_CORE_OPT_DIS (nostuff) */ +/* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */ +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* RTC_DET# */ +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ +/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), +/* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K), + +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */ +/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */ +/* SMBALERT# */ PAD_NC(GPP_C2, DN_20K), +/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_SMBCLK */ +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_SMBDATA */ +/* SML0ALERT# */ PAD_NC(GPP_C5, DN_20K), +/* SM1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_SMBCLK */ +/* SM1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_SMBDATA */ +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), /* PCH_TBT_PERST# (nostuff) */ +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */ +/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */ +/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP, + EDGE_SINGLE), /* SIO_EXT_WAKE# */ +/* UART1_TXD */ PAD_NC(GPP_C13, NONE), +/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* LCD_CBL_DET# */ +/* UART1_CTS# */ PAD_NC(GPP_C15, NONE), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TS_I2C_SDA */ +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TS_I2C_SCL */ +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA_TP */ +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCK_TP */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ +/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), +/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, + LEVEL, NONE), /* TS_INT# */ + +/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), +/* SPI1_MISO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), /* ISH_LAN# */ +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* TBT_FORCE_PWR (nostuff) */ + /* ISH_I2C0_ACC_SDA */ +/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* ISH_I2C0_ACC_SCL */ +/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, DEEP), /* IR_CAM_DET# */ +/* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE), +/* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */ +/* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE), + /* ISH_CPU_UART0_RX */ +/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1), + /* ISH_CPU_UART0_TX */ +/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), +/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */ +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */ +/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ +/* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE), +/* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE), +/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 1, DEEP), /* WWAN_BB_RST# */ +/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* WWAN_GPIO_PERST# */ +/* I2S_MCLK */ PAD_CFG_GPI_SCI_LOW(GPP_D23, NONE, DEEP, + EDGE_SINGLE), /* WWAN_GPIO_WAKE# */ + +/* SATAXPCIE0 */ PAD_NC(GPP_E0, NONE), + /* M3042_PCIE#_SATA */ +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* M2880_PCIE_SATA# */ +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), +/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */ +/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */ +/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */ +/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ +/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */ +/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */ +/* USB2_OC2# */ PAD_NC(GPP_E11, NONE), +/* USB2_OC3# */ PAD_NC(GPP_E12, NONE), +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */ +/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */ +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_SCL_CPU */ +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_SDA_CPU */ +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), +/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), + +/* CNV_PA_BLANKING */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_COEX3 */ +/* GPP_F1 */ PAD_NC(GPP_F1, NONE), +/* GPP_F2 */ PAD_NC(GPP_F2, NONE), +/* GPP_F3 */ PAD_NC(GPP_F3, NONE), +/* CNV_BRI_DT */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), +/* CNV_BRI_RSP */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), +/* CNV_RGI_DT */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), +/* CNV_RGI_RSP */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), +/* CNV_MFUART2_RXD */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* CNV_COEX2 */ +/* CNV_MFUART2_TXD */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* CNV_COEX1 */ +/* GPP_F10 */ PAD_NC(GPP_F10, NONE), +/* EMMC_CMD */ PAD_NC(GPP_F11, NONE), +/* EMMC_DATA0 */ PAD_NC(GPP_F12, NONE), +/* EMMC_DATA1 */ PAD_NC(GPP_F13, NONE), +/* EMMC_DATA2 */ PAD_NC(GPP_F14, NONE), +/* EMMC_DATA3 */ PAD_NC(GPP_F15, NONE), +/* EMMC_DATA4 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA5 */ PAD_NC(GPP_F17, NONE), +/* EMMC_DATA6 */ PAD_NC(GPP_F18, NONE), +/* EMMC_DATA7 */ PAD_NC(GPP_F19, NONE), +/* EMMC_RCLK */ PAD_NC(GPP_F20, NONE), +/* EMMC_CLK */ PAD_NC(GPP_F21, NONE), +/* EMMC_RESET# */ PAD_NC(GPP_F22, NONE), +/* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE), + +/* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */ +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */ +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* TBT_CIO_PLUG_EVT# (nostuff) */ +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */ +/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */ +/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */ +/* SD_WP */ PAD_CFG_GPI(GPP_G7, NONE, DEEP), /* SPK_DET# */ + +/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), +/* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */ +/* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */ +/* I2S2_RXD */ PAD_NC(GPP_H3, NONE), +/* I2C2_SDA */ PAD_NC(GPP_H4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_H5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_H6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_H7, NONE), +/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ +/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ +/* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */ +/* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */ +/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), +/* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */ +/* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE), +/* DPPF_CTRLDATA */ PAD_NC(GPP_H17, NONE), +/* CPU_C10_GATE# */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10_GATE# */ +/* TIMESYNC0 */ PAD_NC(GPP_H19, NONE), +/* IMGCLKOUT1 */ PAD_NC(GPP_H20, NONE), +/* GPP_H21 */ PAD_NC(GPP_H21, NONE), +/* GPP_H22 */ PAD_NC(GPP_H22, NONE), /* RTD3_CIO_PWR_EN (nostuff) */ +/* GPP_H23 */ PAD_NC(GPP_H23, NONE), + +/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */ +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */ +/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* SIO_PWRBTN# */ +/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */ +/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */ +/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */ +/* GPD7 */ PAD_NC(GPD7, NONE), /* TBT_RTD3_WAKE# (nostuff) */ +/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK */ +/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SIO_SLP_WLAN# */ +/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* SIO_SLP_S5# */ +/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* PM_LANPHY_EN */ +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { +/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ +/* SSD RESET pin will stay low first */ +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ +/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ +/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ +/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ +/* RESET# need to stay low before FULL_CARD_POWER_OFF assert */ +/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */ +/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ +/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ +/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..73e1decc1b --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 98 +#define DPTF_CPU_CRITICAL 108 + +/* Skin Sensor for CPU VR temperature monitor */ +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "Skin" +#define DPTF_TSR0_PASSIVE 55 +#define DPTF_TSR0_CRITICAL 100 + +/* Memory Sensor for DDR temperature monitor */ +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "DDR" +#define DPTF_TSR1_PASSIVE 53 +#define DPTF_TSR1_CRITICAL 100 + +/* M.2 Sensor for Ambient temperature monitor */ +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "Ambient" +#define DPTF_TSR2_PASSIVE 38 +#define DPTF_TSR2_CRITICAL 93 + +#undef DPTF_ENABLE_FAN_CONTROL +#undef DPTF_ENABLE_CHARGER + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 500, 100, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Skin (TSR0) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 400, 40, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on DDR (TSR1) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 300, 50, 2, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR2) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 1000, 100, 1, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 21000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 51000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + } +}) diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..41121d28fe --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CAM_EN GPP_B11 /* Active low */ +#define TS_PD GPP_E7 + +/* Method called from LPIT prior to enter s0ix state */ +Method (MS0X, 1) +{ + If (Arg0) { + /* Turn off camera power */ + \_SB.PCI0.STXS (CAM_EN) + } Else { + /* Turn on camera power */ + \_SB.PCI0.CTXS (CAM_EN) + } +} + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) +{ + \_SB.PCI0.LPCB.EC0.PTS (Arg0) + + /* Clear touch screen pd pin to avoid leakage */ + \_SB.PCI0.CTXS (TS_PD) +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) +{ + \_SB.PCI0.LPCB.EC0.WAK (Arg0) +} diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h new file mode 100644 index 0000000000..01a17b5f99 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include +#include + +/* EC wake pin */ +#define EC_WAKE_PIN GPE0_DW1_12 + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* Enable PS/2 keyboard */ +#define SIO_EC_ENABLE_PS2K + +/* Enable DPTF */ +#define EC_ENABLE_DPTF + +#endif diff --git a/src/mainboard/google/hatch/variants/hatch_whl/include/variant/gpio.h b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h similarity index 60% rename from src/mainboard/google/hatch/variants/hatch_whl/include/variant/gpio.h rename to src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h index 29e590422f..f7e0403e59 100644 --- a/src/mainboard/google/hatch/variants/hatch_whl/include/variant/gpio.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC + * Copyright 2018 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,12 +16,19 @@ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H -#include +#include +#include -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_F20 -#define GPIO_MEM_CONFIG_1 GPP_F21 -#define GPIO_MEM_CONFIG_2 GPP_F11 -#define GPIO_MEM_CONFIG_3 GPP_F22 +/* Flash Write Protect */ +#define GPIO_PCH_WP GPP_E15 + +/* Recovery mode */ +#define GPIO_REC_MODE GPP_E8 + +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); + +struct cros_gpio; +const struct cros_gpio *variant_cros_gpios(size_t *num); #endif diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h b/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h new file mode 100644 index 0000000000..10fbaf13f5 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h @@ -0,0 +1,209 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_HDA_VERB_H +#define MAINBOARD_HDA_VERB_H + +#include + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0295, // Codec Vendor / Device ID: Realtek ALC3204 + 0xffffffff, // Subsystem ID + 0x0000002b, // Number of jacks (NID entries) + + /* Rest Codec First */ + AZALIA_RESET(0x1), + /* NID 0x01, HDA Codec Subsystem ID Verb Table */ + AZALIA_SUBVENDOR(0x0, 0x102808b6), + + /* Pin Widget Verb Table */ + AZALIA_PIN_CFG(0x0, 0x12, 0xb7a60130), + AZALIA_PIN_CFG(0x0, 0x13, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0x0, 0x16, 0x40000000), + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x19, 0x04a11030), + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1d, 0x40c00001), + AZALIA_PIN_CFG(0x0, 0x1e, 0x421212f2), + AZALIA_PIN_CFG(0x0, 0x21, 0x04211020), + + /* D reset */ + 0x0205003C, + 0x0204F254, + 0x0205003C, + 0x0204F214, + /* JD1 - 2port JD mode */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + /* Set TRS type-1 */ + 0x02050045, + 0x02045289, + 0x02050049, + 0x02040049, + /* Set TRS type-2 + Set UAJ Line2 vref(ALC3254) */ + 0x0205004A, + 0x0204A830, + 0x02050063, + 0x0204CF00, + /* NID 0x20 set class-D to 2W@4ohm (+12dB gain) + * + Set sine tone gain(0x34) */ + 0x02050038, + 0x02043909, + 0x05C50000, + 0x05C43482, + /* AGC-1 Disable + (Front Gain=0dB ) */ + 0x05D50006, + 0x05D44C50, + 0x05D50002, + 0x05D44004, + /* AGC-2 (Backt Boost Gain= -0.375dB ,Limiter = -3dB) */ + 0x05D50003, + 0x05D45E5E, + 0x05D50001, + 0x05D4D788, + /* AGC-3 + AGC Enable */ + 0x05D50009, + 0x05D451FF, + 0x05D50006, + 0x05D44E50, + /* HP-JD Enable +Nokia type */ + 0x0205004A, + 0x02042010, + 0x02050008, + 0x02046A0C, + /* EAPD set to verb-control + I2C Un-use+ DVDD3.3V */ + 0x02050010, + 0x02040020, + 0x02050034, + 0x0204A23D, + /* Class D silent detection Enable -84dB threshold */ + 0x02050030, + 0x02049000, + 0x02050037, + 0x0204FE15, + /* Disable EQ + set 250Hz 3rd High Pass filter */ + 0x05350000, + 0x0534203A, + 0x05350000, + 0x0534203A, + /* Left Channel-1 */ + 0x0535001d, + 0x05340800, + 0x0535001e, + 0x05340800, + /* Left Channel-2 */ + 0x05350003, + 0x05341EF8, + 0x05350004, + 0x05340000, + /* Left Channel-3 */ + 0x05350005, + 0x053403EE, + 0x05350006, + 0x0534FA60, + /* Left Channel-4 */ + 0x05350007, + 0x05341E10, + 0x05350008, + 0x05347B86, + /* Left Channel-5 */ + 0x05350009, + 0x053401F7, + 0x0535000A, + 0x05349FB6, + /* Left Channel-6 */ + 0x0535000B, + 0x05341C00, + 0x0535000C, + 0x05340000, + /* Left Channel-7 */ + 0x0535000D, + 0x05340200, + 0x0535000E, + 0x05340000, + /* Right Channel-1 */ + 0x05450000, + 0x05442000, + 0x0545001d, + 0x05440800, + /* Right Channel-2 */ + 0x0545001e, + 0x05440800, + 0x05450003, + 0x05441EF8, + /* Right Channel-3 */ + 0x05450004, + 0x05440000, + 0x05450005, + 0x054403EE, + /* Right Channel-4 */ + 0x05450006, + 0x0544FA60, + 0x05450007, + 0x05441E10, + /* Right Channel-5 */ + 0x05450008, + 0x05447B86, + 0x05450009, + 0x054401F7, + /* Right Channel-6 */ + 0x0545000A, + 0x05449FB6, + 0x0545000B, + 0x05441C00, + /* Right Channel-7 */ + 0x0545000C, + 0x05440000, + 0x0545000D, + 0x05440200, + /* Right Channel-8 + EQ Update & Enable */ + 0x0545000E, + 0x05440000, + 0x05350000, + 0x0534E03A, + /* Enable all Microphone */ + 0x0205000D, + 0x0204A023, + 0x0205000D, + 0x0204A023, + /* Enable Internal Speaker (NID14) */ + 0x0205000F, + 0x02040000, + 0x0205000F, + 0x02040000, +}; + +const u32 pc_beep_verbs[] = { + /* PCBeep pass through to NID14 for ePSA test-1 */ + 0x02050036, + 0x020477D7, + 0x0143B000, + 0x01470740, + /* PCBeep pass through to NID14 for ePSA test-2 */ + 0x01470C02, + 0x01470C02, + 0x01470C02, + 0x01470C02, +}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h new file mode 100644 index 0000000000..d878623d59 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* Need to update for Drallion with right SKU IDs*/ +#define VARIANT_SKU_ID 2 +#define VARIANT_SKU_NAME "sku2" +#define VARIANT_SKU_ID_SIGNED_EC 4 +#define VARIANT_SKU_NAME_SIGNED_EC "sku4" + +#endif diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index 8c276e9ae1..9a1dd04f9c 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -14,15 +14,13 @@ * GNU General Public License for more details. */ +#include #include #include #include #include "gpio.h" -#if ENV_RAMSTAGE -#include - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -35,7 +33,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */ int get_write_protect_state(void) { diff --git a/src/mainboard/google/eve/ec.h b/src/mainboard/google/eve/ec.h index b94012160e..f7fea1448e 100644 --- a/src/mainboard/google/eve/ec.h +++ b/src/mainboard/google/eve/ec.h @@ -45,10 +45,11 @@ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) -/* EC can wake from S3 with lid or power button or key press */ +/* EC can wake from S3 with lid or power button or key press or MKBP */ #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) /* Log EC wake events plus EC shutdown events */ diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index 31887c59fb..25c52a596b 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -20,9 +21,6 @@ #include -#if ENV_RAMSTAGE -#include - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -35,7 +33,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */ int get_write_protect_state(void) { diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 54fd7dfe6d..6b3423b886 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -221,8 +221,7 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(struct device *dev) { - struct device *root = SA_DEV_ROOT; - config_t *conf = root->chip_info; + config_t *conf = config_of_path(SA_DEVFN_ROOT); mainboard_set_power_limits(conf); diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index b6029dd0f9..c89a9a8371 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -14,14 +14,12 @@ * GNU General Public License for more details. */ +#include #include #include #include #include -#if ENV_RAMSTAGE -#include - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -34,7 +32,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */ int get_write_protect_state(void) { diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 80451299f6..5991b93e31 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -36,6 +36,15 @@ config CHROMEOS select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH +config CHROMEOS_WIFI_SAR + bool "Enable SAR options for Chrome OS build" + depends on CHROMEOS + select DSAR_ENABLE + select GEO_SAR_ENABLE + select SAR_ENABLE + select USE_SAR + select WIFI_SAR_CBFS + config DEVICETREE string default "variants/baseboard/devicetree.cb" @@ -63,7 +72,6 @@ config GBB_HWID string depends on CHROMEOS default "HATCH TEST 1823" if BOARD_GOOGLE_HATCH - default "HATCH_WHL TEST 2374" if BOARD_GOOGLE_HATCH_WHL default "HELIOS TEST 0878" if BOARD_GOOGLE_HELIOS default "KINDRED TEST 2636" if BOARD_GOOGLE_KINDRED default "KOHAKU TEST 1953" if BOARD_GOOGLE_KOHAKU @@ -79,7 +87,6 @@ config MAINBOARD_FAMILY config MAINBOARD_PART_NUMBER string default "Hatch" if BOARD_GOOGLE_HATCH - default "Hatch_whl" if BOARD_GOOGLE_HATCH_WHL default "Helios" if BOARD_GOOGLE_HELIOS default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU @@ -103,7 +110,6 @@ config TPM_TIS_ACPI_INTERRUPT config VARIANT_DIR string default "hatch" if BOARD_GOOGLE_HATCH - default "hatch_whl" if BOARD_GOOGLE_HATCH_WHL default "helios" if BOARD_GOOGLE_HELIOS default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 9a257259ad..3b5d3f2910 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -6,12 +6,6 @@ config BOARD_GOOGLE_HATCH select BOARD_ROMSIZE_KB_32768 select SOC_INTEL_COMETLAKE -config BOARD_GOOGLE_HATCH_WHL - bool "-> Hatch_whl" - select BOARD_GOOGLE_BASEBOARD_HATCH - select BOARD_ROMSIZE_KB_32768 - select SOC_INTEL_WHISKEYLAKE - config BOARD_GOOGLE_KOHAKU bool "-> Kohaku" select BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/bootblock.c b/src/mainboard/google/hatch/bootblock.c index 9534af11d9..15dfe933eb 100644 --- a/src/mainboard/google/hatch/bootblock.c +++ b/src/mainboard/google/hatch/bootblock.c @@ -19,18 +19,11 @@ static void early_config_gpio(void) { - const struct pad_config *base_early_table; - const struct pad_config *override_early_table; - size_t base_gpios; - size_t override_gpios; + const struct pad_config *variant_early_table; + size_t variant_gpios; - base_early_table = base_early_gpio_table(&base_gpios); - override_early_table = override_early_gpio_table(&override_gpios); - - gpio_configure_pads_with_override(base_early_table, - base_gpios, - override_early_table, - override_gpios); + variant_early_table = variant_early_gpio_table(&variant_gpios); + gpio_configure_pads(variant_early_table, variant_gpios); } void bootblock_mainboard_init(void) diff --git a/src/mainboard/google/hatch/mainboard.c b/src/mainboard/google/hatch/mainboard.c index eb77a0030b..4d5e8ed5f8 100644 --- a/src/mainboard/google/hatch/mainboard.c +++ b/src/mainboard/google/hatch/mainboard.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -23,7 +24,7 @@ #define SKU_UNKNOWN 0xFFFFFFFF #define SKU_MAX 255 -static uint32_t get_board_sku(void) +uint32_t get_board_sku(void) { static uint32_t sku_id = SKU_UNKNOWN; diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c index 3436007252..04e1bc10ea 100644 --- a/src/mainboard/google/hatch/ramstage.c +++ b/src/mainboard/google/hatch/ramstage.c @@ -28,6 +28,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) size_t base_gpios; size_t override_gpios; + variant_devtree_update(); base_table = base_gpio_table(&base_gpios); override_table = override_gpio_table(&override_gpios); @@ -37,6 +38,11 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) override_gpios); } +void __weak variant_devtree_update(void) +{ + /* Override dev tree settings per board */ +} + static void mainboard_enable(struct device *dev) { mainboard_ec_init(); diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index 69fee28025..a94fab5df9 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -29,7 +29,7 @@ */ #define GPIO_MEM_CH_SEL GPP_F2 -static int memory_sku(void) +int __weak variant_memory_sku(void) { const gpio_t spd_gpios[] = { GPIO_MEM_CONFIG_0, @@ -48,7 +48,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) int is_single_ch_mem; variant_memory_params(&memcfg); - mem_sku = memory_sku(); + mem_sku = variant_memory_sku(); /* * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single * channel skus and 0 for dual channel skus. diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 6ff90f8d9d..00198a5a81 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -47,6 +47,13 @@ chip soc/intel/cannonlake # Unlock GPIO pads register "PchUnlockGpioPads" = "1" + # NOTE: if any variant wants to override this value, use the same format + # as register "common_soc_config.pch_thermal_trip" = "value", instead of + # putting it under register "common_soc_config" in overridetree.cb file. + register "common_soc_config.pch_thermal_trip" = "77" + + register "PmTimerDisabled" = "1" + # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | @@ -179,6 +186,12 @@ chip soc/intel/cannonlake register "gpio_pm[COMM_3]" = "0" register "gpio_pm[COMM_4]" = "0" + # chipset_lockdown configuration + # Use below format to override value in overridetree.cb if required + # format: + # register "common_soc_config." = "value" + register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT + device cpu_cluster 0 on device lapic 0 on end end @@ -188,7 +201,7 @@ chip soc/intel/cannonlake device pci 02.0 on end # Integrated Graphics Device device pci 04.0 off end # SA Thermal device device pci 05.0 off end # SA IPU - device pci 12.0 off end # Thermal Subsystem + device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 device pci 14.0 on diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index a466972048..fcb1a614cc 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -30,7 +30,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL), /* A7 : PP3300_SOC_A */ PAD_NC(GPP_A7, NONE), - /* A8 : PEN_GARAGE_DET_L */ + /* A8 : PEN_GARAGE_DET_L (wake) */ PAD_CFG_GPI_GPIO_DRIVER_SCI(GPP_A8, NONE, DEEP, LEVEL, NONE), /* A9 : ESPI_CLK */ /* A10 : FPMCU_PCH_BOOT1 */ @@ -324,8 +324,12 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1), /* G6 : SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), - /* G7 : SD_WP => NC */ - PAD_NC(GPP_G7, NONE), + /* G7 : SD_WP + * As per schematics SD host controller SD_WP pin is not connected to + * uSD card connector. In order to overcome gpio default state, ensures + * to configure gpio pin as NF1 with internal 20K pull down. + */ + PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* * H0 : HP_INT_L */ @@ -382,6 +386,9 @@ static const struct pad_config gpio_table[] = { /* SD card detect VGPIO */ PAD_CFG_GPI_GPIO_DRIVER(vSD3_CD_B, NONE, DEEP), + + /* CNV_WCEN : Disable Wireless Charging */ + PAD_CFG_GPO(CNV_WCEN, 0, DEEP), }; const struct pad_config *base_gpio_table(size_t *num) @@ -419,42 +426,6 @@ const struct pad_config *__weak variant_sleep_gpio_table( return default_sleep_gpio_table; } -/* GPIOs needed prior to ramstage. */ -static const struct pad_config early_gpio_table[] = { - /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), - /* B15 : H1_SLAVE_SPI_CS_L */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* B16 : H1_SLAVE_SPI_CLK */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* B17 : H1_SLAVE_SPI_MISO_R */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* B18 : H1_SLAVE_SPI_MOSI_R */ - PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* PCH_WP_OD */ - PAD_CFG_GPI(GPP_C20, NONE, DEEP), - /* C21 : H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - /* C23 : WLAN_PE_RST# */ - PAD_CFG_GPO(GPP_C23, 1, DEEP), - /* F2 : MEM_CH_SEL */ - PAD_CFG_GPI(GPP_F2, NONE, PLTRST), - /* F11 : PCH_MEM_STRAP2 */ - PAD_CFG_GPI(GPP_F11, NONE, PLTRST), - /* F20 : PCH_MEM_STRAP0 */ - PAD_CFG_GPI(GPP_F20, NONE, PLTRST), - /* F21 : PCH_MEM_STRAP1 */ - PAD_CFG_GPI(GPP_F21, NONE, PLTRST), - /* F22 : PCH_MEM_STRAP3 */ - PAD_CFG_GPI(GPP_F22, NONE, PLTRST), -}; - -const struct pad_config *base_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), @@ -472,9 +443,3 @@ const struct pad_config *__weak override_gpio_table(size_t *num) *num = 0; return NULL; } - -const struct pad_config *__weak override_early_gpio_table(size_t *num) -{ - *num = 0; - return NULL; -} diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h index 17bd5df63d..920e428484 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h @@ -23,21 +23,31 @@ /* * The next set of functions return the gpio table and fill in the number of - * entries for each table. The "base" GPIOs live in the "hatch" variant, and + * entries for each table. The "base" GPIOs live in the "baseboard" variant, and * the overrides live with the specific board (kohaku, kled, etc.). */ const struct pad_config *base_gpio_table(size_t *num); -const struct pad_config *base_early_gpio_table(size_t *num); const struct pad_config *override_gpio_table(size_t *num); -const struct pad_config *override_early_gpio_table(size_t *num); /* Return board specific memory configuration */ void variant_memory_params(struct cnl_mb_cfg *bcfg); +/* Return memory SKU for the variant */ +int variant_memory_sku(void); + /* Return variant specific gpio pads to be configured during sleep */ const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num); +/* Return GPIO pads that need to be configured before ramstage */ +const struct pad_config *variant_early_gpio_table(size_t *num); + /* Return ChromeOS gpio table and fill in number of entries. */ const struct cros_gpio *variant_cros_gpios(size_t *num); +/* Return board SKU */ +uint32_t get_board_sku(void); + +/* Modify devictree settings during ramstage. */ +void variant_devtree_update(void); + #endif /* BASEBOARD_VARIANTS_H */ diff --git a/src/mainboard/google/hatch/variants/hatch/Makefile.inc b/src/mainboard/google/hatch/variants/hatch/Makefile.inc index 555cbb463c..a990b5ad05 100644 --- a/src/mainboard/google/hatch/variants/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/variants/hatch/Makefile.inc @@ -20,3 +20,4 @@ SPD_SOURCES += 16G_2400 # 0b100 SPD_SOURCES += 16G_2666 # 0b101 ramstage-y += gpio.c +bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index f95e0220f1..56f587b6b8 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -27,3 +27,43 @@ const struct pad_config *override_gpio_table(size_t *num) *num = ARRAY_SIZE(gpio_table); return gpio_table; } + +/* + * GPIOs configured before ramstage + * Note: the Hatch platform's romstage will configure + * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins + * as inputs before it reads them, so they are not + * needed in this table. + */ +static const struct pad_config early_gpio_table[] = { + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/hatch_whl/gpio.c b/src/mainboard/google/hatch/variants/hatch_whl/gpio.c deleted file mode 100644 index 7e73724387..0000000000 --- a/src/mainboard/google/hatch/variants/hatch_whl/gpio.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2019 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -static const struct pad_config gpio_table[] = { - /* C13 : EC_PCH_INT_L - * TODO Configure it back to invert mode, when - * ITSS IPCx configuration is fixed in FSP. - */ - PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, NONE)}; - -const struct pad_config *override_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} diff --git a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb deleted file mode 100644 index 03218675c0..0000000000 --- a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb +++ /dev/null @@ -1,162 +0,0 @@ -chip soc/intel/cannonlake - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| GSPI1 | FP MCU | - #| I2C0 | Touchpad | - #| I2C1 | Touch screen | - #| I2C4 | Audio | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - }, - }" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "vSD3_CD_B" - - # USB configuration - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Discrete BT - - device domain 0 on - device pci 14.0 on - chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""Discrete bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C14)" - device usb 2.4 on end - end - end - end - end # USB xHCI - device pci 15.0 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)" - register "wake" = "GPE0_DW0_21" - device i2c 15 on end - end - end # I2C #0 - device pci 15.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - register "probed" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "reset_delay_ms" = "100" - register "reset_off_delay_ms" = "5" - register "has_power_resource" = "1" - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" - register "stop_off_delay_ms" = "5" - device i2c 49 on end - end - chip drivers/i2c/hid - register "generic.hid" = ""GDIX0000"" - register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "10" - register "generic.reset_off_delay_ms" = "3" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" - register "generic.enable_delay_ms" = "12" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 5d on end - end - chip drivers/generic/gpio_keys - register "name" = ""PENH"" - register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" - register "key.wake" = "GPE0_DW0_08" - register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" - register "key.dev_name" = ""EJCT"" - register "key.linux_code" = "SW_PEN_INSERTED" - register "key.linux_input_type" = "EV_SW" - register "key.label" = ""pen_eject"" - device generic 0 on end - end - end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 on - chip drivers/i2c/sx9310 - register "desc" = ""SAR Proximity Sensor"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A0)" - register "speed" = "I2C_SPEED_FAST" - register "uid" = "1" - register "reg_prox_ctrl0" = "0x10" - register "reg_prox_ctrl1" = "0x00" - register "reg_prox_ctrl2" = "0x84" - register "reg_prox_ctrl3" = "0x0e" - register "reg_prox_ctrl4" = "0x07" - register "reg_prox_ctrl5" = "0xc6" - register "reg_prox_ctrl6" = "0x20" - register "reg_prox_ctrl7" = "0x0d" - register "reg_prox_ctrl8" = "0x8d" - register "reg_prox_ctrl9" = "0x43" - register "reg_prox_ctrl10" = "0x1f" - register "reg_prox_ctrl11" = "0x00" - register "reg_prox_ctrl12" = "0x00" - register "reg_prox_ctrl13" = "0x00" - register "reg_prox_ctrl14" = "0x00" - register "reg_prox_ctrl15" = "0x00" - register "reg_prox_ctrl16" = "0x00" - register "reg_prox_ctrl17" = "0x00" - register "reg_prox_ctrl18" = "0x00" - register "reg_prox_ctrl19" = "0x00" - register "reg_sar_ctrl0" = "0x50" - register "reg_sar_ctrl1" = "0x8a" - register "reg_sar_ctrl2" = "0x3c" - device i2c 28 on end - end - end # I2C #3 - device pci 19.0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" - register "property_count" = "1" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on end - end - end #I2C #4 - device pci 1e.3 on - chip drivers/spi/acpi - register "name" = ""CRFP"" - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "uid" = "1" - register "compat_string" = ""google,cros-ec-spi"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" - device spi 1 on end - end # FPMCU - end # GSPI #1 - end - -end diff --git a/src/mainboard/google/hatch/variants/helios/gpio.c b/src/mainboard/google/hatch/variants/helios/gpio.c index 4353fc0a91..0ad3967ee9 100644 --- a/src/mainboard/google/hatch/variants/helios/gpio.c +++ b/src/mainboard/google/hatch/variants/helios/gpio.c @@ -51,6 +51,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_D8, NONE), /* D10 : ISH_SPI_CLK ==> EN_PP3300_PP1800_FP */ PAD_CFG_GPO(GPP_D10, 0, DEEP), + /* D16 : USI_INT_L */ + PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT), /* D21 : SPI1_IO2 ==> NC */ PAD_NC(GPP_D21, NONE), /* F0 : GPP_F0 ==> NC */ @@ -83,14 +85,16 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_G5, NONE), /* G6 : GPP_G6 ==> NC */ PAD_NC(GPP_G6, NONE), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), /* H4 : I2C2_SDA ==> NC */ PAD_NC(GPP_H4, NONE), /* H5 : I2C2_SCL ==> NC */ PAD_NC(GPP_H5, NONE), /* H13 : M2_SKT2_CFG1 ==> SPKR_RST_L */ - PAD_CFG_GPO(GPP_H13, 0, PLTRST), + PAD_CFG_GPO(GPP_H13, 1, DEEP), /* H14 : M2_SKT2_CFG2 ==> TOUCHSCREEN_STOP_L */ - PAD_CFG_GPO(GPP_H14, 0, PLTRST), + PAD_CFG_GPO(GPP_H14, 1, PLTRST), /* H19 : TIMESYNC[0] ==> MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ @@ -103,12 +107,39 @@ const struct pad_config *override_gpio_table(size_t *num) return gpio_table; } -/* GPIOs configured before ramstage */ +/* + * GPIOs configured before ramstage + * Note: the Hatch platform's romstage will configure + * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins + * as inputs before it reads them, so they are not + * needed in this table. + */ static const struct pad_config early_gpio_table[] = { - PAD_NC(GPP_C23, NONE), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), }; -const struct pad_config *override_early_gpio_table(size_t *num) +const struct pad_config *variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; diff --git a/src/mainboard/google/hatch/variants/helios/memory.c b/src/mainboard/google/hatch/variants/helios/memory.c index 64b4cac8d0..a3cd813f09 100644 --- a/src/mainboard/google/hatch/variants/helios/memory.c +++ b/src/mainboard/google/hatch/variants/helios/memory.c @@ -15,8 +15,11 @@ #include #include +#include +#include #include #include +#include static const struct cnl_mb_cfg baseboard_memcfg = { /* @@ -66,3 +69,34 @@ void variant_memory_params(struct cnl_mb_cfg *bcfg) { memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg)); } + +int variant_memory_sku(void) +{ + const gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + int val = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); + + if ((board_id() != 0) && (board_id() != BOARD_ID_UNKNOWN)) + return val; + + /* + * For boards with id 0 or unknown, memory straps 3 and 4 are + * incorrectly stuffed in hardware. This is a workaround for these + * boards to override memory strap 3 to 0 and 4 to 1. + */ + switch (val) { + case 3: + val = 0; + break; + case 4: + val = 1; + break; + } + + return val; +} diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index 1907289621..f97f120e7b 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -21,6 +21,7 @@ chip soc/intel/cannonlake #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ + #| GSPI1 | FP MCU | #| I2C0 | Trackpad | #| I2C1 | Touchscreen | #| I2C4 | Audio | @@ -28,12 +29,24 @@ chip soc/intel/cannonlake register "common_soc_config" = "{ .i2c[0] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 50, + .fall_time_ns = 15, + .data_hold_time_ns = 330, }, .i2c[1] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 25, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 150, + .fall_time_ns = 150, }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 120, + .fall_time_ns = 120, }, .gspi[0] = { .speed_mhz = 1, @@ -82,12 +95,17 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = + "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "10" register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "10" + register "generic.enable_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end @@ -124,6 +142,44 @@ chip soc/intel/cannonlake register "property_list[0].integer" = "1" device i2c 1a on end end + chip drivers/i2c/generic + register "hid" = ""10EC1011"" + register "desc" = ""RT1011 Tweeter Left Speaker Amp"" + register "uid" = "0" + register "name" = ""TL"" + device i2c 38 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1011"" + register "desc" = ""RT1011 Tweeter Right Speaker Amp"" + register "uid" = "1" + register "name" = ""TR"" + device i2c 39 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1011"" + register "desc" = ""RT1011 Woofer Left Speaker Amp"" + register "uid" = "2" + register "name" = ""WL"" + device i2c 3a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1011"" + register "desc" = ""RT1011 Woofer Right Speaker Amp"" + register "uid" = "3" + register "name" = ""WR"" + device i2c 3b on end + end end #I2C #4 + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" + device spi 1 on end + end # FPMCU + end # GSPI #1 end end diff --git a/src/mainboard/google/hatch/variants/kindred/Makefile.inc b/src/mainboard/google/hatch/variants/kindred/Makefile.inc index 563275dd19..78f3812252 100644 --- a/src/mainboard/google/hatch/variants/kindred/Makefile.inc +++ b/src/mainboard/google/hatch/variants/kindred/Makefile.inc @@ -21,3 +21,4 @@ SPD_SOURCES += 16G_2666 # 0b101 bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c index f6aeb690c5..d6525e6564 100644 --- a/src/mainboard/google/hatch/variants/kindred/gpio.c +++ b/src/mainboard/google/hatch/variants/kindred/gpio.c @@ -59,19 +59,41 @@ const struct pad_config *override_gpio_table(size_t *num) return gpio_table; } -/* GPIOs configured before ramstage */ +/* + * GPIOs configured before ramstage + * Note: the Hatch platform's romstage will configure + * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins + * as inputs before it reads them, so they are not + * needed in this table. + */ static const struct pad_config early_gpio_table[] = { - /* F3 : MEM_STRAP_3 */ - PAD_CFG_GPI(GPP_F3, NONE, PLTRST), - /* F10 : MEM_STRAP_2 */ - PAD_CFG_GPI(GPP_F10, NONE, PLTRST), - /* H19 : MEM_STRAP_0 */ - PAD_CFG_GPI(GPP_H19, NONE, PLTRST), - /* H22 : MEM_STRAP_1 */ - PAD_CFG_GPI(GPP_H22, NONE, PLTRST), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), }; -const struct pad_config *override_early_gpio_table(size_t *num) +const struct pad_config *variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; diff --git a/src/mainboard/cubietech/cubieboard/memlayout.ld b/src/mainboard/google/hatch/variants/kindred/variant.c similarity index 54% rename from src/mainboard/cubietech/cubieboard/memlayout.ld rename to src/mainboard/google/hatch/variants/kindred/variant.c index b9bf10b8f6..14b26ed10c 100644 --- a/src/mainboard/cubietech/cubieboard/memlayout.ld +++ b/src/mainboard/google/hatch/variants/kindred/variant.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Alexandru Gagniuc + * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,22 +13,22 @@ * GNU General Public License for more details. */ -#include +#include +#include +#include -#include - -SECTIONS +void variant_devtree_update(void) { - SRAM_START(0x0) - /* eGON.BT0: 32 bytes */ - BOOTBLOCK(0x20, 0x5fa0) - STACK(0x6000, 8K) - SRAM_END(0x8000) + uint32_t sku_id; + struct device *emmc_host; - DRAM_START(0x40000000) - RAMSTAGE(0x40000000, 16M) - ROMSTAGE(0x41000000, 108K) + emmc_host = pcidev_path_on_root(PCH_DEVFN_EMMC); - /* TODO: Implement MMU support and move TTB to a better location. */ - TTB(0x42000000, 16K) + if (emmc_host == NULL) + return; + + /* SKU ID 1, 3 doesn't have a eMMC device, hence disable it. */ + sku_id = get_board_sku(); + if (sku_id == 1 || sku_id == 3) + emmc_host->enabled = 0; } diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 88c1d7b14c..53a58c9df7 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -24,7 +24,9 @@ static const struct pad_config gpio_table[] = { /* A6 : SERIRQ ==> NC */ PAD_NC(GPP_A6, NONE), /* A10 : PEN_RESET_ODL */ - PAD_CFG_GPO(GPP_A10, 0, DEEP), + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A16 : EMR_GARAGE_DET (notification) */ + PAD_CFG_GPI_APIC(GPP_A16, NONE, PLTRST, LEVEL, NONE), /* A17 : PIRQA# ==> NC */ PAD_NC(GPP_A17, NONE), /* A18 : ISH_GP0 ==> NC */ @@ -39,18 +41,16 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_B8, NONE), /* C1 : SMBDATA: NC */ PAD_NC(GPP_C1, NONE), - /* - * C12 : EMR_GARAGE_INT - * The same signal is routed to both A8 and C12. Currently C12 - * is the interrupt source, and A8 is the wake source. - * Hoping that GPP_A8 can be used for both interrupt (SCI) and wake - * (GPIO). Keeping as GPI for now. - */ - PAD_CFG_GPI_SCI(GPP_C12, NONE, DEEP, EDGE_SINGLE, INVERT), - /* C15 : EN_PP3300_TSP_DIG_DX */ + /* C7 : PEN_IRQ_OD_L */ + PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, INVERT), + /* C12 : EN_PP3300_TSP_DX */ + PAD_CFG_GPO(GPP_C12, 0, DEEP), + /* C15 : EN_PP3300_DIG_DX */ PAD_CFG_GPO(GPP_C15, 0, DEEP), /* C23 : UART2_CTS# ==> NC */ PAD_NC(GPP_C23, NONE), + /* D16 : TOUCHSCREEN_INT_L */ + PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT), /* E23 : GPP_E23 ==> NC */ PAD_NC(GPP_E23, NONE), /* F1 : GPP_F1 ==> NC */ @@ -69,6 +69,10 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_G5, NONE), /* G6 : GPP_G6 ==> NC */ PAD_NC(GPP_G6, NONE), + /* H4 : PCH_I2C_PEN_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : PCH_I2C_PEN_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), }; const struct pad_config *override_gpio_table(size_t *num) @@ -77,12 +81,39 @@ const struct pad_config *override_gpio_table(size_t *num) return gpio_table; } -/* GPIOs configured before ramstage */ +/* + * GPIOs configured before ramstage + * Note: the Hatch platform's romstage will configure + * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins + * as inputs before it reads them, so they are not + * needed in this table. + */ static const struct pad_config early_gpio_table[] = { - PAD_NC(GPP_C23, NONE), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), }; -const struct pad_config *override_early_gpio_table(size_t *num) +const struct pad_config *variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl index f1f09438fa..06df7b178f 100644 --- a/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl @@ -13,4 +13,57 @@ * GNU General Public License for more details. */ -#include +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 105 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 49 +#define DPTF_TSR0_CRITICAL 75 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 75 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 94, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 8000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 250 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 51000, /* PowerLimitMinimum */ + 51000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 18cc1d4b36..13025c83f7 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -1,4 +1,7 @@ chip soc/intel/cannonlake + register "tdp_pl1_override" = "8" + register "tdp_pl2_override" = "51" + register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -29,15 +32,21 @@ chip soc/intel/cannonlake register "common_soc_config" = "{ .i2c[0] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 135, + .fall_time_ns = 45, }, .i2c[1] = { .speed = I2C_SPEED_FAST, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 95, + .fall_time_ns = 55, }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 100, + .fall_time_ns = 20, }, .gspi[0] = { .speed_mhz = 1, @@ -72,17 +81,47 @@ chip soc/intel/cannonlake end end # I2C 0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ATML0001"" + register "desc" = ""Atmel Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "91" # 90.5 ms + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)" + register "enable_delay_ms" = "1" # 90 ns + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + device i2c 4b on end + end + end # I2C #1 + device pci 15.2 on chip drivers/i2c/hid register "generic.hid" = ""WCOM50C1"" register "generic.desc" = ""WCOM Digitizer"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A10)" - register "generic.reset_delay_ms" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C15)" + # TODO: We can't use GPP_A10 as reset_gpio due to its voltage level, + # so we need to reassign it or remove it. + #register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A10)" + #register "generic.reset_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0x09 on end end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + # GPP_A16 is the IRQ source, and GPP_A8 is the wake source + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_A16)" + register "key.wake" = "GPE0_DW0_08" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end end # I2C #2 device pci 19.0 on chip drivers/i2c/da7219 @@ -108,5 +147,15 @@ chip soc/intel/cannonlake # No PCIe WiFi device pci 1d.5 off end + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" + device spi 1 on end + end # FPMCU + end # GSPI #1 end # domain end diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index 2b72cae036..f2db756e5e 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -28,9 +29,6 @@ #define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1 -#if ENV_RAMSTAGE -#include - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -44,36 +42,23 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif int get_write_protect_state(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; } int get_recovery_mode_switch(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; } void init_bootmode_straps(void) { u32 flags = 0; -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ if (get_gpio(GPIO_SPI_WP)) @@ -85,7 +70,7 @@ void init_bootmode_straps(void) /* Developer: Virtual */ - pci_write_config32(dev, SATA_SP, flags); + pci_s_write_config32(dev, SATA_SP, flags); } static const struct cros_gpio cros_gpios[] = { diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 3398902b38..b675f33fc5 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -64,6 +64,7 @@ config VARIANT_DIR default "careena" if BOARD_GOOGLE_CAREENA default "grunt" if BOARD_GOOGLE_GRUNT default "liara" if BOARD_GOOGLE_LIARA + default "treeya" if BOARD_GOOGLE_TREEYA config MAINBOARD_PART_NUMBER string @@ -116,6 +117,7 @@ config GBB_HWID default "CAREENA TEST 8777" if BOARD_GOOGLE_CAREENA default "GRUNT TEST 8296" if BOARD_GOOGLE_GRUNT default "LIARA TEST 0464" if BOARD_GOOGLE_LIARA + default "TREEYA TEST 0307" if BOARD_GOOGLE_TREEYA config AMD_FWM_POSITION_INDEX int diff --git a/src/mainboard/google/kahlee/Kconfig.name b/src/mainboard/google/kahlee/Kconfig.name index c9401be585..03d7baa1b4 100644 --- a/src/mainboard/google/kahlee/Kconfig.name +++ b/src/mainboard/google/kahlee/Kconfig.name @@ -12,3 +12,6 @@ config BOARD_GOOGLE_GRUNT config BOARD_GOOGLE_LIARA bool "-> Liara" select BOARD_GOOGLE_BASEBOARD_KAHLEE +config BOARD_GOOGLE_TREEYA + bool "-> Treeya" + select BOARD_GOOGLE_BASEBOARD_KAHLEE diff --git a/src/mainboard/google/kahlee/variants/treeya/Makefile.inc b/src/mainboard/google/kahlee/variants/treeya/Makefile.inc new file mode 100644 index 0000000000..0579e1899f --- /dev/null +++ b/src/mainboard/google/kahlee/variants/treeya/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Google, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +subdirs-y += ../baseboard/spd + +romstage-y += ../baseboard/romstage.c + +ramstage-y += ../baseboard/mainboard.c diff --git a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb new file mode 100644 index 0000000000..d73c47c6b8 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb @@ -0,0 +1,170 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip soc/amd/stoneyridge + register "spd_addr_lookup" = " + { + { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 + }" + register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" + register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" + register "uma_size" = "16 * MiB" + register "stapm_percent" = "80" + register "stapm_time_ms" = "2500000" + register "stapm_power_mw" = "7800" + + # Enable I2C0 for audio, USB3 hub at 400kHz + register "i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 95, + .fall_time_ns = 3, + }" + + # Enable I2C1 for H1 at 400kHz + register "i2c[1]" = "{ + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 62, + .fall_time_ns = 2, + }" + + # Enable I2C2 for trackpad, pen at 400kHz + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 170, + .fall_time_ns = 91, + }" + + # Enable I2C3 for touchscreen at 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 84, + .fall_time_ns = 50, + }" + + register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ + GPIO_I2C2_SCL | GPIO_I2C3_SCL" + + device cpu_cluster 0 on + device lapic 10 on end + end + device domain 0 on + device pci 0.0 on end # Root Complex + device pci 0.2 off end # IOMMU (Disabled for performance and battery) + device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # + device pci 2.2 on end # + device pci 2.3 on end # + device pci 2.4 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end + end # + device pci 2.5 on end # + device pci 8.0 on end # PSP + device pci 9.0 on end # PCIe Host Bridge + device pci 9.2 on end # HDA + device pci 10.0 on end # xHCI + device pci 11.0 off end # SATA + device pci 12.0 on end # EHCI + device pci 14.0 on # SMbus + end # SMbus + device pci 14.3 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC + device pci 14.7 on end # SD + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #domain + device mmio 0xfedc2000 on + chip drivers/generic/adau7002 + device generic 0.0 on end + end + chip drivers/i2c/da7219 + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_14)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + register "mclk_name" = ""oscout1"" + device i2c 1a on end + end + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_119)" + register "sdmode_delay" = "5" + device generic 0.1 on end + end + end + device mmio 0xfedc3000 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "desc" = ""Cr50 TPM"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + device i2c 50 on end + end + end + device mmio 0xfedc4000 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" + register "wake" = "7" + device i2c 15 on end + end + end + device mmio 0xfedc5000 on + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 39 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + end +end #chip soc/amd/stoneyridge diff --git a/src/mainboard/google/hatch/variants/hatch_whl/include/variant/ec.h b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/gpe.asl similarity index 82% rename from src/mainboard/google/hatch/variants/hatch_whl/include/variant/ec.h rename to src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/gpe.asl index 768987d225..0a08774206 100644 --- a/src/mainboard/google/hatch/variants/hatch_whl/include/variant/ec.h +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/gpe.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC + * Copyright (C) 2018 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,9 +13,4 @@ * GNU General Public License for more details. */ -#ifndef VARIANT_EC_H -#define VARIANT_EC_H - -#include - -#endif +#include diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..4f91d72822 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/mainboard.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/routing.asl b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/routing.asl new file mode 100644 index 0000000000..233494f51e --- /dev/null +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/routing.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/sleep.asl new file mode 100644 index 0000000000..c5a1557962 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/sleep.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/thermal.asl new file mode 100644 index 0000000000..77137bb903 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/thermal.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h b/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h new file mode 100644 index 0000000000..96388ae5e0 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h @@ -0,0 +1,4 @@ +#include + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT diff --git a/src/mainboard/google/hatch/variants/hatch_whl/include/variant/acpi/dptf.asl b/src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h similarity index 77% rename from src/mainboard/google/hatch/variants/hatch_whl/include/variant/acpi/dptf.asl rename to src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h index f1f09438fa..5a6b54044f 100644 --- a/src/mainboard/google/hatch/variants/hatch_whl/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2019 Google LLC + * Copyright (C) 2017 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -9,8 +9,8 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include +#include diff --git a/src/soc/intel/broadwell/stage_cache.c b/src/mainboard/google/kahlee/variants/treeya/include/variant/thermal.h similarity index 53% rename from src/soc/intel/broadwell/stage_cache.c rename to src/mainboard/google/kahlee/variants/treeya/include/variant/thermal.h index dc59ab7756..1bb78efa2a 100644 --- a/src/soc/intel/broadwell/stage_cache.c +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/thermal.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,19 +14,25 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include +#ifndef THERMAL_H +#define THERMAL_H -void stage_cache_external_region(void **base, size_t *size) -{ - /* The ramstage cache lives in the TSEG region. - * The top of RAM is defined to be the TSEG base address. */ - u32 offset = smm_region_size(); - offset -= CONFIG_IED_REGION_SIZE; - offset -= CONFIG_SMM_RESERVED_SIZE; +/* + * Stoney Ridge Thermal Requirements 12 (6W) + * TDP (W) 6 + * T die,max (°C) 95 + * T ctl,max 85 + * T die,lmt (default) 90 + * T ctl,lmt (default) 80 + */ - *base = (void *)(cbmem_top() + offset); - *size = CONFIG_SMM_RESERVED_SIZE; -} +/* Control TDP Settings */ +#define CTL_TDP_SENSOR_ID 2 /* EC TIN2 */ + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 94 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 85 + +#endif diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 7719506421..863f49ee23 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -38,6 +38,9 @@ config BOARD_SPECIFIC_OPTIONS select EC_GOOGLE_CHROMEEC_SPI select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_FORCE_NATIVE_VGA_INIT + select HAVE_LINEAR_FRAMEBUFFER config MAINBOARD_DIR string @@ -47,7 +50,9 @@ config MAINBOARD_PART_NUMBER string default "Kukui" if BOARD_GOOGLE_KUKUI default "Krane" if BOARD_GOOGLE_KRANE + default "Kodama" if BOARD_GOOGLE_KODAMA default "Flapjack" if BOARD_GOOGLE_FLAPJACK + default "Jacuzzi" if BOARD_GOOGLE_JACUZZI config DRIVER_TPM_SPI_BUS hex @@ -66,6 +71,7 @@ config GBB_HWID depends on CHROMEOS default "KUKUI TEST 9847" if BOARD_GOOGLE_KUKUI default "KRANE TEST 5417" if BOARD_GOOGLE_KRANE + default "KODAMA TEST 7122" if BOARD_GOOGLE_KODAMA default "FLAPJACK TEST 4147" if BOARD_GOOGLE_FLAPJACK - + default "JACUZZI TEST 6792" if BOARD_GOOGLE_JACUZZI endif diff --git a/src/mainboard/google/kukui/Kconfig.name b/src/mainboard/google/kukui/Kconfig.name index 348be667ca..33049e38c2 100644 --- a/src/mainboard/google/kukui/Kconfig.name +++ b/src/mainboard/google/kukui/Kconfig.name @@ -8,6 +8,14 @@ config BOARD_GOOGLE_KRANE bool "-> Krane" select BOARD_GOOGLE_KUKUI_COMMON +config BOARD_GOOGLE_KODAMA + bool "-> Kodama" + select BOARD_GOOGLE_KUKUI_COMMON + config BOARD_GOOGLE_FLAPJACK bool "-> Flapjack" select BOARD_GOOGLE_KUKUI_COMMON + +config BOARD_GOOGLE_JACUZZI + bool "-> Jacuzzi" + select BOARD_GOOGLE_KUKUI_COMMON diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index 5931c79ecd..d8b3cc4c2f 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -21,8 +21,11 @@ static const char *const sdram_configs[] = { [1] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", [2] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", - [3] = "sdram-lpddr4x-KMDP6001DA-B425-4GB", + [3] = "sdram-lpddr4x-KMDH6001DA-B422-4GB", + [4] = "sdram-lpddr4x-KMDP6001DA-B425-4GB", [5] = "sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB", + [6] = "sdram-lpddr4x-KMDV6001DA-B620-4GB", + [7] = "sdram-lpddr4x-SDADA4CR-128G-4GB", }; static struct sdram_params params; diff --git a/src/mainboard/google/kukui/sdram_params/Makefile.inc b/src/mainboard/google/kukui/sdram_params/Makefile.inc index 77158a5c59..fbc505b588 100644 --- a/src/mainboard/google/kukui/sdram_params/Makefile.inc +++ b/src/mainboard/google/kukui/sdram_params/Makefile.inc @@ -1,8 +1,11 @@ sdram-params := sdram-params += sdram-lpddr4x-H9HCNNNCPMALHR-4GB sdram-params += sdram-lpddr4x-MT53E1G32D4NQ-4GB +sdram-params += sdram-lpddr4x-KMDH6001DA-B422-4GB sdram-params += sdram-lpddr4x-KMDP6001DA-B425-4GB sdram-params += sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB +sdram-params += sdram-lpddr4x-KMDV6001DA-B620-4GB +sdram-params += sdram-lpddr4x-SDADA4CR-128G-4GB $(foreach params,$(sdram-params), \ $(eval cbfs-files-y += $(params)) \ diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c new file mode 100644 index 0000000000..1e0c3628fd --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +struct sdram_params params = { + .impedance = { + [ODT_OFF] = {0x9, 0x7, 0x0, 0xF}, + [ODT_ON] = {0xA, 0x9, 0x0, 0xE} + }, + .wr_level = { + [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, + [CHANNEL_B] = { {0x1E, 0x1F}, {0x1D, 0x1E} } + }, + .cbt_cs = { + [CHANNEL_A] = {0x1, 0x1}, + [CHANNEL_B] = {0x2, 0x2} + }, + .cbt_mr12 = { + [CHANNEL_A] = {0x56, 0x56}, + [CHANNEL_B] = {0x58, 0x5C} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c index 1e0c3628fd..12acc61b3e 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c @@ -17,20 +17,20 @@ struct sdram_params params = { .impedance = { - [ODT_OFF] = {0x9, 0x7, 0x0, 0xF}, - [ODT_ON] = {0xA, 0x9, 0x0, 0xE} + [ODT_OFF] = {0x7, 0x6, 0x0, 0xF}, + [ODT_ON] = {0x8, 0x9, 0x0, 0xD} }, .wr_level = { - [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, - [CHANNEL_B] = { {0x1E, 0x1F}, {0x1D, 0x1E} } + [CHANNEL_A] = { {0x22, 0x21}, {0x20, 0x21} }, + [CHANNEL_B] = { {0x23, 0x27}, {0x23, 0x27} } }, .cbt_cs = { - [CHANNEL_A] = {0x1, 0x1}, - [CHANNEL_B] = {0x2, 0x2} + [CHANNEL_A] = {0x0, 0x0}, + [CHANNEL_B] = {0x6, 0x6} }, .cbt_mr12 = { - [CHANNEL_A] = {0x56, 0x56}, - [CHANNEL_B] = {0x58, 0x5C} + [CHANNEL_A] = {0x56, 0x5A}, + [CHANNEL_B] = {0x58, 0x58} }, .emi_cona_val = 0xF053F154, .emi_conh_val = 0x44440003, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c new file mode 100644 index 0000000000..8cc0d3d693 --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +struct sdram_params params = { + .impedance = { + [ODT_OFF] = {0x8, 0x7, 0x0, 0xF}, + [ODT_ON] = {0x9, 0x9, 0x0, 0xD} + }, + .wr_level = { + [CHANNEL_A] = { {0x21, 0x24}, {0x22, 0x24} }, + [CHANNEL_B] = { {0x24, 0x28}, {0x22, 0x27} } + }, + .cbt_cs = { + [CHANNEL_A] = {0xC, 0xC}, + [CHANNEL_B] = {0xB, 0xB} + }, + .cbt_mr12 = { + [CHANNEL_A] = {0x58, 0x58}, + [CHANNEL_B] = {0x56, 0x56} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c new file mode 100644 index 0000000000..61060d6fdc --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +struct sdram_params params = { + .impedance = { + [ODT_OFF] = {0x8, 0x7, 0x0, 0xF}, + [ODT_ON] = {0x9, 0x9, 0x0, 0xE} + }, + .wr_level = { + [CHANNEL_A] = { {0x1F, 0x1C}, {0x1C, 0x1B} }, + [CHANNEL_B] = { {0x27, 0x28}, {0x23, 0x28} } + }, + .cbt_cs = { + [CHANNEL_A] = {0x3, 0x3}, + [CHANNEL_B] = {0x4, 0x6} + }, + .cbt_mr12 = { + [CHANNEL_A] = {0x5C, 0x5A}, + [CHANNEL_B] = {0x5C, 0x5A} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 1b27a69b54..ec7fb201d7 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -64,7 +64,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "1" - register "p_cnt_throttling_supported" = "0" device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/google/link/gpio.c b/src/mainboard/google/link/gpio.c index dcd29a33c6..035cf6da3f 100644 --- a/src/mainboard/google/link/gpio.c +++ b/src/mainboard/google/link/gpio.c @@ -18,7 +18,7 @@ #include -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */ .gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */ .gpio5 = GPIO_MODE_GPIO, /* SIM_DET */ @@ -35,7 +35,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */ }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio3 = GPIO_DIR_INPUT, .gpio5 = GPIO_DIR_INPUT, @@ -52,13 +52,13 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio28 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio1 = GPIO_LEVEL_HIGH, .gpio6 = GPIO_LEVEL_HIGH, .gpio24 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio7 = GPIO_INVERT, .gpio8 = GPIO_INVERT, .gpio12 = GPIO_INVERT, @@ -66,7 +66,7 @@ const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio15 = GPIO_INVERT, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */ .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */ .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */ @@ -75,7 +75,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio36 = GPIO_DIR_OUTPUT, .gpio41 = GPIO_DIR_INPUT, .gpio42 = GPIO_DIR_INPUT, @@ -84,18 +84,18 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio60 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio36 = GPIO_LEVEL_HIGH, .gpio60 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { }; const struct pch_gpio_map mainboard_gpio_map = { diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index fde2bd00e1..0dce17d40d 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -226,25 +226,21 @@ static void display_startup(void) struct edid edid; int ret; u32 mipi_dsi_flags; - bool dual_dsi_mode; if (read_edid_from_ps8640(&edid) < 0) return; - dual_dsi_mode = false; mipi_dsi_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE; edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); - mtk_ddp_init(dual_dsi_mode); - ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, - dual_dsi_mode, &edid); + mtk_ddp_init(); + ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, &edid); if (ret < 0) { printk(BIOS_ERR, "dsi init fail\n"); return; } - mtk_ddp_mode_set(&edid, dual_dsi_mode); - + mtk_ddp_mode_set(&edid); set_vbe_mode_info_valid(&edid, (uintptr_t)0); } diff --git a/src/mainboard/google/octopus/bootblock.c b/src/mainboard/google/octopus/bootblock.c index 0c239db369..4da3e94b83 100644 --- a/src/mainboard/google/octopus/bootblock.c +++ b/src/mainboard/google/octopus/bootblock.c @@ -21,8 +21,8 @@ void bootblock_mainboard_init(void) { - const struct pad_config *pads; - size_t num; + const struct pad_config *pads, *override_pads; + size_t num, override_num; lpc_configure_pads(); @@ -34,5 +34,7 @@ void bootblock_mainboard_init(void) mainboard_ec_init(); pads = variant_early_gpio_table(&num); - gpio_configure_pads(pads, num); + override_pads = variant_early_override_gpio_table(&override_num); + gpio_configure_pads_with_override(pads, num, + override_pads, override_num); } diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index 91cf1e4b70..3312d4d988 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -16,12 +16,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include #include #include @@ -199,3 +201,16 @@ const char *smbios_mainboard_manufacturer(void) return manuf; } + +bool __weak variant_ext_usb_status(unsigned int port_type, unsigned int port_id) +{ + /* All externally visible USB ports are present */ + return true; +} + +static void disable_unused_devices(void *unused) +{ + usb_xhci_disable_unused(variant_ext_usb_status); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, disable_unused_devices, NULL); diff --git a/src/mainboard/google/octopus/smihandler.c b/src/mainboard/google/octopus/smihandler.c index 27928eec0f..855c9825e8 100644 --- a/src/mainboard/google/octopus/smihandler.c +++ b/src/mainboard/google/octopus/smihandler.c @@ -39,6 +39,8 @@ void mainboard_smi_sleep(u8 slp_typ) pads = variant_sleep_gpio_table(&num, slp_typ); gpio_configure_pads(pads, num); + variant_smi_sleep(slp_typ); + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); } @@ -60,3 +62,8 @@ void elog_gsmi_cb_mainboard_log_wake_source(void) google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S0IX_WAKE_EVENTS); } + +void __weak variant_smi_sleep(u8 slp_typ) +{ + /* Leave for the variant to implement if necessary. */ +} diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index fc609cd125..8f8507046e 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -148,18 +148,86 @@ chip soc/intel/apollolake register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.1 on end + end chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_109)" device usb 2.2 on end end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""SDCard"" + register "type" = "UPC_TYPE_EXPRESSCARD" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""User Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""World Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.7 on end + end chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_109)" device usb 2.8 on end end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""SDCard"" + register "type" = "UPC_TYPE_EXPRESSCARD" + device usb 3.5 on end + end end end end # - XHCI diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index febf7792e7..b3145d10df 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -299,6 +299,12 @@ const struct pad_config *__weak variant_override_gpio_table(size_t *num) return NULL; } +const struct pad_config *__weak variant_early_override_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */ @@ -325,6 +331,19 @@ static const struct pad_config early_gpio_table[] = { */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF2, HIZCRx1, ENPU), /* ESPI_IO1 */ + + /* GPIO_67 and GPIO_117 are in early_gpio_table and gpio_table. For variants + * having LTE SKUs, these two GPIOs would be overridden to output high first + * in the bootblock then be set to default state in gpio_table for non-LTE + * SKUs and keep to output high for LTE SKUs in ramstage. + */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, TxLASTRxE, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ + PAD_CFG_GPI_SCI_LOW(GPIO_117, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE1_B -- LTE_WAKE_L */ + /* GPIO_161 is in early_gpio_table and gpio_table because LTE SKU needs + * to override this pin to output low then high respectively in two + * stages. + */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, Tx1RxDCRx0, DISPUPD), /* AVS_I2S1_MCLK -- LTE_OFF_ODL */ }; const struct pad_config *__weak diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h index 5374ace795..2132db591d 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h @@ -26,6 +26,7 @@ const struct pad_config *variant_base_gpio_table(size_t *num); const struct pad_config *variant_override_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); +const struct pad_config *variant_early_override_gpio_table(size_t *num); const struct pad_config *variant_sleep_gpio_table(size_t *num, int slp_typ); /* Baseboard default swizzle. Can be reused if swizzle is same. */ @@ -46,8 +47,22 @@ void variant_nhlt_init(struct nhlt *nhlt); /* Modify devictree settings during ramstage. */ struct device; void variant_update_devtree(struct device *dev); +/** + * variant_ext_usb_status() - Get status of externally visible USB ports + * @port_type: Type of USB port i.e. USB2/USB3 + * @port_id: USB Port ID + * + * This function is supplied by the mainboard/variant to SoC's XHCI driver to + * identify the status of externally visible USB ports. + * + * Return: true if the port is present, false if the port is absent. + */ +bool variant_ext_usb_status(unsigned int port_type, unsigned int port_id); /* Get no touchscreen SKU ID. */ bool no_touchscreen_sku(uint32_t sku_id); +/* allow each variants to customize smi sleep flow. */ +void variant_smi_sleep(u8 slp_typ); + #endif /* BASEBOARD_VARIANTS_H */ diff --git a/src/mainboard/google/octopus/variants/bobba/Makefile.inc b/src/mainboard/google/octopus/variants/bobba/Makefile.inc index 9fb63f5f43..ba865e9f82 100644 --- a/src/mainboard/google/octopus/variants/bobba/Makefile.inc +++ b/src/mainboard/google/octopus/variants/bobba/Makefile.inc @@ -1,3 +1,4 @@ bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/cpu/intel/haswell/stage_cache.c b/src/mainboard/google/octopus/variants/bobba/variant.c similarity index 57% rename from src/cpu/intel/haswell/stage_cache.c rename to src/mainboard/google/octopus/variants/bobba/variant.c index 009cc09ba6..05a331a1eb 100644 --- a/src/cpu/intel/haswell/stage_cache.c +++ b/src/mainboard/google/octopus/variants/bobba/variant.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 Google, Inc. + * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,14 +13,17 @@ * GNU General Public License for more details. */ -#include -#include -#include "haswell.h" +#include +#include -void stage_cache_external_region(void **base, size_t *size) +const char *get_wifi_sar_cbfs_filename(void) { - /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. */ - *size = RESERVED_SMM_SIZE; - *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); + const char *filename = NULL; + uint32_t sku_id = get_board_sku(); + + if (sku_id == 33 || sku_id == 34 || sku_id == 35 || sku_id == 36 || sku_id == 41 || + sku_id == 42 || sku_id == 43 || sku_id == 44) + filename = "wifi_sar-droid.hex"; + + return filename; } diff --git a/src/mainboard/google/octopus/variants/casta/overridetree.cb b/src/mainboard/google/octopus/variants/casta/overridetree.cb index 091b3027f4..2f2f80bd28 100644 --- a/src/mainboard/google/octopus/variants/casta/overridetree.cb +++ b/src/mainboard/google/octopus/variants/casta/overridetree.cb @@ -83,6 +83,32 @@ chip soc/intel/apollolake }" device domain 0 on + device pci 15.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.1 on end + end + chip drivers/usb/acpi + device usb 2.3 off end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.1 on end + end + chip drivers/usb/acpi + device usb 3.3 off end + end + end + end + end # - XHCI device pci 17.1 on chip drivers/i2c/da7219 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" diff --git a/src/mainboard/google/octopus/variants/casta/variant.c b/src/mainboard/google/octopus/variants/casta/variant.c index 89b1033886..12c8dd747b 100644 --- a/src/mainboard/google/octopus/variants/casta/variant.c +++ b/src/mainboard/google/octopus/variants/casta/variant.c @@ -16,6 +16,8 @@ #include #include +#define RIGHT_USB_C_PORT_ID 4 + const char *get_wifi_sar_cbfs_filename(void) { const char *filename = NULL; @@ -26,3 +28,12 @@ const char *get_wifi_sar_cbfs_filename(void) return filename; } + +bool variant_ext_usb_status(unsigned int port_type, unsigned int port_id) +{ + uint32_t sku_id = get_board_sku(); + + if (sku_id == 2 && port_id == RIGHT_USB_C_PORT_ID) + return false; + return true; +} diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index d2d0d641dc..a1e02d2159 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -21,8 +21,6 @@ static const struct pad_config default_override_table[] = { - PAD_NC(GPIO_50, UP_20K), - PAD_NC(GPIO_51, UP_20K), PAD_NC(GPIO_52, UP_20K), PAD_NC(GPIO_53, UP_20K), PAD_NC(GPIO_67, UP_20K), diff --git a/src/mainboard/google/octopus/variants/garg/gpio.c b/src/mainboard/google/octopus/variants/garg/gpio.c index 90601ce850..36fde90631 100644 --- a/src/mainboard/google/octopus/variants/garg/gpio.c +++ b/src/mainboard/google/octopus/variants/garg/gpio.c @@ -50,6 +50,28 @@ static const struct pad_config hdmi_override_table[] = { DISPUPD), PAD_NC(GPIO_213, DN_20K), + +}; + +static const struct pad_config lte_override_table[] = { + /* Default override table. */ + PAD_NC(GPIO_104, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_213, DN_20K), + + /* Be specific to LTE SKU */ + /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ + PAD_CFG_GPO(GPIO_67, 1, PWROK), + + /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ + PAD_CFG_GPO(GPIO_117, 1, PWROK), + + /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ + PAD_CFG_GPO(GPIO_161, 1, DEEP), }; const struct pad_config *variant_override_gpio_table(size_t *num) @@ -61,8 +83,29 @@ const struct pad_config *variant_override_gpio_table(size_t *num) case SKU_9_HDMI: *num = ARRAY_SIZE(hdmi_override_table); return hdmi_override_table; + case SKU_17_LTE: + *num = ARRAY_SIZE(lte_override_table); + return lte_override_table; default: *num = ARRAY_SIZE(default_override_table); return default_override_table; } } + +static const struct pad_config lte_early_override_table[] = { + /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ + PAD_CFG_GPO(GPIO_67, 1, PWROK), + + /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ + PAD_CFG_GPO(GPIO_117, 1, PWROK), + + /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ + PAD_CFG_GPO(GPIO_161, 0, DEEP), +}; + +const struct pad_config *variant_early_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(lte_early_override_table); + + return lte_early_override_table; +} diff --git a/src/mainboard/google/octopus/variants/garg/variant.c b/src/mainboard/google/octopus/variants/garg/variant.c index a3efe3f802..2754e640f9 100644 --- a/src/mainboard/google/octopus/variants/garg/variant.c +++ b/src/mainboard/google/octopus/variants/garg/variant.c @@ -13,10 +13,13 @@ * GNU General Public License for more details. */ +#include #include #include #include #include +#include +#include enum { SKU_1_2A2C = 1, @@ -24,6 +27,34 @@ enum { SKU_17_LTE = 17, }; +struct gpio_with_delay { + gpio_t gpio; + unsigned int delay_msecs; +}; + +static void power_off_lte_module(u8 slp_typ) +{ + const struct gpio_with_delay lte_power_off_gpios[] = { + { + GPIO_161, /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ + 30, + }, + { + GPIO_117, /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ + 100 + }, + { + GPIO_67, /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ + 0 + } + }; + + for (int i = 0; i < ARRAY_SIZE(lte_power_off_gpios); i++) { + gpio_output(lte_power_off_gpios[i].gpio, 0); + mdelay(lte_power_off_gpios[i].delay_msecs); + } +} + const char *mainboard_vbt_filename(void) { uint32_t sku_id; @@ -37,3 +68,19 @@ const char *mainboard_vbt_filename(void) return "vbt.bin"; } } + +void variant_smi_sleep(u8 slp_typ) +{ + /* Currently use cases here all target to S5 therefore we do early return + * here for saving one transaction to the EC for getting SKU ID. */ + if (slp_typ != ACPI_S5) + return; + + switch (get_board_sku()) { + case SKU_17_LTE: + power_off_lte_module(slp_typ); + return; + default: + return; + } +} diff --git a/src/mainboard/google/octopus/variants/meep/Makefile.inc b/src/mainboard/google/octopus/variants/meep/Makefile.inc index 9fb63f5f43..ba865e9f82 100644 --- a/src/mainboard/google/octopus/variants/meep/Makefile.inc +++ b/src/mainboard/google/octopus/variants/meep/Makefile.inc @@ -1,3 +1,4 @@ bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/octopus/variants/meep/gpio.c b/src/mainboard/google/octopus/variants/meep/gpio.c index 7b47bf1217..44d9fff129 100644 --- a/src/mainboard/google/octopus/variants/meep/gpio.c +++ b/src/mainboard/google/octopus/variants/meep/gpio.c @@ -17,6 +17,7 @@ #include #include #include +#include static const struct pad_config default_override_table[] = { PAD_NC(GPIO_104, UP_20K), @@ -26,8 +27,34 @@ static const struct pad_config default_override_table[] = { DISPUPD), }; +static const struct pad_config hdmi_sku_override_table[] = { + PAD_NC(GPIO_104, UP_20K), + + /* HV_DDI1_DDC_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_126, NONE, DEEP, NF1, HIZCRx1, + DISPUPD), + /* HV_DDI1_DDC_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_127, NONE, DEEP, NF1, HIZCRx1, + DISPUPD), + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), +}; + const struct pad_config *variant_override_gpio_table(size_t *num) { - *num = ARRAY_SIZE(default_override_table); - return default_override_table; + uint32_t sku_id; + sku_id = get_board_sku(); + + switch (sku_id) { + case SKU_33_DORP: + case SKU_34_DORP: + case SKU_35_DORP: + case SKU_36_DORP: + *num = ARRAY_SIZE(hdmi_sku_override_table); + return hdmi_sku_override_table; + default: + *num = ARRAY_SIZE(default_override_table); + return default_override_table; + } } diff --git a/src/mainboard/google/octopus/variants/meep/include/variant/ec.h b/src/mainboard/google/octopus/variants/meep/include/variant/ec.h index 16f931b6cd..196d52e3e9 100644 --- a/src/mainboard/google/octopus/variants/meep/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/meep/include/variant/ec.h @@ -18,4 +18,7 @@ #include +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + #endif diff --git a/src/mainboard/google/octopus/variants/meep/include/variant/sku.h b/src/mainboard/google/octopus/variants/meep/include/variant/sku.h new file mode 100644 index 0000000000..16a4eabecc --- /dev/null +++ b/src/mainboard/google/octopus/variants/meep/include/variant/sku.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_SKU_H__ +#define __MAINBOARD_SKU_H__ + +enum { + SKU_4_VORTININJA = 4, /* Stylus + rear camera */ + SKU_5_VORTININJA = 5, /* Stylus + no rear camera */ + SKU_6_VORTININJA = 6, /* no Stylus + rear camera */ + SKU_7_VORTININJA = 7, /* no Stylus + no rear camera */ + SKU_33_DORP = 33, /* HDMI */ + SKU_34_DORP = 34, /* HDMI+Kblight */ + SKU_35_DORP = 35, /* HDMI+TS */ + SKU_36_DORP = 36, /* HDMI+TS+KBlight */ +}; + +#endif /* __MAINBOARD_SKU_H__ */ diff --git a/src/mainboard/google/octopus/variants/meep/overridetree.cb b/src/mainboard/google/octopus/variants/meep/overridetree.cb index c639b733f1..d7bdd2e936 100644 --- a/src/mainboard/google/octopus/variants/meep/overridetree.cb +++ b/src/mainboard/google/octopus/variants/meep/overridetree.cb @@ -83,6 +83,62 @@ chip soc/intel/apollolake }" device domain 0 on + device pci 15.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.4 on end + end + end + end + end # - XHCI device pci 16.0 on chip drivers/i2c/hid register "generic.hid" = ""WCOM50C1"" @@ -91,9 +147,21 @@ chip soc/intel/apollolake register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" register "generic.reset_delay_ms" = "20" register "generic.has_power_resource" = "1" + register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0x9 on end end + chip drivers/i2c/hid + register "generic.hid" = ""EMRTE635"" + register "generic.desc" = ""EMRIGHT Digitizer"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0xa on end + end end # - I2C 0 device pci 17.1 on chip drivers/i2c/da7219 diff --git a/src/mainboard/google/octopus/variants/meep/variant.c b/src/mainboard/google/octopus/variants/meep/variant.c new file mode 100644 index 0000000000..ece8ff955a --- /dev/null +++ b/src/mainboard/google/octopus/variants/meep/variant.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +const char *get_wifi_sar_cbfs_filename(void) +{ + const char *filename = NULL; + uint32_t sku_id = get_board_sku(); + + switch (sku_id) { + case SKU_4_VORTININJA: + case SKU_5_VORTININJA: + case SKU_6_VORTININJA: + case SKU_7_VORTININJA: + filename = "wifi_sar-vortininja.hex"; + break; + } + return filename; +} + +const char *mainboard_vbt_filename(void) +{ + uint32_t sku_id; + + sku_id = get_board_sku(); + + switch (sku_id) { + case SKU_33_DORP: + case SKU_34_DORP: + case SKU_35_DORP: + case SKU_36_DORP: + return "vbt_dorp_hdmi.bin"; + default: + return "vbt.bin"; + } +} diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 095d5049ed..4adcdb6b08 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -26,14 +27,10 @@ #include #include "ec.h" - -#if ENV_RAMSTAGE -#include - void fill_lb_gpios(struct lb_gpios *gpios) { - struct device *dev = pcidev_on_root(0x1f, 0); - u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); struct lb_gpio chromeos_gpios[] = { /* Write Protect: GPIO70 active high */ @@ -51,7 +48,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif int get_lid_switch(void) { diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index 046db97585..33d3544264 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -62,7 +62,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "1" - register "p_cnt_throttling_supported" = "0" device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/google/parrot/gpio.c b/src/mainboard/google/parrot/gpio.c index 8ad18f1f51..359b6ecc6d 100644 --- a/src/mainboard/google/parrot/gpio.c +++ b/src/mainboard/google/parrot/gpio.c @@ -18,7 +18,7 @@ #include -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_NONE, /* NOT USED */ .gpio1 = GPIO_MODE_NONE, /* NOT USED */ .gpio2 = GPIO_MODE_NATIVE, /* NOT USED / PIRQE# */ @@ -53,7 +53,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio31 = GPIO_MODE_NATIVE, /* ACPRESENT */ }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -88,7 +88,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio31 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_LOW, .gpio1 = GPIO_LEVEL_LOW, .gpio2 = GPIO_LEVEL_LOW, @@ -123,14 +123,14 @@ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio31 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio7 = GPIO_INVERT, .gpio8 = GPIO_INVERT, .gpio12 = GPIO_INVERT, .gpio15 = GPIO_INVERT, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */ .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */ .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */ @@ -139,7 +139,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, .gpio33 = GPIO_DIR_INPUT, .gpio34 = GPIO_DIR_INPUT, @@ -174,7 +174,7 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio63 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_LOW, .gpio33 = GPIO_LEVEL_LOW, .gpio34 = GPIO_LEVEL_LOW, @@ -209,7 +209,7 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio63 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX0 */ .gpio65 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX1 */ .gpio66 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX2 */ @@ -224,7 +224,7 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio75 = GPIO_MODE_NATIVE, /* SML1DATA */ }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_INPUT, .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, @@ -239,7 +239,7 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio75 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_LOW, .gpio65 = GPIO_LEVEL_LOW, .gpio66 = GPIO_LEVEL_LOW, diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index 3879732135..84b0031654 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -15,14 +15,13 @@ #include #include +#include #include #include #include #include -#if ENV_RAMSTAGE -#include void fill_lb_gpios(struct lb_gpios *gpios) { @@ -36,7 +35,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */ int get_write_protect_state(void) { diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 7fcb3b8b3e..ac86e79f22 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -64,7 +64,6 @@ chip soc/intel/skylake register "tdp_pl2_override" = "15" register "psys_pmax" = "45" register "tcc_offset" = "10" - register "pch_trip_temp" = "75" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" @@ -182,6 +181,7 @@ chip soc/intel/skylake #| I2C2 | Trackpad | #| I2C3 | Camera | #| I2C4 | Audio | + #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, @@ -217,6 +217,7 @@ chip soc/intel/skylake .speed_mhz = 1, .early_init = 1, }, + .pch_thermal_trip = 75, }" # Touchscreen register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" diff --git a/src/mainboard/google/poppy/variants/atlas/mainboard.c b/src/mainboard/google/poppy/variants/atlas/mainboard.c index 07a4e66c1f..9c4b2bc75d 100644 --- a/src/mainboard/google/poppy/variants/atlas/mainboard.c +++ b/src/mainboard/google/poppy/variants/atlas/mainboard.c @@ -25,8 +25,10 @@ static uint32_t get_pl2(void) { + struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); uint16_t id; - id = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID); + + id = pci_read_config16(igd_dev, PCI_DEVICE_ID); /* Assume we only have KLB-Y and AML-Y SKUs */ if (id == PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM) return PL2_KBL; @@ -37,8 +39,7 @@ static uint32_t get_pl2(void) /* Override dev tree settings per board */ void variant_devtree_update(void) { - struct device *root = SA_DEV_ROOT; - config_t *cfg = root->chip_info; + config_t *cfg = config_of_path(SA_DEVFN_ROOT); /* Update PL2 based on CPU */ cfg->tdp_pl2_override = get_pl2(); diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 727a10f5f4..d9604746dd 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -177,6 +177,7 @@ chip soc/intel/skylake #| I2C3 | Pen | #| I2C4 | Camera | #| I2C5 | Audio | + #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, @@ -226,6 +227,7 @@ chip soc/intel/skylake .sda_hold = 36, }, }, + .pch_thermal_trip = 75, }" # Touchscreen @@ -270,9 +272,6 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_E15" - # PCH Trip Temperature in degree C - register "pch_trip_temp" = "75" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 7c11ea19c4..3d37eda207 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -219,6 +219,7 @@ chip soc/intel/skylake #| I2C1 | Trackpad | #| I2C2 | Pen | #| I2C3 | Audio | + #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, @@ -263,6 +264,7 @@ chip soc/intel/skylake .sda_hold = 36, }, }, + .pch_thermal_trip = 75, }" # Must leave UART0 enabled or SD/eMMC will not work as PCI @@ -285,9 +287,6 @@ chip soc/intel/skylake register "tcc_offset" = "3" # TCC of 97C register "psys_pmax" = "101" - # PCH Trip Temperature in degree C - register "pch_trip_temp" = "75" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index cd7e0ca0b1..d0f60741e3 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -470,6 +470,8 @@ const struct pad_config *variant_sku_gpio_table(size_t *num) case SKU_1_BARD: case SKU_2_BARD: case SKU_3_BARD: + case SKU_4_BARD: + case SKU_5_BARD: *num = ARRAY_SIZE(fpmcu_gpio_table); board_gpio_tables = fpmcu_gpio_table; break; diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/sku.h b/src/mainboard/google/poppy/variants/nami/include/variant/sku.h index 0ec85d0116..63c8928bab 100644 --- a/src/mainboard/google/poppy/variants/nami/include/variant/sku.h +++ b/src/mainboard/google/poppy/variants/nami/include/variant/sku.h @@ -48,6 +48,7 @@ #define SKU_1_BARD 0x1009CE3 #define SKU_2_BARD 0x1019CE1 #define SKU_3_BARD 0X1009CE1 - +#define SKU_4_BARD 0X1009CE0 +#define SKU_5_BARD 0X1009CE2 #endif /* __MAINBOARD_SKU_H__ */ diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index adb8c00579..f63c520013 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -212,6 +212,8 @@ const char *mainboard_vbt_filename(void) case SKU_1_BARD: case SKU_2_BARD: case SKU_3_BARD: + case SKU_4_BARD: + case SKU_5_BARD: return "vbt-bard.bin"; default: return "vbt.bin"; @@ -234,11 +236,11 @@ void variant_devtree_update(void) uint32_t sku_id = variant_board_sku(); uint32_t i; int oem_index; - struct device *root = SA_DEV_ROOT; - config_t *cfg = root->chip_info; uint8_t pl2_id = PL2_ID_DEFAULT; struct device *spi_fpmcu = PCH_DEV_GSPI1; + config_t *cfg = config_of_path(SA_DEVFN_ROOT); + switch (sku_id) { case SKU_0_SONA: case SKU_1_SONA: @@ -267,6 +269,8 @@ void variant_devtree_update(void) case SKU_1_BARD: case SKU_2_BARD: case SKU_3_BARD: + case SKU_4_BARD: + case SKU_5_BARD: case SKU_0_EKKO: case SKU_1_EKKO: case SKU_2_EKKO: diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 1e4133b4f7..ef5e8ad921 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -189,6 +189,7 @@ chip soc/intel/skylake #| I2C3 | Pen | #| I2C4 | Camera | #| I2C5 | Audio | + #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, @@ -247,6 +248,7 @@ chip soc/intel/skylake .sda_hold = 36, }, }, + .pch_thermal_trip = 75, }" # Touch Screen @@ -291,9 +293,6 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_E15" - # PCH Trip Temperature in degree C - register "pch_trip_temp" = "75" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/poppy/variants/nautilus/mainboard.c b/src/mainboard/google/poppy/variants/nautilus/mainboard.c index 6d9f2e99a9..9aa6b724dd 100644 --- a/src/mainboard/google/poppy/variants/nautilus/mainboard.c +++ b/src/mainboard/google/poppy/variants/nautilus/mainboard.c @@ -41,11 +41,11 @@ const char *smbios_system_sku(void) void variant_devtree_update(void) { uint32_t sku_id = variant_board_sku(); - struct device *root = SA_DEV_ROOT; - config_t *cfg = root->chip_info; uint16_t abase; uint32_t val32; + config_t *cfg = config_of_path(SA_DEVFN_ROOT); + switch (sku_id) { case SKU_0_NAUTILUS: /* Disable LTE module */ diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index bf1897c120..75fcf9c54f 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -67,7 +67,6 @@ chip soc/intel/skylake register "tdp_pl2_override" = "18" register "psys_pmax" = "45" register "tcc_offset" = "10" - register "pch_trip_temp" = "75" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" @@ -201,6 +200,7 @@ chip soc/intel/skylake #| I2C3 | Camera | #| I2C4 | Audio | #| I2C5 | Rear Camera & SAR | + #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, @@ -241,6 +241,7 @@ chip soc/intel/skylake .speed_mhz = 1, .early_init = 1, }, + .pch_thermal_trip = 75, }" # Touchscreen register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h b/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h index 46e848b710..dfb0f7449e 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h @@ -48,6 +48,7 @@ #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) #define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) diff --git a/src/mainboard/google/poppy/variants/nocturne/mainboard.c b/src/mainboard/google/poppy/variants/nocturne/mainboard.c index 28d3d1b24d..7b6b28b0ba 100644 --- a/src/mainboard/google/poppy/variants/nocturne/mainboard.c +++ b/src/mainboard/google/poppy/variants/nocturne/mainboard.c @@ -26,8 +26,10 @@ static uint32_t get_pl2(void) { + struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); uint16_t id; - id = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID); + + id = pci_read_config16(igd_dev, PCI_DEVICE_ID); /* Assume we only have KLB-Y and AML-Y SKUs */ if (id == PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM) return PL2_KBL; @@ -38,8 +40,7 @@ static uint32_t get_pl2(void) /* Override dev tree settings per board */ void variant_devtree_update(void) { - struct device *root = SA_DEV_ROOT; - config_t *cfg = root->chip_info; + config_t *cfg = config_of_path(SA_DEVFN_ROOT); /* Update PL2 based on CPU */ cfg->tdp_pl2_override = get_pl2(); diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 1f73a5903e..70a4667e9e 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -172,6 +172,7 @@ chip soc/intel/skylake #| I2C0 | Touchscreen | #| I2C1 | Trackpad | #| I2C5 | Audio | + #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, @@ -207,6 +208,7 @@ chip soc/intel/skylake .speed_mhz = 1, .early_init = 1, }, + .pch_thermal_trip = 75, }" # Touchscreen @@ -242,9 +244,6 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_E15" - # PCH Trip Temperature in degree C - register "pch_trip_temp" = "75" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 872e2e5d9a..4711b1f0ae 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -179,6 +179,7 @@ chip soc/intel/skylake #| I2C2 | Camera | #| I2C4 | Camera | #| I2C5 | Audio | + #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, @@ -228,6 +229,7 @@ chip soc/intel/skylake .sda_hold = 36, }, }, + .pch_thermal_trip = 75, }" # Touchscreen @@ -271,9 +273,6 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_E15" - # PCH Trip Temperature in degree C - register "pch_trip_temp" = "75" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 7aaf4015b5..6643d9b55d 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -22,8 +22,6 @@ #include #include #include -#include -#include enum rec_mode_state { REC_MODE_UNINITIALIZED, @@ -120,8 +118,7 @@ int get_lid_switch(void) void mainboard_prepare_cr50_reset(void) { -#if ENV_RAMSTAGE /* Ensure system powers up after CR50 reset */ - pmc_set_afterg3(MAINBOARD_POWER_STATE_ON); -#endif + if (ENV_RAMSTAGE) + pmc_soc_set_afterg3_en(true); } diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index cd1925840a..ebcf140b4c 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -164,6 +164,9 @@ chip soc/intel/cannonlake register "tcc_offset" = "1" + # PCH Thermal Trip Temperature in deg C + register "common_soc_config.pch_thermal_trip" = "77" + register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { @@ -316,7 +319,7 @@ chip soc/intel/cannonlake register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" - register "generic.reset_delay_ms" = "20" + register "generic.reset_delay_ms" = "120" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" register "generic.enable_delay_ms" = "55" register "generic.has_power_resource" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 739a849715..d3aab62a68 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -163,6 +163,9 @@ chip soc/intel/cannonlake register "tcc_offset" = "10" + # PCH Thermal Trip Temperature in deg C + register "common_soc_config.pch_thermal_trip" = "77" + register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 60c7a09249..ff247da471 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -26,9 +27,6 @@ #include "ec.h" #include -#if ENV_RAMSTAGE -#include - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -51,7 +49,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif int get_write_protect_state(void) { @@ -74,16 +71,14 @@ int get_lid_switch(void) */ int get_recovery_mode_switch(void) { -#ifdef __PRE_RAM__ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); -#else +#ifndef __PRE_RAM__ static int ec_in_rec_mode = 0; static int ec_rec_flag_good = 0; - struct device *dev = pcidev_on_root(0x1f, 0); #endif + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u8 reg8 = pci_s_read_config8(dev, GEN_PMCON_3); u8 ec_status = ec_read(EC_STATUS_REG); - u8 reg8 = pci_read_config8(dev, GEN_PMCON_3); printk(BIOS_SPEW,"%s: EC status:%#x RTC_BAT: %x\n", __func__, ec_status, reg8 & RTC_BATTERY_DEAD); diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index ddcf4e22d1..b9ccbf938c 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -73,7 +73,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "1" - register "p_cnt_throttling_supported" = "0" device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 diff --git a/src/mainboard/google/stout/gpio.c b/src/mainboard/google/stout/gpio.c index 43134ea264..014037e4b9 100644 --- a/src/mainboard/google/stout/gpio.c +++ b/src/mainboard/google/stout/gpio.c @@ -18,7 +18,7 @@ #include -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, /* GPIO0 */ .gpio1 = GPIO_MODE_GPIO, /* SIO_EXT_SMI# */ .gpio2 = GPIO_MODE_NONE, /* NOT USED */ @@ -53,7 +53,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio31 = GPIO_MODE_NATIVE, /* AC_PRESENT */ }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { /* * Note: Only gpio configured as "gpio" or "none" need to have the * direction configured. @@ -86,7 +86,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio29 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { /* * Note: Only gpio configured as "gpio" or "none" need to have the * level set. @@ -119,13 +119,13 @@ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio29 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, .gpio6 = GPIO_INVERT, .gpio8 = GPIO_INVERT, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, /* PCI_CLKRUN# */ .gpio33 = GPIO_MODE_GPIO, /* GPIO33 */ .gpio34 = GPIO_MODE_GPIO, /* CCD_ON */ @@ -160,7 +160,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio63 = GPIO_MODE_NATIVE, /* TP51 */ }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { /* * Note: Only gpio configured as "gpio" or "none" need to have the * direction configured. @@ -190,7 +190,7 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio61 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { /* * Note: Only gpio configured as "gpio" or "none" need to have the * level set. @@ -220,7 +220,7 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio61 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, /* CLK_FLEX0 / TP38 */ .gpio65 = GPIO_MODE_GPIO, /* CLK_FLEX1 / TP45 */ .gpio66 = GPIO_MODE_GPIO, /* CLK_FLEX2 / TP83 */ @@ -235,7 +235,7 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio75 = GPIO_MODE_NATIVE, /* SMB_ME1_DAT */ }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { /* * Note: Only gpio configured as "gpio" or "none" need to have the * direction configured. @@ -251,7 +251,7 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio72 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { /* * Note: Only gpio configured as "gpio" or "none" need to have the * level set. diff --git a/src/mainboard/hp/2570p/devicetree.cb b/src/mainboard/hp/2570p/devicetree.cb index 79a84b73c2..c638676e54 100644 --- a/src/mainboard/hp/2570p/devicetree.cb +++ b/src/mainboard/hp/2570p/devicetree.cb @@ -52,7 +52,6 @@ chip northbridge/intel/sandybridge register "gen3_dec" = "0x00fcfe01" register "gen4_dec" = "0x000402e9" register "gpi6_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/hp/2760p/devicetree.cb b/src/mainboard/hp/2760p/devicetree.cb index a301857b7a..06124ed30d 100644 --- a/src/mainboard/hp/2760p/devicetree.cb +++ b/src/mainboard/hp/2760p/devicetree.cb @@ -61,7 +61,6 @@ chip northbridge/intel/sandybridge register "gen3_dec" = "0x00fcfe01" register "gen4_dec" = "0x007c0281" register "gpi6_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/hp/8460p/devicetree.cb b/src/mainboard/hp/8460p/devicetree.cb index a06aea9669..6852f02710 100644 --- a/src/mainboard/hp/8460p/devicetree.cb +++ b/src/mainboard/hp/8460p/devicetree.cb @@ -60,7 +60,6 @@ chip northbridge/intel/sandybridge register "gen3_dec" = "0x00fcfe01" register "gen4_dec" = "0x000402e9" register "gpi6_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/hp/8470p/devicetree.cb b/src/mainboard/hp/8470p/devicetree.cb index 471537218e..3725b08f66 100644 --- a/src/mainboard/hp/8470p/devicetree.cb +++ b/src/mainboard/hp/8470p/devicetree.cb @@ -61,7 +61,6 @@ chip northbridge/intel/sandybridge register "gen3_dec" = "0x00fcfe01" register "gen4_dec" = "0x000402e9" register "gpi6_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/hp/8770w/devicetree.cb b/src/mainboard/hp/8770w/devicetree.cb index d98402c540..0a30de287b 100644 --- a/src/mainboard/hp/8770w/devicetree.cb +++ b/src/mainboard/hp/8770w/devicetree.cb @@ -49,7 +49,6 @@ chip northbridge/intel/sandybridge register "gen3_dec" = "0x00fcfe01" register "gen4_dec" = "0x000402e9" register "gpi6_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 95659beaf5..1472f84043 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -44,7 +44,6 @@ chip northbridge/intel/sandybridge register "docking_supported" = "0" register "gen1_dec" = "0x00fc0601" register "gen2_dec" = "0x00fc0801" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/hp/folio_9470m/devicetree.cb b/src/mainboard/hp/folio_9470m/devicetree.cb index d626934343..cd610b6ac6 100644 --- a/src/mainboard/hp/folio_9470m/devicetree.cb +++ b/src/mainboard/hp/folio_9470m/devicetree.cb @@ -52,7 +52,6 @@ chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did register "gen3_dec" = "0x00fcfe01" register "gen4_dec" = "0x000402e9" register "gpi6_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/hp/revolve_810_g1/devicetree.cb b/src/mainboard/hp/revolve_810_g1/devicetree.cb index ad69ca27e4..32d04ea190 100644 --- a/src/mainboard/hp/revolve_810_g1/devicetree.cb +++ b/src/mainboard/hp/revolve_810_g1/devicetree.cb @@ -52,7 +52,6 @@ chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did register "gen3_dec" = "0x00fcfe01" register "gen4_dec" = "0x000402e9" register "gpi6_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index 68e7c63767..5108db4a65 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -44,7 +44,6 @@ chip northbridge/intel/sandybridge register "docking_supported" = "0" register "gen1_dec" = "0x00fc0601" register "gen2_dec" = "0x00fc0801" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index 0c5962fea0..97f7a7b49d 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -33,7 +33,6 @@ chip northbridge/intel/i945 # 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "1" - register "ide_legacy_combined" = "0x0" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 6561927d3b..6048620659 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -22,9 +23,6 @@ #include #include -#if ENV_RAMSTAGE -#include - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -45,7 +43,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif int get_recovery_mode_switch(void) { diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.c b/src/mainboard/intel/cannonlake_rvp/chromeos.c index 44254bcbcb..0440994f5a 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.c +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.c @@ -15,14 +15,12 @@ #include #include +#include #include #include #include #include -#if ENV_RAMSTAGE -#include - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -33,7 +31,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */ int get_lid_switch(void) { diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index a581217e17..e7094d71e9 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -15,13 +15,11 @@ #include #include +#include #include #include #include -#if ENV_RAMSTAGE -#include - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -32,7 +30,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */ int get_lid_switch(void) { diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 573b9c80ed..c01465c4e7 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -47,7 +47,6 @@ chip northbridge/intel/i945 register "gpi13_routing" = "1" register "gpe0_en" = "0x20000601" - register "ide_legacy_combined" = "0x0" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" register "c3_latency" = "85" diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 699141fc0f..74fe20f548 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -22,9 +23,6 @@ #include #include -#if ENV_RAMSTAGE -#include - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -45,7 +43,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif int get_recovery_mode_switch(void) { diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 4ed1f3c694..0a024b70d3 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -51,7 +51,6 @@ chip northbridge/intel/sandybridge register "gen3_dec" = "0x003c0701" register "c2_latency" = "1" - register "p_cnt_throttling_supported" = "0" device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/intel/emeraldlake2/gpio.c b/src/mainboard/intel/emeraldlake2/gpio.c index 36c52e32de..90010b9170 100644 --- a/src/mainboard/intel/emeraldlake2/gpio.c +++ b/src/mainboard/intel/emeraldlake2/gpio.c @@ -18,7 +18,7 @@ #include -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio3 = GPIO_MODE_GPIO, @@ -36,7 +36,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio28 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio3 = GPIO_DIR_INPUT, .gpio5 = GPIO_DIR_INPUT, @@ -50,34 +50,34 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio27 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio36 = GPIO_MODE_GPIO, .gpio48 = GPIO_MODE_GPIO, .gpio57 = GPIO_MODE_GPIO, .gpio60 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio48 = GPIO_DIR_INPUT, .gpio57 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { }; const struct pch_gpio_map mainboard_gpio_map = { diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index ce8e5486d8..785fe4a862 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -15,14 +15,12 @@ #include #include +#include #include #include #include #include -#if ENV_RAMSTAGE -#include - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -33,7 +31,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */ int get_lid_switch(void) { diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index ff93d27f22..29f05c9ec3 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -24,9 +25,6 @@ #include "gpio.h" #include "ec.h" -#if ENV_RAMSTAGE -#include - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -37,7 +35,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */ int get_lid_switch(void) { diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 64224889a5..3f3dd409c3 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -14,15 +14,12 @@ * GNU General Public License for more details. */ +#include #include #include #include - #include "gpio.h" -#if ENV_RAMSTAGE -#include - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -35,7 +32,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */ int get_write_protect_state(void) { diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index df36b38a31..540ba6a349 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -14,14 +14,12 @@ * GNU General Public License for more details. */ +#include #include #include #define WP_GPIO GP_E_22 -#if ENV_RAMSTAGE -#include - #define ACTIVE_LOW 0 #define ACTIVE_HIGH 1 @@ -35,7 +33,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */ int get_write_protect_state(void) { diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index cd7929c31a..5db7551d12 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -33,7 +33,7 @@ chip northbridge/intel/i945 # 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "1" - register "ide_legacy_combined" = "0x1" + register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x1" register "c3_latency" = "85" diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index fad139a7ac..8928b87988 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -40,7 +40,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "0" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "xhci_switchable_ports" = "0x0f" register "superspeed_capable_ports" = "0x0f" diff --git a/src/mainboard/kontron/ktqm77/gpio.c b/src/mainboard/kontron/ktqm77/gpio.c index 05c66577c6..4b886575a2 100644 --- a/src/mainboard/kontron/ktqm77/gpio.c +++ b/src/mainboard/kontron/ktqm77/gpio.c @@ -23,7 +23,7 @@ * system with vendor supplied firmware. */ -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, /* Unknown Input */ .gpio1 = GPIO_MODE_GPIO, /* Unknown Input */ .gpio2 = GPIO_MODE_GPIO, /* Unknown Input */ @@ -59,7 +59,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio31 = GPIO_MODE_NATIVE /* Native - ACPRESENT */ }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, /* Unknown Input */ .gpio1 = GPIO_DIR_INPUT, /* Unknown Input */ .gpio2 = GPIO_DIR_INPUT, /* Unknown Input */ @@ -94,7 +94,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio31 = GPIO_DIR_INPUT, /* Native */ }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_LOW, /* Unknown Input */ .gpio1 = GPIO_LEVEL_LOW, /* Unknown Input */ .gpio2 = GPIO_LEVEL_LOW, /* Unknown Input */ @@ -129,7 +129,7 @@ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio31 = GPIO_LEVEL_LOW, /* Native */ }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, /* Native - CLKRUN# pin */ .gpio33 = GPIO_MODE_GPIO, /* Unknown Output LOW */ .gpio34 = GPIO_MODE_GPIO, /* Unknown Input */ @@ -164,7 +164,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio63 = GPIO_MODE_NATIVE, /* Native - SLP_S5# */ }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, /* Native */ .gpio33 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ .gpio34 = GPIO_DIR_INPUT, /* Unknown Input */ @@ -199,7 +199,7 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio63 = GPIO_DIR_INPUT, /* Native */ }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_LOW, /* Native */ .gpio33 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ .gpio34 = GPIO_LEVEL_LOW, /* Unknown Input */ @@ -234,7 +234,7 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio63 = GPIO_LEVEL_LOW, /* Native */ }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, /* Unknown Output LOW */ .gpio65 = GPIO_MODE_GPIO, /* Unknown Output LOW */ .gpio66 = GPIO_MODE_GPIO, /* Unknown Output LOW */ @@ -249,7 +249,7 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio75 = GPIO_MODE_NATIVE, /* Native - SML1DATA */ }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ .gpio65 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ .gpio66 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ @@ -264,7 +264,7 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio75 = GPIO_DIR_INPUT, /* Native */ }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ .gpio65 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ .gpio66 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 48c2ea010e..024b8f8dd1 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -46,7 +46,6 @@ chip northbridge/intel/sandybridge register "gen4_dec" = "0x00000000" register "gpi13_routing" = "2" register "gpi6_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 1, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/lenovo/l520/gpio.c b/src/mainboard/lenovo/l520/gpio.c index 68d0c79c70..c7818abdf7 100644 --- a/src/mainboard/lenovo/l520/gpio.c +++ b/src/mainboard/lenovo/l520/gpio.c @@ -16,7 +16,7 @@ */ #include -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, @@ -42,7 +42,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio30 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_OUTPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_OUTPUT, @@ -68,7 +68,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio30 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, .gpio2 = GPIO_LEVEL_HIGH, .gpio4 = GPIO_LEVEL_HIGH, @@ -87,20 +87,20 @@ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio30 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set1 pch_gpio_set1_reset = { +static const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio24 = GPIO_RESET_RSMRST, .gpio30 = GPIO_RESET_RSMRST, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, .gpio6 = GPIO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio33 = GPIO_MODE_GPIO, .gpio35 = GPIO_MODE_GPIO, .gpio36 = GPIO_MODE_GPIO, @@ -123,7 +123,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio61 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio33 = GPIO_DIR_OUTPUT, .gpio35 = GPIO_DIR_OUTPUT, .gpio36 = GPIO_DIR_INPUT, @@ -145,7 +145,7 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio61 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio33 = GPIO_LEVEL_LOW, .gpio35 = GPIO_LEVEL_HIGH, .gpio50 = GPIO_LEVEL_HIGH, @@ -159,10 +159,10 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio61 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set2 pch_gpio_set2_reset = { +static const struct pch_gpio_set2 pch_gpio_set2_reset = { }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, .gpio65 = GPIO_MODE_GPIO, .gpio66 = GPIO_MODE_GPIO, @@ -173,7 +173,7 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio71 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_OUTPUT, .gpio65 = GPIO_DIR_OUTPUT, .gpio66 = GPIO_DIR_OUTPUT, @@ -184,7 +184,7 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio71 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_LOW, .gpio65 = GPIO_LEVEL_LOW, .gpio66 = GPIO_LEVEL_LOW, @@ -193,7 +193,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio71 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set3 pch_gpio_set3_reset = { +static const struct pch_gpio_set3 pch_gpio_set3_reset = { }; const struct pch_gpio_map mainboard_gpio_map = { diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index a9e8babe6e..15d323d8b9 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -44,7 +44,6 @@ chip northbridge/intel/sandybridge register "gen4_dec" = "0x000c06a1" register "gpi13_routing" = "2" register "gpi7_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 1, 0, 1, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/lenovo/s230u/gpio.c b/src/mainboard/lenovo/s230u/gpio.c index a0e30c26e7..31bb6fa885 100644 --- a/src/mainboard/lenovo/s230u/gpio.c +++ b/src/mainboard/lenovo/s230u/gpio.c @@ -15,7 +15,7 @@ #include -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, /* POUT1# (from palm sensor 1) */ @@ -47,7 +47,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio31 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_OUTPUT, .gpio1 = GPIO_DIR_OUTPUT, .gpio2 = GPIO_DIR_INPUT, @@ -79,7 +79,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio31 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, .gpio1 = GPIO_LEVEL_HIGH, .gpio3 = GPIO_LEVEL_HIGH, @@ -101,11 +101,11 @@ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio30 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set1 pch_gpio_set1_reset = { +static const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio24 = GPIO_RESET_RSMRST, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio2 = GPIO_INVERT, .gpio4 = GPIO_INVERT, .gpio6 = GPIO_NO_INVERT, @@ -118,10 +118,10 @@ const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio31 = GPIO_NO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio33 = GPIO_MODE_GPIO, /* PCH_WLBT_OFF_5# (to WLAN mPCIe pin 5) */ /* GPIO34 marked as PCH_BT_ON#, but is native (STP_PCI#) */ .gpio35 = GPIO_MODE_GPIO, /* 3G_DET# (from WWAN/mSATA mPCIe pin 43) */ @@ -148,7 +148,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio33 = GPIO_DIR_OUTPUT, .gpio35 = GPIO_DIR_INPUT, .gpio36 = GPIO_DIR_OUTPUT, @@ -173,7 +173,7 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio60 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio33 = GPIO_LEVEL_HIGH, .gpio36 = GPIO_LEVEL_HIGH, .gpio37 = GPIO_LEVEL_HIGH, @@ -194,10 +194,10 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio60 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set2 pch_gpio_set2_reset = { +static const struct pch_gpio_set2 pch_gpio_set2_reset = { }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, .gpio65 = GPIO_MODE_GPIO, .gpio68 = GPIO_MODE_GPIO, @@ -208,7 +208,7 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio74 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_OUTPUT, .gpio65 = GPIO_DIR_OUTPUT, .gpio68 = GPIO_DIR_OUTPUT, @@ -219,7 +219,7 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio74 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_HIGH, .gpio65 = GPIO_LEVEL_HIGH, .gpio68 = GPIO_LEVEL_LOW, @@ -227,7 +227,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio74 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set3 pch_gpio_set3_reset = { +static const struct pch_gpio_set3 pch_gpio_set3_reset = { }; const struct pch_gpio_map mainboard_gpio_map = { diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index c4092fe901..6deff6039c 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -68,7 +68,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" # device specific SPI configuration register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index d1e3f75499..aa6cc68154 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -68,7 +68,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t420s/gpio.c b/src/mainboard/lenovo/t420s/gpio.c index c3915779a6..3058f1a21f 100644 --- a/src/mainboard/lenovo/t420s/gpio.c +++ b/src/mainboard/lenovo/t420s/gpio.c @@ -12,7 +12,7 @@ */ #include -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, // -USB30_SMIB - input .gpio1 = GPIO_MODE_GPIO, // -EC_SCI - input .gpio2 = GPIO_MODE_GPIO, // -LCD_PRESENCE - input @@ -47,7 +47,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio31 = GPIO_MODE_NATIVE, // ACPRESENT - input }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -82,7 +82,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio31 = GPIO_DIR_INPUT }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, .gpio1 = GPIO_LEVEL_HIGH, .gpio2 = GPIO_LEVEL_LOW, @@ -117,17 +117,17 @@ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio31 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio0 = GPIO_INVERT, .gpio1 = GPIO_INVERT, .gpio13 = GPIO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { .gpio18 = GPIO_NO_BLINK, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, // CLKRUN - output .gpio33 = GPIO_MODE_GPIO, // SATA_DOCK_DTCT - output to SATA4GP .gpio34 = GPIO_MODE_GPIO, // DGFX_VRM_ID - input - HIGH: 1GB / LOW: 2GB @@ -162,7 +162,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio63 = GPIO_MODE_NATIVE, // SLP_S5 - output }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_INPUT, @@ -197,7 +197,7 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio63 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_HIGH, .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_HIGH, @@ -232,7 +232,7 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio63 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_NATIVE, // NC .gpio65 = GPIO_MODE_NATIVE, // VIDEO_CLK_27M_NSS - output .gpio66 = GPIO_MODE_NATIVE, // NC @@ -247,7 +247,7 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio75 = GPIO_MODE_NATIVE, // SML1DATA - EC_SDA2 - i/o }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_OUTPUT, .gpio65 = GPIO_DIR_OUTPUT, .gpio66 = GPIO_DIR_OUTPUT, @@ -262,7 +262,7 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio75 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_HIGH, .gpio65 = GPIO_LEVEL_HIGH, .gpio66 = GPIO_LEVEL_HIGH, diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 2731b69ec0..f7e04367c6 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -39,7 +39,6 @@ chip northbridge/intel/sandybridge register "gen3_dec" = "0x000c06a1" register "gpi13_routing" = "2" register "gpi1_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/lenovo/t430/gpio.c b/src/mainboard/lenovo/t430/gpio.c index 2e4897af30..4a90179ebf 100644 --- a/src/mainboard/lenovo/t430/gpio.c +++ b/src/mainboard/lenovo/t430/gpio.c @@ -15,7 +15,7 @@ #include -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, @@ -37,7 +37,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio29 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -52,26 +52,26 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio27 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio10 = GPIO_LEVEL_HIGH, .gpio22 = GPIO_LEVEL_HIGH, .gpio29 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set1 pch_gpio_set1_reset = { +static const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio24 = GPIO_RESET_RSMRST, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, .gpio6 = GPIO_INVERT, .gpio13 = GPIO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, .gpio35 = GPIO_MODE_GPIO, @@ -91,7 +91,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio57 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio34 = GPIO_DIR_INPUT, .gpio35 = GPIO_DIR_INPUT, .gpio36 = GPIO_DIR_INPUT, @@ -105,7 +105,7 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio57 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio33 = GPIO_LEVEL_HIGH, .gpio43 = GPIO_LEVEL_HIGH, .gpio51 = GPIO_LEVEL_HIGH, @@ -114,10 +114,10 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio55 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set2 pch_gpio_set2_reset = { +static const struct pch_gpio_set2 pch_gpio_set2_reset = { }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, .gpio65 = GPIO_MODE_GPIO, .gpio66 = GPIO_MODE_GPIO, @@ -128,7 +128,7 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio71 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_INPUT, .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, @@ -139,10 +139,10 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio71 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { }; -const struct pch_gpio_set3 pch_gpio_set3_reset = { +static const struct pch_gpio_set3 pch_gpio_set3_reset = { }; const struct pch_gpio_map mainboard_gpio_map = { diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 21d54acf11..0c2f668897 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -71,7 +71,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "docking_supported" = "1" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t430s/variants/t430s/gpio.c b/src/mainboard/lenovo/t430s/variants/t430s/gpio.c index 56fb578b7e..9adc481d62 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/gpio.c +++ b/src/mainboard/lenovo/t430s/variants/t430s/gpio.c @@ -12,7 +12,7 @@ */ #include -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, // -EC_SCI - input .gpio2 = GPIO_MODE_GPIO, @@ -47,7 +47,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio31 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -82,7 +82,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio31 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_LOW, .gpio1 = GPIO_LEVEL_HIGH, .gpio2 = GPIO_LEVEL_LOW, @@ -117,21 +117,21 @@ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio31 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, .gpio6 = GPIO_INVERT, .gpio13 = GPIO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_reset = { +static const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio24 = GPIO_RESET_RSMRST, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { .gpio18 = GPIO_NO_BLINK, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, @@ -166,7 +166,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio63 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_INPUT, @@ -201,7 +201,7 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio63 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_HIGH, .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_LOW, @@ -236,7 +236,7 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio63 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, .gpio65 = GPIO_MODE_GPIO, .gpio66 = GPIO_MODE_GPIO, @@ -251,7 +251,7 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio75 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_INPUT, .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, @@ -266,7 +266,7 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio75 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_HIGH, .gpio65 = GPIO_LEVEL_HIGH, .gpio66 = GPIO_LEVEL_HIGH, diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb index eff2d69304..7893daf9ec 100644 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb @@ -63,7 +63,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/t520/variants/t520/gpio.c b/src/mainboard/lenovo/t520/variants/t520/gpio.c index 3a10bd0083..a4351bb5ba 100644 --- a/src/mainboard/lenovo/t520/variants/t520/gpio.c +++ b/src/mainboard/lenovo/t520/variants/t520/gpio.c @@ -15,7 +15,7 @@ #include -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, // -USB30_SMI - input .gpio1 = GPIO_MODE_GPIO, // -EC_SCI - input .gpio2 = GPIO_MODE_GPIO, // -LCD_PRESENCE - input @@ -50,7 +50,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio31 = GPIO_MODE_NATIVE, // ACPRESENT - input }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -85,7 +85,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio31 = GPIO_DIR_INPUT }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, .gpio1 = GPIO_LEVEL_HIGH, .gpio2 = GPIO_LEVEL_LOW, @@ -120,17 +120,17 @@ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio31 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, .gpio7 = GPIO_INVERT, .gpio13 = GPIO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { .gpio18 = GPIO_NO_BLINK, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, // CLKRUN - output .gpio33 = GPIO_MODE_GPIO, // SATA_DOCK_DTCT - output to SATA4GP .gpio34 = GPIO_MODE_GPIO, // VRAM_SIZE_ID - input - HIGH: 1GB / LOW: 2GB @@ -165,7 +165,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio63 = GPIO_MODE_NATIVE, // SLP_S5 - output }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_INPUT, @@ -200,7 +200,7 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio63 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_HIGH, .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_HIGH, @@ -235,7 +235,7 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio63 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_NATIVE, // NC .gpio65 = GPIO_MODE_NATIVE, // NC .gpio66 = GPIO_MODE_NATIVE, // NC @@ -250,7 +250,7 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio75 = GPIO_MODE_NATIVE, // SML1DATA - EC_SDA2 - i/o }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_OUTPUT, .gpio65 = GPIO_DIR_OUTPUT, .gpio66 = GPIO_DIR_OUTPUT, @@ -265,7 +265,7 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio75 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_HIGH, .gpio65 = GPIO_LEVEL_HIGH, .gpio66 = GPIO_LEVEL_HIGH, diff --git a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb index ceca46ea84..8716046410 100644 --- a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb @@ -63,7 +63,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb index 335543a8f7..190539ac1f 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb @@ -62,7 +62,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/t530/variants/t530/gpio.c b/src/mainboard/lenovo/t530/variants/t530/gpio.c index cc3ace28fd..cbae7f0d36 100644 --- a/src/mainboard/lenovo/t530/variants/t530/gpio.c +++ b/src/mainboard/lenovo/t530/variants/t530/gpio.c @@ -12,7 +12,7 @@ */ #include -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, @@ -47,7 +47,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio31 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -82,7 +82,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio31 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, .gpio1 = GPIO_LEVEL_HIGH, .gpio2 = GPIO_LEVEL_LOW, @@ -117,7 +117,7 @@ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio31 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio0 = GPIO_NO_INVERT, .gpio1 = GPIO_INVERT, .gpio2 = GPIO_NO_INVERT, @@ -152,7 +152,7 @@ const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio31 = GPIO_NO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { .gpio0 = GPIO_NO_BLINK, .gpio1 = GPIO_NO_BLINK, .gpio2 = GPIO_NO_BLINK, @@ -187,7 +187,7 @@ const struct pch_gpio_set1 pch_gpio_set1_blink = { .gpio31 = GPIO_NO_BLINK, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, @@ -222,7 +222,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio63 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_INPUT, @@ -257,7 +257,7 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio63 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_HIGH, .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_LOW, @@ -292,7 +292,7 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio63 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, .gpio65 = GPIO_MODE_GPIO, .gpio66 = GPIO_MODE_GPIO, @@ -307,7 +307,7 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio75 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_INPUT, .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, @@ -322,7 +322,7 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio75 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_HIGH, .gpio65 = GPIO_LEVEL_HIGH, .gpio66 = GPIO_LEVEL_HIGH, diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb index 0a80fa1d8c..0844124f0e 100644 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb @@ -51,7 +51,6 @@ chip northbridge/intel/sandybridge register "gen1_dec" = "0x007c1601" register "gen2_dec" = "0x000c15e1" register "gen4_dec" = "0x000c06a1" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/lenovo/t530/variants/w530/gpio.c b/src/mainboard/lenovo/t530/variants/w530/gpio.c index c6a10d11db..8eb776bfae 100644 --- a/src/mainboard/lenovo/t530/variants/w530/gpio.c +++ b/src/mainboard/lenovo/t530/variants/w530/gpio.c @@ -17,7 +17,7 @@ #include -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, @@ -52,7 +52,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio31 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -74,7 +74,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio29 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio8 = GPIO_LEVEL_LOW, .gpio10 = GPIO_LEVEL_HIGH, .gpio15 = GPIO_LEVEL_LOW, @@ -84,19 +84,19 @@ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio29 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set1 pch_gpio_set1_reset = { +static const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio24 = GPIO_RESET_RSMRST, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, .gpio13 = GPIO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, @@ -131,7 +131,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio63 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_INPUT, .gpio35 = GPIO_DIR_INPUT, @@ -151,7 +151,7 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio57 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio33 = GPIO_LEVEL_HIGH, .gpio43 = GPIO_LEVEL_HIGH, .gpio51 = GPIO_LEVEL_HIGH, @@ -160,10 +160,10 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio55 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set2 pch_gpio_set2_reset = { +static const struct pch_gpio_set2 pch_gpio_set2_reset = { }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, .gpio65 = GPIO_MODE_GPIO, .gpio66 = GPIO_MODE_GPIO, @@ -178,7 +178,7 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio75 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_INPUT, .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, @@ -189,10 +189,10 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio71 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { }; -const struct pch_gpio_set3 pch_gpio_set3_reset = { +static const struct pch_gpio_set3 pch_gpio_set3_reset = { }; const struct pch_gpio_map mainboard_gpio_map = { diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 21d38f5ab2..2a98a60cac 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -66,7 +66,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "0x0065" - register "p_cnt_throttling_supported" = "1" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x131e/gpio.c b/src/mainboard/lenovo/x131e/gpio.c index d11b66231c..e51e9af3d1 100644 --- a/src/mainboard/lenovo/x131e/gpio.c +++ b/src/mainboard/lenovo/x131e/gpio.c @@ -15,7 +15,7 @@ #include -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, @@ -40,7 +40,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio29 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_OUTPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_OUTPUT, @@ -65,7 +65,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio29 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, .gpio2 = GPIO_LEVEL_HIGH, .gpio3 = GPIO_LEVEL_HIGH, @@ -84,19 +84,19 @@ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio29 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set1 pch_gpio_set1_reset = { +static const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio24 = GPIO_RESET_RSMRST, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, .gpio6 = GPIO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, .gpio35 = GPIO_MODE_GPIO, @@ -117,7 +117,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio61 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_OUTPUT, .gpio35 = GPIO_DIR_OUTPUT, @@ -138,7 +138,7 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio61 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio33 = GPIO_LEVEL_LOW, .gpio34 = GPIO_LEVEL_HIGH, .gpio35 = GPIO_LEVEL_HIGH, @@ -149,10 +149,10 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio61 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set2 pch_gpio_set2_reset = { +static const struct pch_gpio_set2 pch_gpio_set2_reset = { }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, .gpio65 = GPIO_MODE_GPIO, .gpio66 = GPIO_MODE_GPIO, @@ -164,7 +164,7 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio72 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_OUTPUT, .gpio65 = GPIO_DIR_OUTPUT, .gpio66 = GPIO_DIR_OUTPUT, @@ -176,7 +176,7 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio72 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_HIGH, .gpio65 = GPIO_LEVEL_LOW, .gpio66 = GPIO_LEVEL_HIGH, @@ -186,7 +186,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio72 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set3 pch_gpio_set3_reset = { +static const struct pch_gpio_set3 pch_gpio_set3_reset = { }; const struct pch_gpio_map mainboard_gpio_map = { diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index 8caa0d1a2f..288870f81d 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -70,7 +70,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/gpio.c b/src/mainboard/lenovo/x1_carbon_gen1/gpio.c index 9a33841d32..e5beabc5c2 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/gpio.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/gpio.c @@ -15,7 +15,7 @@ */ #include -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, @@ -50,7 +50,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio31 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -85,7 +85,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio31 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, .gpio1 = GPIO_LEVEL_HIGH, .gpio2 = GPIO_LEVEL_LOW, @@ -120,7 +120,7 @@ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio31 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set1 pch_gpio_set1_reset = { +static const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio0 = GPIO_RESET_PWROK, .gpio1 = GPIO_RESET_PWROK, .gpio2 = GPIO_RESET_PWROK, @@ -155,7 +155,7 @@ const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio31 = GPIO_RESET_PWROK, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio0 = GPIO_NO_INVERT, .gpio1 = GPIO_INVERT, .gpio2 = GPIO_NO_INVERT, @@ -190,7 +190,7 @@ const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio31 = GPIO_NO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { .gpio0 = GPIO_NO_BLINK, .gpio1 = GPIO_NO_BLINK, .gpio2 = GPIO_NO_BLINK, @@ -225,7 +225,7 @@ const struct pch_gpio_set1 pch_gpio_set1_blink = { .gpio31 = GPIO_NO_BLINK, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, @@ -260,7 +260,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio63 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_INPUT, @@ -295,7 +295,7 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio63 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_HIGH, .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_LOW, @@ -330,7 +330,7 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio63 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set2 pch_gpio_set2_reset = { +static const struct pch_gpio_set2 pch_gpio_set2_reset = { .gpio32 = GPIO_RESET_PWROK, .gpio33 = GPIO_RESET_PWROK, .gpio34 = GPIO_RESET_PWROK, @@ -365,7 +365,7 @@ const struct pch_gpio_set2 pch_gpio_set2_reset = { .gpio63 = GPIO_RESET_PWROK, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, .gpio65 = GPIO_MODE_GPIO, .gpio66 = GPIO_MODE_GPIO, @@ -380,7 +380,7 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio75 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_INPUT, .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, @@ -395,7 +395,7 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio75 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_LOW, .gpio65 = GPIO_LEVEL_LOW, .gpio66 = GPIO_LEVEL_LOW, @@ -410,7 +410,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio75 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set3 pch_gpio_set3_reset = { +static const struct pch_gpio_set3 pch_gpio_set3_reset = { .gpio64 = GPIO_RESET_PWROK, .gpio65 = GPIO_RESET_PWROK, .gpio66 = GPIO_RESET_PWROK, diff --git a/src/mainboard/lenovo/x200/gpio.c b/src/mainboard/lenovo/x200/gpio.c index 2da409738d..516a3ae69b 100644 --- a/src/mainboard/lenovo/x200/gpio.c +++ b/src/mainboard/lenovo/x200/gpio.c @@ -13,7 +13,7 @@ #include -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, .gpio3 = GPIO_MODE_GPIO, @@ -35,7 +35,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio28 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, .gpio3 = GPIO_DIR_INPUT, @@ -57,7 +57,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio28 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio9 = GPIO_LEVEL_HIGH, .gpio19 = GPIO_LEVEL_HIGH, .gpio20 = GPIO_LEVEL_HIGH, @@ -66,15 +66,15 @@ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio28 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, .gpio8 = GPIO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, .gpio36 = GPIO_MODE_GPIO, @@ -89,7 +89,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio57 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_OUTPUT, .gpio36 = GPIO_DIR_INPUT, @@ -104,7 +104,7 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio57 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_LOW, .gpio41 = GPIO_LEVEL_HIGH, diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 6ece08bee6..bf74d710bb 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -68,7 +68,6 @@ chip northbridge/intel/nehalem register "gen3_dec" = "0x1c1681" register "gen4_dec" = "0x040069" - register "p_cnt_throttling_supported" = "1" register "c2_latency" = "1" register "docking_supported" = "1" diff --git a/src/mainboard/lenovo/x201/gpio.c b/src/mainboard/lenovo/x201/gpio.c index 76872ecd35..ee63f87137 100644 --- a/src/mainboard/lenovo/x201/gpio.c +++ b/src/mainboard/lenovo/x201/gpio.c @@ -15,7 +15,7 @@ #include -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, @@ -50,7 +50,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio31 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set1 pch_gpio_set1_reset = { +static const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio0 = GPIO_RESET_PWROK, .gpio1 = GPIO_RESET_PWROK, .gpio2 = GPIO_RESET_PWROK, @@ -85,7 +85,7 @@ const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio31 = GPIO_RESET_PWROK, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -120,7 +120,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio31 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, .gpio1 = GPIO_LEVEL_HIGH, .gpio2 = GPIO_LEVEL_HIGH, @@ -155,7 +155,7 @@ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio31 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { .gpio0 = GPIO_NO_BLINK, .gpio1 = GPIO_NO_BLINK, .gpio2 = GPIO_NO_BLINK, @@ -190,7 +190,7 @@ const struct pch_gpio_set1 pch_gpio_set1_blink = { .gpio31 = GPIO_NO_BLINK, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio0 = GPIO_NO_INVERT, .gpio1 = GPIO_INVERT, .gpio2 = GPIO_INVERT, @@ -225,7 +225,7 @@ const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio31 = GPIO_NO_INVERT, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, @@ -260,7 +260,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio63 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_OUTPUT, .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_INPUT, @@ -295,7 +295,7 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio63 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_HIGH, .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_HIGH, @@ -330,7 +330,7 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio63 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_NATIVE, .gpio65 = GPIO_MODE_NATIVE, .gpio66 = GPIO_MODE_NATIVE, @@ -345,7 +345,7 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio75 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_OUTPUT, .gpio65 = GPIO_DIR_OUTPUT, .gpio66 = GPIO_DIR_OUTPUT, @@ -360,7 +360,7 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio75 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_LOW, .gpio65 = GPIO_LEVEL_LOW, .gpio66 = GPIO_LEVEL_LOW, diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 360de04943..26fa1a4d1f 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -69,7 +69,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 4687e9ccc3..61a5468a78 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -72,7 +72,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x230/gpio.c b/src/mainboard/lenovo/x230/gpio.c index a3e3a750d3..85d086c2f1 100644 --- a/src/mainboard/lenovo/x230/gpio.c +++ b/src/mainboard/lenovo/x230/gpio.c @@ -16,7 +16,7 @@ #include -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, @@ -51,7 +51,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio31 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -86,7 +86,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio31 = GPIO_DIR_INPUT }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, .gpio1 = GPIO_LEVEL_HIGH, .gpio2 = GPIO_LEVEL_LOW, @@ -121,13 +121,13 @@ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio31 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, .gpio6 = GPIO_INVERT, .gpio13 = GPIO_INVERT, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_GPIO, .gpio34 = GPIO_MODE_GPIO, @@ -162,7 +162,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio63 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, .gpio33 = GPIO_DIR_INPUT, .gpio34 = GPIO_DIR_OUTPUT, @@ -197,7 +197,7 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio63 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_HIGH, .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_LOW, @@ -232,7 +232,7 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio63 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_GPIO, .gpio65 = GPIO_MODE_GPIO, .gpio66 = GPIO_MODE_GPIO, @@ -247,7 +247,7 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio75 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_INPUT, .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, @@ -262,7 +262,7 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio75 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_HIGH, .gpio65 = GPIO_LEVEL_HIGH, .gpio66 = GPIO_LEVEL_HIGH, diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index 4db2536148..fc23f359e3 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -21,7 +21,6 @@ chip northbridge/intel/sandybridge register "docking_supported" = "0" register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0a01" - register "p_cnt_throttling_supported" = "1" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" diff --git a/src/mainboard/opencellular/rotundu/Kconfig b/src/mainboard/opencellular/rotundu/Kconfig index fe1cbf94e6..ddacbe747c 100644 --- a/src/mainboard/opencellular/rotundu/Kconfig +++ b/src/mainboard/opencellular/rotundu/Kconfig @@ -23,7 +23,6 @@ config BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU select HAVE_OPTION_TABLE select ENABLE_BUILTIN_COM1 select ENABLE_FSP_FAST_BOOT - select HAVE_ACPI_RESUME select USE_BLOBS select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/portwell/Kconfig b/src/mainboard/portwell/Kconfig new file mode 100644 index 0000000000..78e5037c30 --- /dev/null +++ b/src/mainboard/portwell/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_PORTWELL + +choice + prompt "Mainboard model" + +source "src/mainboard/portwell/*/Kconfig.name" + +endchoice + +source "src/mainboard/portwell/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Portwell" + +endif # VENDOR_PORTWELL diff --git a/src/mainboard/portwell/Kconfig.name b/src/mainboard/portwell/Kconfig.name new file mode 100644 index 0000000000..12240ed1cd --- /dev/null +++ b/src/mainboard/portwell/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_PORTWELL + bool "Portwell" diff --git a/src/mainboard/portwell/m107/Kconfig b/src/mainboard/portwell/m107/Kconfig new file mode 100644 index 0000000000..b366418c16 --- /dev/null +++ b/src/mainboard/portwell/m107/Kconfig @@ -0,0 +1,100 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## Copyright (C) 2018-2019 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_PORTWELL_M107 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select SOC_INTEL_BRASWELL + select PCIEXP_L1_SUB_STATE + select HAVE_FSP_BIN + select CACHE_MRC_SETTINGS + select DISABLE_HPET + select GENERIC_SPD_BIN + +choice + prompt "Onboard memory manufacturer" + default ONBOARD_MEM_MICRON + +config ONBOARD_MEM_SAMSUNG + bool "Samsung" + help + Samsung K4B8G1646D memory + +config ONBOARD_MEM_MICRON + bool "Micron" + help + Micron MT41K512M16HA memory +endchoice + +config MAINBOARD_DIR + string + default portwell/m107 + +config MAINBOARD_PART_NUMBER + string + default "PQ7-M107" + +config CBFS_SIZE + hex + default 0x00800000 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0x10C00 + help + This should be updated when the microcode patch changes. + +config CPU_MICROCODE_CBFS_LOC + hex + default 0xFFFE9400 + +config MRC_SETTINGS_CACHE_SIZE + hex + default 0x08000 + +config FSP_LOC + hex + default 0xfff9c000 + +config BOOTBLOCK_LOC + hex + default 0xFFFF0000 + +config BOOTBLOCK_SIZE + hex + default 0x10000 + +config SPI_FLASH_INCLUDE_ALL_DRIVERS + bool + default n + +config SPI_FLASH_WINBOND + bool + default y + +config C_ENV_BOOTBLOCK_SIZE + hex "C Bootblock Size" + default 0x4000 + +config DRIVERS_INTEL_WIFI + bool + default n + +endif # BOARD_PORTWELL_M107 diff --git a/src/mainboard/portwell/m107/Kconfig.name b/src/mainboard/portwell/m107/Kconfig.name new file mode 100644 index 0000000000..eca9589c9a --- /dev/null +++ b/src/mainboard/portwell/m107/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_PORTWELL_M107 + bool "PQ7-M107" diff --git a/src/mainboard/portwell/m107/Makefile.inc b/src/mainboard/portwell/m107/Makefile.inc new file mode 100644 index 0000000000..cca992e20c --- /dev/null +++ b/src/mainboard/portwell/m107/Makefile.inc @@ -0,0 +1,27 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015 Intel Corp. +## Copyright (C) 2018-2019 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += com_init.c + +ramstage-y += gpio.c +ramstage-y += hda_verb.c +ramstage-y += irqroute.c +ramstage-y += w25q64.c + +# Order of names in SPD_SOURCES is important! +SPD_SOURCES = SAMSUNG_K4B8G1646D-MYKO +SPD_SOURCES += MICRON_MT41K512M16HA-125A diff --git a/src/mainboard/portwell/m107/acpi/ec.asl b/src/mainboard/portwell/m107/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/portwell/m107/acpi/mainboard.asl b/src/mainboard/portwell/m107/acpi/mainboard.asl new file mode 100644 index 0000000000..2c325c6f13 --- /dev/null +++ b/src/mainboard/portwell/m107/acpi/mainboard.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (_UID, 1) + } +} diff --git a/src/mainboard/portwell/m107/acpi/sleepstates.asl b/src/mainboard/portwell/m107/acpi/sleepstates.asl new file mode 100644 index 0000000000..428fda2a01 --- /dev/null +++ b/src/mainboard/portwell/m107/acpi/sleepstates.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Name(\_S0, Package(){0x0,0x0,0x0,0x0}) +Name(\_S4, Package(){0x6,0x6,0x0,0x0}) +Name(\_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/src/mainboard/portwell/m107/acpi/superio.asl b/src/mainboard/portwell/m107/acpi/superio.asl new file mode 100644 index 0000000000..0258e28216 --- /dev/null +++ b/src/mainboard/portwell/m107/acpi/superio.asl @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* mainboard configuration */ +#include "onboard.h" + + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + Name (_ADR, 0) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + FixedIO (0x03F8, 0x08) + FixedIO (0x6E, 0x02) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + FixedIO (0x03F8, 0x08) + FixedIO (0x6E, 0x02) + IRQNoFlags () {4} + } + EndDependentFn () + }) + } diff --git a/src/mainboard/portwell/m107/acpi_tables.c b/src/mainboard/portwell/m107/acpi_tables.c new file mode 100644 index 0000000000..15c955afc2 --- /dev/null +++ b/src/mainboard/portwell/m107/acpi_tables.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* Disable DPTF */ + gnvs->dpte = 0; + + /* PMIC is configured in I2C1, hide it for the OS */ + gnvs->dev.lpss_en[LPSS_NVS_I2C2] = 0; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} diff --git a/src/mainboard/portwell/m107/board_info.txt b/src/mainboard/portwell/m107/board_info.txt new file mode 100644 index 0000000000..9abbdfd293 --- /dev/null +++ b/src/mainboard/portwell/m107/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Portwell +Board name: PQ7-M107 +Category: sbc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/portwell/m107/cmos.layout b/src/mainboard/portwell/m107/cmos.layout new file mode 100644 index 0000000000..c293c5f989 --- /dev/null +++ b/src/mainboard/portwell/m107/cmos.layout @@ -0,0 +1,121 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2015 Intel Corp. +## Copyright (C) 2018 Eltan B.V. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +# reboot_counter reserved for core, not used by platform. +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +#400 1 e 2 unused +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#416 568 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/soc/intel/baytrail/stage_cache.c b/src/mainboard/portwell/m107/com_init.c similarity index 57% rename from src/soc/intel/baytrail/stage_cache.c rename to src/mainboard/portwell/m107/com_init.c index 4c2a97621a..f19aba311c 100644 --- a/src/soc/intel/baytrail/stage_cache.c +++ b/src/mainboard/portwell/m107/com_init.c @@ -2,6 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,19 +15,15 @@ * GNU General Public License for more details. */ -#include -#include -#include +#include +#include +#include "onboard.h" -void stage_cache_external_region(void **base, size_t *size) +#define SERIAL_DEV PNP_DEV(ITE8528_CMD_PORT, 1) /* ITE8528 UART1 */ + +void bootblock_mainboard_early_init(void) { - char *smm_base; - /* 1MiB cache size */ - const long cache_size = CONFIG_SMM_RESERVED_SIZE; - - /* Ramstage cache lives in TSEG region which is the definition of - * cbmem_top(). */ - smm_base = cbmem_top(); - *size = cache_size; - *base = &smm_base[smm_region_size() - cache_size]; + /* Enable the serial port inside the EC */ + pnp_set_logical_device(SERIAL_DEV); + pnp_set_enable(SERIAL_DEV, 1); } diff --git a/src/mainboard/portwell/m107/devicetree.cb b/src/mainboard/portwell/m107/devicetree.cb new file mode 100644 index 0000000000..9a27fed8cf --- /dev/null +++ b/src/mainboard/portwell/m107/devicetree.cb @@ -0,0 +1,124 @@ +chip soc/intel/braswell + + ############################################################ + # Set the parameters for MemoryInit + ############################################################ + + register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB + + register "PcdMrcInitMmioSize" = "0x0800" + register "PcdMrcInitSpdAddr1" = "0xa0" + register "PcdMrcInitSpdAddr2" = "0xa2" + register "PcdIgdDvmt50PreAlloc" = "1" + register "PcdApertureSize" = "2" + register "PcdGttSize" = "1" + register "PcdDvfsEnable" = "0" + register "PcdCaMirrorEn" = "1" + + ############################################################ + # Set the parameters for SiliconInit + ############################################################ + + register "PcdSdcardMode" = "PCH_DISABLED" + register "PcdEnableHsuart0" = "0" + register "PcdEnableHsuart1" = "0" + register "PcdEnableAzalia" = "1" + register "PcdEnableXhci" = "1" + register "PcdEnableLpe" = "0" + register "PcdEnableDma0" = "0" + register "PcdEnableDma1" = "0" + register "PcdEnableI2C0" = "0" + register "PcdEnableI2C1" = "0" + register "PcdEnableI2C2" = "0" + register "PcdEnableI2C3" = "0" + register "PcdEnableI2C4" = "0" + register "PcdEnableI2C5" = "0" + register "PcdEnableI2C6" = "0" + register "PunitPwrConfigDisable" = "0" # Enable SVID + register "ChvSvidConfig" = "1" + register "PcdEmmcMode" = "PCH_PCI_MODE" + register "PcdUsb3ClkSsc" = "1" + register "PcdDispClkSsc" = "1" + register "PcdSataClkSsc" = "1" + register "PcdEnableSata" = "1" + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "5" + register "Usb2Port0IUsbTxEmphasisEn" = "2" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "3" + register "Usb2Port1IUsbTxEmphasisEn" = "2" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "3" + register "Usb2Port2IUsbTxEmphasisEn" = "2" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "3" + register "Usb2Port3IUsbTxEmphasisEn" = "2" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "3" + register "Usb2Port4IUsbTxEmphasisEn" = "2" + register "Usb2Port4PerPortTxPeHalf" = "1" + register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" + register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" + register "PcdSataInterfaceSpeed" = "3" + register "PcdPchSsicEnable" = "1" + register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM + register "PMIC_I2CBus" = "0" + register "ISPEnable" = "0" # Disable IUNIT + register "ISPPciDevConfig" = "3" + register "PcdSdDetectChk" = "0" # Disable SD card detect + register "DptfDisable" = "1" + + # LPE audio codec settings + register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock + + # Enable devices in PCI mode + register "lpss_acpi_mode" = "0" + register "emmc_acpi_mode" = "0" + register "sd_acpi_mode" = "0" + register "lpe_acpi_mode" = "0" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # 8086 2280 - SoC router + device pci 02.0 on end # 8086 22B1 - GFX + device pci 0b.0 off end # 8086 22DC - PUNIT/DPTF + device pci 10.0 on end # 8086 2294 - MMC Port + device pci 12.0 on end # 8086 0F16 - SD Port + device pci 13.0 on end # 8086 22a3 - SATA Port + device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time + device pci 18.0 off end # 8086 22c0 - SIO - DMA + device pci 18.1 off end # 8086 22c1 - I2C Port 1 + device pci 18.2 off end # 8086 22c2 - I2C Port 2 + device pci 18.3 off end # 8086 22c3 - I2C Port 3 + device pci 18.4 off end # 8086 22c4 - I2C Port 4 + device pci 18.5 off end # 8086 22c5 - I2C Port 5 + device pci 18.6 off end # 8086 22c6 - I2C Port 6 + device pci 18.7 off end # 8086 22c7 - I2C Port 7 + device pci 1a.0 on end # 8086 2298 - Trusted Execution Engine + device pci 1b.0 on end # 8086 2284 - HD Audio + device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 + device pci 1c.1 on end # 8086 0000 - PCIe Root Port 2 + device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 + device pci 1c.3 on end # 8086 0000 - PCIe Root Port 4 + device pci 1e.0 off end # 8086 2286 - SIO - DMA + device pci 1e.3 off end # 8086 228a - HSUART 1 + device pci 1e.4 off end # 8086 228c - HSUART 2 + device pci 1f.0 on end # 8086 229c - LPC bridge + device pci 1f.3 on end # 8086 2292 - SMBus 0 + end +end diff --git a/src/mainboard/portwell/m107/dsdt.asl b/src/mainboard/portwell/m107/dsdt.asl new file mode 100644 index 0000000000..4eea7b93f4 --- /dev/null +++ b/src/mainboard/portwell/m107/dsdt.asl @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015-2018 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + /* Some generic macros */ + #include + + /* global NVS and variables */ + #include + + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + } + } + + /* Chipset specific sleep states */ + #include "acpi/sleepstates.asl" + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/portwell/m107/fadt.c b/src/mainboard/portwell/m107/fadt.c new file mode 100644 index 0000000000..7814106a4c --- /dev/null +++ b/src/mainboard/portwell/m107/fadt.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = asl_revision; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + acpi_fill_in_fadt(fadt); + + fadt->iapc_boot_arch &= ~ACPI_FADT_8042; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/portwell/m107/gpio.c b/src/mainboard/portwell/m107/gpio.c new file mode 100644 index 0000000000..5a73ca9148 --- /dev/null +++ b/src/mainboard/portwell/m107/gpio.c @@ -0,0 +1,253 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +/* South East Community */ +static const struct soc_gpio_map gpse_gpio_map[] = { + Native_M1,/* 00 MF_PLT_CLK0 */ + GPIO_NC, /* 01 PWM1 */ + GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */ + GPIO_NC, /* 03 MF_PLT_CLK4 */ + GPIO_NC, /* 04 MF_PLT_CLK3 */ + GPIO_NC, /* PWM0 05 */ + GPIO_NC, /* 06 MF_PLT_CLK5 */ + GPIO_NC, /* 07 MF_PLT_CLK2 */ + GPIO_NC, /* 15 SDMMC2_D3_CD_B */ + Native_M1, /* 16 SDMMC1_CLK */ + NATIVE_PU20K(1), /* 17 SDMMC1_D0 */ + GPIO_NC, /* 18 SDMMC2_D1 */ + GPIO_NC, /* 19 SDMMC2_CLK */ + NATIVE_PU20K(1),/* 20 SDMMC1_D2 */ + GPIO_NC, /* 21 SDMMC2_D2 */ + GPIO_NC, /* 22 SDMMC2_CMD */ + NATIVE_PU20K(1), /* 23 SDMMC1_CMD */ + NATIVE_PU20K(1), /* 24 SDMMC1_D1 */ + GPIO_NC, /* 25 SDMMC2_D0 */ + NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ + NATIVE_PU20K(1), /* 30 SDMMC3_D1 */ + Native_M1, /* 31 SDMMC3_CLK */ + NATIVE_PU20K(1), /* 32 SDMMC3_D3 */ + NATIVE_PU20K(1), /* 33 SDMMC3_D2 */ + NATIVE_PU20K(1), /* 34 SDMMC3_CMD */ + NATIVE_PU20K(1), /* 35 SDMMC3_D0 */ + NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ + NATIVE_PU20K(1), /* 46 LPC_CLKRUNB */ + NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ + Native_M1, /* 48 LPC_FRAMEB */ + Native_M1, /* 49 MF_LPC_CLKOUT1 */ + NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ + Native_M1, /* 51 MF_LPC_CLKOUT0 */ + NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ + Native_M1,/* SPI1_MISO */ + Native_M1, /* 61 SPI1_CS0_B */ + Native_M1, /* SPI1_CLK */ + NATIVE_PU20K(1), /* 63 MMC1_D6 */ + Native_M1, /* 62 SPI1_MOSI */ + NATIVE_PU20K(1), /* 65 MMC1_D5 */ + GPIO_NC, /* 66 SPI1_CS1_B */ + NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */ + NATIVE_PU20K(1), /* 68 MMC1_D7 */ + GPIO_NC, /* 69 MMC1_RCLK */ + Native_M1, /* 75 GPO USB_OC1_B */ + Native_M1, /* 76 PMU_RESETBUTTON_B */ + GPIO_NC, /* 77 GPIO_ALERT */ + Native_M1, /* 78 SDMMC3_PWR_EN_B */ + Native_M1, /* 79 GPI ILB_SERIRQ */ + Native_M1, /* 80 USB_OC0_B */ + NATIVE_INT_PU20K(1, L1), /* 81 SDMMC3_CD_B */ + Native_M1, /* 82 SPKR */ + Native_M1, /* 83 SUSPWRDNACK */ + SPARE_PIN, /* 84 spare pin */ + Native_M1, /* 85 SDMMC3_1P8_EN */ + GPIO_END +}; + +/* South West Community */ +static const struct soc_gpio_map gpsw_gpio_map[] = { + NATIVE_PU20K(1), /* 00 FST_SPI_D2 */ + NATIVE_PU20K(1), /* 01 FST_SPI_D0 */ + NATIVE_PU20K(1), /* 02 FST_SPI_CLK */ + NATIVE_PU20K(1), /* 03 FST_SPI_D3 */ + NATIVE_PU20K(1), /* 04 FST_SPI_CS1_B */ + NATIVE_PU20K(1), /* 05 FST_SPI_D1 */ + NATIVE_PU20K(1), /* 06 FST_SPI_CS0_B */ + GPIO_NC, /* 07 FST_SPI_CS2_B NC */ + GPIO_NC, /* 15 UART1_RTS_B */ + GPIO_NC, /* 16 UART1_RXD */ + GPIO_NC, /* 17 UART2_RXD */ + GPIO_NC, /* 18 UART1_CTS_B */ + GPIO_NC, /* 19 UART2_RTS_B */ + GPIO_NC, /* 20 UART1_TXD */ + GPIO_NC, /* 21 UART2_TXD */ + GPIO_NC, /* 22 UART2_CTS_B */ + Native_M2, /* 30 MF_HDA_CLK */ + Native_M2, /* 31 MF_HDA_RSTB */ + Native_M2, /* 32 MF_HDA_SDI0 */ + Native_M2, /* 33 MF_HDA_SDO */ + GPIO_NC, /* 34 MF_HDA_DOCKRSTB */ + Native_M2, /* 35 MF_HDA_SYNC */ + GPIO_NC, /* 36 MF_HDA_SDI1 */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 45 I2C5_SDA */ + GPIO_NC, /* 46 I2C4_SDA */ + GPIO_INPUT_NO_PULL, /* 47 I2C6_SDA SD_WP_1P8*/ + GPIO_NC, /* 48 I2C5_SCL */ + GPIO_NC, /* 49 I2C_NFC_SDA */ + GPIO_NC, /* 50 I2C4_SCL */ + GPIO_NC, /* 51 I2C6_SCL */ + GPIO_NC, /* 52 I2C_NFC_SCL */ + GPIO_NC, /* 60 I2C1_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */ + GPIO_NC, /* 62 I2C2_SDA */ + GPIO_NC, /* 63 I2C1_SCL */ + GPIO_NC, /* 64 I2C3_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */ + GPIO_NC, /* 66 I2C2_SCL */ + GPIO_NC, /* 67 I2C3_SCL */ + GPIO_NC, /* 75 SATA_GP0 */ + GPIO_NC, /* 76 GPI SATA_GP1 */ + Native_M1, /* 77 SATA_LEDN */ + GPIO_NC, /* 78 SATA_GP2 */ + Native_M1, /* 79 MF_SMB_ALERT_N */ + GPIO_INPUT_NO_PULL, /* 80 SATA_GP3, MMC1_RST */ + Native_M1, /* 81 MF_SMB_CLK */ + Native_M1, /* 82 MF_SMB_DATA */ + Native_M1, /* 90 PCIE_CLKREQ0B */ + Native_M1, /* 91 PCIE_CLKREQ1B */ + GPIO_NC, /* 92 GP_SSP_2_CLK */ + Native_M1, /* 93 PCIE_CLKREQ2B */ + GPIO_NC, /* 94 GP_SSP_2_RXD */ + Native_M1, /* 93 PCIE_CLKREQ3B */ + GPIO_NC, /* 96 GP_SSP_2_FS */ + GPIO_NC, /* 97 GP_SSP_2_TXD */ + GPIO_END +}; + +/* North Community */ +static const struct soc_gpio_map gpn_gpio_map[] = { + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 00 GPIO_DFX0 SMC_EXTSMI_N */ + GPIO_NC, /* 01 GPIO_DFX3 */ + GPIO_NC, /* 02 GPIO_DFX7 */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 03 GPIO_DFX1 PM_THRM_N */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 04 GPIO_DFX5 LID_N */ + GPIO_NC, /* 05 GPIO_DFX4 */ + GPIO_NC, /* 06 GPIO_DFX8 */ + GPIO_NC, /* 07 GPIO_DFX2 */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 08 GPIO_DFX6 WAKE1_N */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ + GPIO_NC, /* 16 SEC_GPIO_SUS10 */ + GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + /* 17 GPIO_SUS3 */ + GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 18 GPIO_SUS7 */ + GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 19 GPIO_SUS1 */ + GPIO_NC, /* 20 GPIO_SUS5 */ + GPIO_NC, /* 21 SEC_GPIO_SUS11 */ + GPIO_NC, /* 22 GPIO_SUS4 */ + GPIO_NC, /* 23 SEC_GPIO_SUS8 */ + Native_M6, /* 24 GPIO_SUS2 */ + GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */ + Native_M1, /* 26 CX_PREQ_B */ + GPIO_NC, /* 27 SEC_GPIO_SUS9 */ + Native_M1, /* 30 TRST_B */ + Native_M1, /* 31 TCK */ + GPIO_SKIP, /* 32 PROCHOT_B */ + GPIO_SKIP, /* 33 SVID0_DATA */ + Native_M1, /* 34 TMS */ + GPIO_NC, /* 35 CX_PRDY_B_2 */ + GPIO_NC, /* 36 TDO_2 */ + Native_M1, /* 37 CX_PRDY_B */ + GPIO_SKIP, /* 38 SVID0_ALERT_B */ + Native_M1, /* 39 TDO */ + GPIO_SKIP, /* 40 SVID0_CLK */ + Native_M1, /* 41 TDI */ + GPIO_NC, /* 45 GP_CAMERASB05 */ + GPIO_NC, /* 46 GP_CAMERASB02 */ + Native_M2, /* 47 GP_CAMERASB08 */ + GPIO_NC, /* 48 GP_CAMERASB00 */ + GPIO_NC, /* 49 GP_CAMERASBO6 */ + Native_M2, /* 50 GP_CAMERASB10 */ + GPIO_NC, /* 51 GP_CAMERASB03 */ + Native_M2, /* 52 GP_CAMERASB09 */ + GPIO_NC, /* 53 GP_CAMERASB01 */ + GPIO_NC, /* 54 GP_CAMERASB07 */ + Native_M2, /* 55 GP_CAMERASB11 */ + GPIO_NC, /* 56 GP_CAMERASB04 */ + GPIO_NC, /* 60 PANEL0_BKLTEN */ + Native_M1, /* 61 HV_DDI0_HPD */ + GPIO_NC, /* 62 HV_DDI2_DDC_SDA */ + GPIO_NC, /* 63 PANEL1_BKLTCTL */ + Native_M1, /* 64 HV_DDI1_HPD */ + Native_M1, /* 65 PANEL0_BKLTCTL */ + NATIVE_PU20K(1), /* 66 HV_DDI0_DDC_SDA */ + GPIO_NC, /* 67 HV_DDI2_DDC_SCL */ + NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ + GPIO_NC, /* 69 PANEL1_VDDEN */ + GPIO_NC, /* 70 PANEL1_BKLTEN */ + NATIVE_PU20K(1), /* 71 HV_DDI0_DDC_SCL */ + GPIO_NC, /* 72 PANEL0_VDDEN */ + GPIO_END +}; + +/* East Community */ +static const struct soc_gpio_map gpe_gpio_map[] = { + Native_M1, /* 00 PMU_SLP_S3_B */ + GPIO_NC, /* 01 PMU_BATLOW_B */ + Native_M1, /* 02 SUS_STAT_B */ + Native_M1, /* 03 PMU_SLP_S0IX_B */ + Native_M1, /* 04 PMU_AC_PRESENT */ + Native_M1, /* 05 PMU_PLTRST_B */ + Native_M1, /* 06 PMU_SUSCLK */ + GPIO_NC, /* 07 PMU_SLP_LAN_B */ + Native_M1, /* 08 PMU_PWRBTN_B */ + Native_M1, /* 09 PMU_SLP_S4_B */ + NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ + GPIO_NC, /* 11 PMU_WAKE_LAN_B */ + GPIO_NC, /* 15 MF_GPIO_3 */ + GPIO_NC, /* 16 MF_GPIO_7 */ + GPIO_NC, /* 17 MF_I2C1_SCL */ + GPIO_NC, /* 18 MF_GPIO_1 */ + GPIO_NC, /* 19 MF_GPIO_5 */ + GPIO_NC, /* 20 MF_GPIO_9 */ + GPIO_NC, /* 21 MF_GPIO_0 */ + GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */ + GPIO_NC, /* 23 MF_GPIO_8 */ + GPIO_NC, /* 24 MF_GPIO_2 */ + GPIO_NC, /* 25 MF_GPIO_6 */ + GPIO_NC, /* 26 MF_I2C1_SDA */ + GPIO_END +}; + +static struct soc_gpio_config gpio_config = { + /* BSW */ + .north = gpn_gpio_map, + .southeast = gpse_gpio_map, + .southwest = gpsw_gpio_map, + .east = gpe_gpio_map +}; + +struct soc_gpio_config *mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/portwell/m107/hda_verb.c b/src/mainboard/portwell/m107/hda_verb.c new file mode 100644 index 0000000000..868e5244da --- /dev/null +++ b/src/mainboard/portwell/m107/hda_verb.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +const u32 cim_verb_data[0] = {}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/mainboard/portwell/m107/irqroute.c similarity index 77% rename from src/soc/amd/picasso/bootblock/bootblock.c rename to src/mainboard/portwell/m107/irqroute.c index 62e4e1589f..e5d1d62949 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/mainboard/portwell/m107/irqroute.c @@ -1,6 +1,10 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -11,9 +15,6 @@ * GNU General Public License for more details. */ -#include +#include "irqroute.h" -asmlinkage void bootblock_c_entry(uint64_t base_timestamp) -{ - /* This function is here for building/linking only */ -} +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/portwell/m107/irqroute.h b/src/mainboard/portwell/m107/irqroute.h new file mode 100644 index 0000000000..6b7cb4169e --- /dev/null +++ b/src/mainboard/portwell/m107/irqroute.h @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +/* + * IR02h GFX INT(A) - PIRQ A + * IR0Bh PUNIT INT(A) - PIRQ F + * IR10h EMMC INT(ABCD) - PIRQ DEFG + * IR11h SDIO INT(A) - PIRQ B + * IR12h SD INT(A) - PIRQ C + * IR13h SATA INT(A) - PIRQ D + * IR14h XHCI INT(A) - PIRQ E + * IR15h LP Audio INT(A) - PIRQ F + * IR17h MMC INT(A) - PIRQ F + * IR18h SIO INT(ABCD) - PIRQ BADC + * IR1Ah TXE INT(A) - PIRQ F + * IR1Bh HD Audio INT(A) - PIRQ G + * IR1Ch PCIe INT(ABCD) - PIRQ EFGH + * IR1Dh EHCI INT(A) - PIRQ D + * IR1Eh SIO INT(ABCD) - PIRQ BDEF + * IR1Fh LPC INT(ABCD) - PIRQ HGBC +*/ +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(PUNIT_DEV, F, F, F, F), \ + PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, E, F, G, H), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) + +/* + * Route each PIRQ[A-H] to a PIC IRQ[0-15] + * Reserved: 0, 1, 2, 8, 13 + * PS2 keyboard: 12 + * ACPI/SCI: 9 + * Floppy: 6 + */ +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, 11), \ + PIRQ_PIC(B, 5), \ + PIRQ_PIC(C, 5), \ + PIRQ_PIC(D, 11), \ + PIRQ_PIC(E, 11), \ + PIRQ_PIC(F, 5), \ + PIRQ_PIC(G, 11), \ + PIRQ_PIC(H, 11) diff --git a/src/mainboard/portwell/m107/mainboard.c b/src/mainboard/portwell/m107/mainboard.c new file mode 100644 index 0000000000..d540c25246 --- /dev/null +++ b/src/mainboard/portwell/m107/mainboard.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +/* + * mainboard_enable is executed as first thing after + * enumerate_buses(). + */ +static void mainboard_enable(struct device *dev) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/portwell/m107/onboard.h b/src/mainboard/portwell/m107/onboard.h new file mode 100644 index 0000000000..fd4e4d6516 --- /dev/null +++ b/src/mainboard/portwell/m107/onboard.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +/* SD CARD gpio */ +#define SDCARD_CD 81 /* Not used */ + +#define ITE8528_CMD_PORT 0x6E +#define ITE8528_DATA_PORT 0x6F +#endif diff --git a/src/mainboard/portwell/m107/romstage.c b/src/mainboard/portwell/m107/romstage.c new file mode 100644 index 0000000000..0fe76864ec --- /dev/null +++ b/src/mainboard/portwell/m107/romstage.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ + struct region_device spd_rdev; + u8 spd_index = 0; + + if (CONFIG(ONBOARD_MEM_MICRON)) + spd_index = 1; + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found\n"); + + memory_params->PcdMemoryTypeEnable = MEM_DDR3; + memory_params->PcdMemorySpdPtr = (uintptr_t)rdev_mmap_full(&spd_rdev); + memory_params->PcdMemChannel0Config = 1; /* Memory down */ + memory_params->PcdMemChannel1Config = 2; /* Disabled */ +} + +void mainboard_after_memory_init(void) +{ + printk(BIOS_DEBUG, "%s/%s called\n", __FILE__, __func__); + + /* Disable the Braswell UART hardware for COM1. */ + pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, 0); +} diff --git a/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex b/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex new file mode 100644 index 0000000000..f18cbc2a87 --- /dev/null +++ b/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex @@ -0,0 +1,257 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Eltan B.V. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# +# 8 Gb DDR3 (1600 MHz 11-11-11) Micron MT41K512M16HA-125:A +# +# SINGLE DIE +# + +# 512MBx16 64Mx16x8 ( 8 bank, 16 Rows, 10 Col, 2 KB page size ) +# 5-6-7-8-9-10-11 +# DDR3L-1600 +# tCk 1.25ns +# tRCD 13.75ns +# tRP 13.75ns +# tRAS 35ns +# tRC 48.75ns +# CL-tRCD-tRP 11-11-11 + +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 3 = 384 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 128 +23 + +# 1 SPD Revision +# 0x10 = Revision 1.0 +10 + +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0c = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SODIMM +# bits[6:4]: 0 = Not hybrid +# bits[7]: 0 = Not hybrid +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bits[7]: reserverd +05 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 4 = 16 Row Address Bits +# bits[7:6]: 0 = reserved +21 + +# 6 Module Nominal Voltage +# bits[0]: 0 = 1.5V operable +# bits[1]: 1 = 1.35V operable +# bits[2]: 0 = NOT 1.25V operable +# bits[7:3]: reserved +02 + +# 7 Module Organization +# bits[2:0]: 010b = 16 bits SDRAM device +# bits[5:3]: 000b = 1 ranks +# bits[7:6]: reserved +02 + +# 8 Module Memory Bus width +# bits[2:0]: 3 = 64 bits pirmary bus width +# bits[4:3]: 0 = 0 bits bus witdth extension +# bits[7:5]: reserved +03 + +# 9 Fine Timebase (FTB) dividend / divisor +# bits[3:0]: 1 = Divisor +# bits[7:4]: 1 = Dividend +11 + +# 10 Medium Timebase (MTB) dividend +# bits[7:0]: 0 = 1 (timebase 0.125ns) +01 + +# 11 Medium Timebase (MTB) divisor +# bits[7:0]: 8 (timebase 0.125ns) +08 + +# 12 SDRAM Minimum cycle time (tCKmin) +# 0xA tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +0A + +# 13 Reserved +00 + +# 14 CAS Latencies supported, Least Significate Byte +# Support 5,6,7,8,9,10,11 +FE + +# 15 CAS Latencies supported, Most Significate Byte +# No supporting CL 12-18 +00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x69 tAA = 13.125ns (offset = 00) DDR3-1600K downbin +69 + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 tWR = 15 ns +78 + +# 18 Minimum RAS to CAS Delay Time (tRCDmin) +# 0x69 tRCD = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 0x3C tRRD = 7.5ns DDR3-1600, 2KB +3C + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x69 tRP = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 21 Upper Nibble for tRAS and tRC +# 3:0 : 1 higher tRAS = 35ns +# 7:0 : 1 higher tRC = 48.125ns +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant byte +# lower 0x118 : tRAS = 35ns DDR3-1600 +18 + +# 23 Minimum Active to Precharge Delay Time (tRCmin), Most Significant byte +# lower 0x181 : tRC = 48.125ns (offset 00) DDR3-1600K downbin +81 + +# 24 Minimum Refresh Recovery Delay time (tRFCmin), Least Significant byte +# lower 0xAF0 : tRFC = 350ns 8 Gb +F0 + +# 25 Minimum Refresh Recovery Delay time (tRFCmin), Most Significant byte +# higher 0xAF0 : tRFC = 350ns 8 Gb +0A + +# 26 tWTRmin +# 0x3C : tWTR = 7.5 ns (DDR3) +3C + +# 27 tRTPmin +# 0x3C : tRTP = 7.5 ns (DDR3) +3C + +# 28 Upper Nibble for tFAW +# Bit [3:0] : 1 = higher 0x140 tFAW = 40ns +01 + +# 29 tFAWmin Lower +# lower 0x140 : tFAW = 40ns +40 + +# 30 SDRAM Optional Features +# byte [0] : 1 = RZQ/6 is support +# byte [1] : 1 = RZQ/7 is supported +# byte [7] : 1 = DLL-Off Mode support +83 + +# 31 Thermal options +# byte [0] : 1 = 0 - 95C +# byte [2] : 1 = Auto Self Refresh (ASR) is supported +# byte [7] : 1 = Partial Array Self Refres (PASR) is supported +85 + +# 32 Module Thermal support +# byte [0] : 0 = Thermal sensor accuracy undefined +# byte [7] : 0 = No thermal sensor +00 + +# 33 SDRAM device type +# byte [1:0] : 00b = Signal Loading not specified +# byte [6:4] : 000b = Die count not specified +# byte [7] : 1 = Non-Standard Device +80 + +# 34 Fine tCKmin +# 0x00 tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +00 + +# 35 Fine tAAmin +# 0x00 tAA = 13.125ns (tAAmin offset = 00) DDR3-1600K downbin +00 + +# 36 Fine tRCDmin +# 0x00 tRCD = 13.125ns DDR3-1600K downbin +00 + +# 37 Fine tRPmin +# 0x00 tRP = 13.125ns (offset 00) DDR3-1600K downbin +00 + +# 38 Fine tRCmin +# 0x00 tRC = 48.125ns (offset 00) DDR3-1600K downbin +00 + +# 39-59 reserved, general section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 60-116 Module specific section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 + +# 117-118 Module Manufacturer +80 2C + +# 119 Module Manufacturing Location +01 + +# 120-121 Module Manufacturing Date +13 0A + +# 122-125 Module Serial number +00 00 00 00 + +# 126-127 SPD CRC +00 00 + +# 128-145 Module Part number +4D 54 34 31 4B 35 31 32 4D 31 36 48 41 2D 31 32 +35 00 + +# 145-146 Module revision code +00 00 + +# 148-149 DRAM Manufacturer ID code +80 2C + +# 150-175 Manufacturer Specific Data +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 + +# 176-255 Open for Customer Use + +# 176 - 255 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex b/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex new file mode 100644 index 0000000000..64faf1e163 --- /dev/null +++ b/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex @@ -0,0 +1,254 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2018-2019 Eltan B.V. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# +# 8 Gb DDR3 (1600 MHz 11-11-11) Samsung K4B8G1646D-MYK0 +# +# DUAL DIE +# +# 512Mb x16 ( 8 bank, 16 Rows, 10 Col, 2 KB page size ) +# 5-6-7-8-9-10-11 +# DDR3L-1600 +# tCk 1.25ns +# tRCD 13.75ns +# tRP 13.75ns +# tRAS 35ns +# tRC 48.75ns +# CL-tRCD-tRP 11-11-11 + +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 3 = 384 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 128 +23 + +# 1 SPD Revision +# 0x10 = Revision 1.0 +10 + +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0c = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SODIMM +# bits[6:4]: 0 = Not hybrid +# bits[7]: 0 = Not hybrid +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bits[7]: reserverd +04 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 100b = 16 Row Address Bits +# bits[7:6]: 0 = reserved +21 + +# 6 Module Nominal Voltage +# bits[0]: 0 = 1.5V operable +# bits[1]: 1 = 1.35V operable +# bits[2]: 0 = NOT 1.25V operable +# bits[7:3]: reserved +02 + +# 7 Module Organization +# bits[2:0]: 010b = 16 bits SDRAM device +# bits[5:3]: 001b = 2 ranks +# bits[7:6]: reserved +0A + +# 8 Module Memory Bus width +# bits[2:0]: 3 = 64 bits pirmary bus width +# bits[4:3]: 0 = 0 bits bus witdth extension +# bits[7:5]: reserved +03 + +# 9 Fine Timebase (FTB) dividend / divisor +# bits[3:0]: 1 = Divisor +# bits[7:4]: 1 = Dividend +11 + +# 10 Medium Timebase (MTB) dividend +# bits[7:0]: 0 = 1 (timebase 0.125ns) +01 + +# 11 Medium Timebase (MTB) divisor +# bits[7:0]: 8 (timebase 0.125ns) +08 + +# 12 SDRAM Minimum cycle time (tCKmin) +# 0xA tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +0A + +# 13 Reserved +00 + +# 14 CAS Latencies supported, Least Significate Byte +# Support 5,6,7,8,9,10,11 +FE + +# 15 CAS Latencies supported, Most Significate Byte +# Not supporting CL 12-18 +00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x69 tAA = 13.125ns (offset = 00) DDR3-1600K downbin +69 + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 tWR = 15 ns +78 + +# 18 Minimum RAS to CAS Delay Time (tRCDmin) +# 0x69 tRCD = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 48 tRRD = 6.0ns DDR3-1600, 1KB +30 + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x69 tRP = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 21 Upper Nibble for tRAS and tRC +# 3:0 : 1 higher tRAS = 35ns +# 7:0 : 1 higher tRC = 48.125ns +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant byte +# lower 0x118 : tRAS = 35ns DDR3-1600 +18 + +# 23 Minimum Active to Precharge Delay Time (tRCmin), Most Significant byte +# lower 0x181 : tRC = 48.125ns (offset 00) DDR3-1600K downbin +81 + +# 24 Minimum Refresh Recovery Delay time (tRFCmin), Least Significant byte +# lower 0x680 : tRFC = 208ns 4 Gb +80 + +# 25 Minimum Refresh Recovery Delay time (tRFCmin), Most Significant byte +# higher 0x680 : tRFC = 208ns 4 Gb +06 + +# 26 tWTRmin +# 0x3C : tWTR = 7.5 ns (DDR3) +3C + +# 27 tRTPmin +# 0x3C : tRTP = 7.5 ns (DDR3) +3C + +# 28 Upper Nibble for tFAW +# Bit [3:0] : 1 = higher 0x140 tFAW = 40ns DDR3-1600K, 2 KB page size +01 + +# 29 tFAWmin Lower +# lower 0x140 : tFAW = 40ns DDR3-1600K, 2 KB page size +40 + +# 30 SDRAM Optional Features +# byte [0] : 1 = RZQ/6 is support +# byte [1] : 1 = RZQ/7 is supported +# byte [7] : 1 = DLL-Off Mode support +83 + +# 31 Thermal options +# byte [2]: 1 = Auto Self Refresh (ASR) is supported +04 + +# 32 Module Thermal support +# byte [0] : 0 = Thermal sensor accuracy undefined +# byte [7] : 0 = No thermal sensor +00 + +# 33 SDRAM device type +# byte [1:0] : 01b = multi load stack +# byte [6:4] : 100b = 8 die +# byte [7] : 0 = Standard Device +41 + +# 34 Fine tCKmin +# 0x00 tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +00 + +# 35 Fine tAAmin +# 0x00 tAA = 13.125ns (tAAmin offset = 00) DDR3-1600K downbin +00 + +# 36 Fine tRCDmin +# 0x00 tRCD = 13.125ns DDR3-1600K downbin +00 + +# 37 Fine tRPmin +# 0x00 tRP = 13.125ns (offset 00) DDR3-1600K downbin +00 + +# 38 Fine tRCmin +# 0x00 tRC = 48.125ns (offset 00) DDR3-1600K downbin +00 + +# 39-59 reserved, general section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 60-116 Module specific section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 + +# 117-118 Module Manufacturer +80 CE + +# 119 Module Manufacturing Location +01 + +# 120-121 Module Manufacturing Date +12 1B + +# 122-125 Module Serial number +00 00 00 00 + +# 126-127 SPD CRC +00 00 + +# 128-145 Module Part number +4B 34 42 38 47 31 36 34 36 44 2D 4D 59 4B 30 20 +20 20 + +# 145-146 Module revision code +00 00 + +# 148-149 DRAM Manufacturer ID code +80 CE + +# 150-175 Manufacturer Specific Data +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 + +# 176-255 Open for Customer Use + +# 176 - 255 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/portwell/m107/w25q64.c b/src/mainboard/portwell/m107/w25q64.c new file mode 100644 index 0000000000..bc908f04b3 --- /dev/null +++ b/src/mainboard/portwell/m107/w25q64.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +/* + * SPI lockdown configuration + */ +#define SPI_OPMENU_0 CMD_W25_WRSR /* Write Status Register */ +#define SPI_OPTYPE_0 SPI_OPTYPE_WR_NOADDR /* Write, no address */ + +#define SPI_OPMENU_1 CMD_W25_PP /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 SPI_OPTYPE_WR_ADDR /* Write, address required */ + +#define SPI_OPMENU_2 CMD_W25_READ /* Read Data */ +#define SPI_OPTYPE_2 SPI_OPTYPE_RD_ADDR /* Read, address required */ + +#define SPI_OPMENU_3 CMD_W25_RDSR /* Read Status Register */ +#define SPI_OPTYPE_3 SPI_OPTYPE_RD_NOADDR /* Read, no address */ + +#define SPI_OPMENU_4 CMD_W25_SE /* Sector Erase */ +#define SPI_OPTYPE_4 SPI_OPTYPE_WR_ADDR /* Write, address required */ + +#define SPI_OPMENU_5 CMD_W25_RDID /* Read ID */ +#define SPI_OPTYPE_5 SPI_OPTYPE_RD_NOADDR /* Read, no address */ + +#define SPI_OPMENU_6 CMD_W25_BE /* BE: Block Erase */ +#define SPI_OPTYPE_6 SPI_OPTYPE_WR_ADDR /* Write, address required */ + +#define SPI_OPMENU_7 CMD_W25_FAST_READ /* FAST: Fast Read */ +#define SPI_OPTYPE_7 SPI_OPTYPE_RD_ADDR /* Read, address required */ + +#define SPI_OPPREFIX CMD_W25_WREN /* WREN only to be inline */ + /* with flashrom */ + +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) + +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) + +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) + +#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) + +static const struct spi_config spi_config = { + .preop = CMD_W25_WREN, + .optype = SPI_OPTYPE, + .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, + .lvscc = SPI_VSCC, + .uvscc = SPI_VSCC, +}; + +int mainboard_get_spi_config(struct spi_config *cfg) +{ + memcpy(cfg, &spi_config, sizeof(*cfg)); + + return 0; +} diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index 2372b9d280..ecde9e4774 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -5,6 +5,7 @@ config BOARD_PURISM_BASEBOARD_LIBREM_SKL select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_SKYLAKE select MAINBOARD_USES_FSP2_0 select SPD_READ_BY_WORD diff --git a/src/mainboard/purism/librem_skl/hda_verb.c b/src/mainboard/purism/librem_skl/hda_verb.c index c0de990d80..ea89f00a53 100644 --- a/src/mainboard/purism/librem_skl/hda_verb.c +++ b/src/mainboard/purism/librem_skl/hda_verb.c @@ -1,8 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation - * (Written by Naresh G Solanki for Intel Corp.) + * Copyright (C) 2019 Purism SPC. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -14,70 +13,60 @@ * GNU General Public License for more details. */ -#include -#include -#include #include -#include -#include -#include "hda_verb.h" +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */ + 0x19910269, /* Subsystem ID */ + 0x0000000c, /* Number of jacks (NID entries) */ -static void codecs_init(u8 *base, u32 codec_mask) -{ - int i; + 0x0017ff00, /* Function Reset */ + 0x0017ff00, /* Double Function Reset */ + 0x0017ff00, + 0x0017ff00, - /* Can support up to 4 codecs */ - for (i = 3; i >= 0; i--) { - if (codec_mask & (1 << i)) - hda_codec_init(base, i, cim_verb_data_size, - cim_verb_data); - } + /* Bits 31:28 - Codec Address */ + /* Bits 27:20 - NID */ + /* Bits 19:8 - Verb ID */ + /* Bits 7:0 - Payload */ - if (pc_beep_verbs_size) - hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs); -} + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x19910269 */ + AZALIA_SUBVENDOR(0x0, 0x19910269), -static void mb_hda_codec_init(void *unused) -{ - static struct soc_intel_skylake_config *config; - u8 *base; - struct resource *res; - u32 codec_mask; - struct device *dev; + /* Pin Widget Verb Table */ - dev = SA_DEV_ROOT; - /* Check if HDA is enabled, else return */ - if (dev == NULL || dev->chip_info == NULL) - return; + /* Pin Complex (NID 0x12) */ + AZALIA_PIN_CFG(0x0, 0x12, 0x40000000), - config = dev->chip_info; + /* Pin Complex (NID 0x14) */ + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), - /* - * IoBufferOwnership 0:HD-A Link, 1:Shared HD-A Link and I2S Port, - * 3:I2S Ports. In HDA mode where codec need to be programmed with - * verb table - */ - if (config->IoBufferOwnership == 3) - return; + /* Pin Complex (NID 0x15) */ + AZALIA_PIN_CFG(0x0, 0x15, 0x04214020), - /* Find base address */ - dev = pcidev_path_on_root(PCH_DEVFN_HDA); - if (dev == NULL) - return; - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (!res) - return; + /* Pin Complex (NID 0x17) */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), - base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "HDA: base = %p\n", base); + /* Pin Complex (NID 0x18) */ + AZALIA_PIN_CFG(0x0, 0x18, 0x04a19040), - codec_mask = hda_codec_detect(base); + /* Pin Complex (NID 0x19) */ + AZALIA_PIN_CFG(0x0, 0x19, 0x90a70130), - if (codec_mask) { - printk(BIOS_DEBUG, "HDA: codec_mask = %02x\n", codec_mask); - codecs_init(base, codec_mask); - } -} + /* Pin Complex (NID 0x1A) */ + AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0), -BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, mb_hda_codec_init, NULL); + /* Pin Complex (NID 0x1B) */ + AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0), + + /* Pin Complex (NID 0x1D) */ + AZALIA_PIN_CFG(0x0, 0x1D, 0x40548505), + + /* Pin Complex (NID 0x1E) */ + AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/purism/librem_skl/hda_verb.h b/src/mainboard/purism/librem_skl/hda_verb.h deleted file mode 100644 index 660ad0c10c..0000000000 --- a/src/mainboard/purism/librem_skl/hda_verb.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef HDA_VERB_H -#define HDA_VERB_H - -#include - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */ - 0x19910269, /* Subsystem ID */ - 0x0000000c, /* Number of jacks (NID entries) */ - - 0x0017ff00, /* Function Reset */ - 0x0017ff00, /* Double Function Reset */ - 0x0017ff00, - 0x0017ff00, - - /* Bits 31:28 - Codec Address */ - /* Bits 27:20 - NID */ - /* Bits 19:8 - Verb ID */ - /* Bits 7:0 - Payload */ - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x19910269 */ - AZALIA_SUBVENDOR(0x0, 0x19910269), - - /* Pin Widget Verb Table */ - - /* Pin Complex (NID 0x12) */ - AZALIA_PIN_CFG(0x0, 0x12, 0x40000000), - - /* Pin Complex (NID 0x14) */ - AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), - - /* Pin Complex (NID 0x15) */ - AZALIA_PIN_CFG(0x0, 0x15, 0x04214020), - - /* Pin Complex (NID 0x17) */ - AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), - - /* Pin Complex (NID 0x18) */ - AZALIA_PIN_CFG(0x0, 0x18, 0x04a19040), - - /* Pin Complex (NID 0x19) */ - AZALIA_PIN_CFG(0x0, 0x19, 0x90a70130), - - /* Pin Complex (NID 0x1A) */ - AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0), - - /* Pin Complex (NID 0x1B) */ - AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0), - - /* Pin Complex (NID 0x1D) */ - AZALIA_PIN_CFG(0x0, 0x1D, 0x40548505), - - /* Pin Complex (NID 0x1E) */ - AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0), -}; - -const u32 pc_beep_verbs[] = { -}; -AZALIA_ARRAY_SIZES; -#endif diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 3ba9d2c331..0ceef6a2fd 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -58,7 +58,7 @@ chip northbridge/intel/i945 register "docking_supported" = "1" register "p_cnt_throttling_supported" = "1" - register "ide_legacy_combined" = "0x1" + register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 1dfa02d317..68f2ba437f 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -66,7 +66,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "0" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - register "p_cnt_throttling_supported" = "1" register "xhci_overcurrent_mapping" = "0x00080401" register "xhci_switchable_ports" = "0x0f" diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index f1016210e6..76ad9859c6 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -71,7 +71,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "0" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 1, 1 }" - register "p_cnt_throttling_supported" = "1" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0f" diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 6760f03611..9e02d9a901 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -29,15 +30,13 @@ #define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1 -#if ENV_RAMSTAGE -#include #include "ec.h" #include void fill_lb_gpios(struct lb_gpios *gpios) { - struct device *dev = pcidev_on_root(0x1f, 0); - u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); u8 lid = ec_read(0x83); struct lb_gpio chromeos_gpios[] = { @@ -60,36 +59,23 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif int get_write_protect_state(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; } int get_recovery_mode_switch(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; } void init_bootmode_straps(void) { u32 flags = 0; -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif /* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */ if (get_gpio(GPIO_SPI_WP)) @@ -98,7 +84,7 @@ void init_bootmode_straps(void) if (!get_gpio(GPIO_REC_MODE)) flags |= (1 << FLAG_REC_MODE); - pci_write_config32(dev, SATA_SP, flags); + pci_s_write_config32(dev, SATA_SP, flags); } static const struct cros_gpio cros_gpios[] = { diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index feae5bf1e8..1a4ecfdd54 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -64,7 +64,6 @@ chip northbridge/intel/sandybridge register "gen3_dec" = "0x00fc1601" register "c2_latency" = "1" - register "p_cnt_throttling_supported" = "0" device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/samsung/lumpy/gpio.c b/src/mainboard/samsung/lumpy/gpio.c index 9d07e643cf..103763d6e2 100644 --- a/src/mainboard/samsung/lumpy/gpio.c +++ b/src/mainboard/samsung/lumpy/gpio.c @@ -22,7 +22,7 @@ * GPIO SET 1 includes GPIO0 to GPIO31 */ -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, /* CHP3_SERDBG */ .gpio1 = GPIO_MODE_GPIO, /* KBC3_EXTSMI# */ .gpio2 = GPIO_MODE_NATIVE, /* CHP3_ALSINT# (Light Sensor) */ @@ -57,7 +57,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio31 = GPIO_MODE_NATIVE, /* KBC3_AC_PRESENT */ }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_OUTPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -92,7 +92,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio31 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_LOW, .gpio1 = GPIO_LEVEL_LOW, .gpio2 = GPIO_LEVEL_LOW, @@ -127,7 +127,7 @@ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio31 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio0 = GPIO_NO_INVERT, .gpio1 = GPIO_INVERT, .gpio2 = GPIO_INVERT, @@ -150,7 +150,7 @@ const struct pch_gpio_set1 pch_gpio_set1_invert = { * GPIO SET 2 includes GPIO32 to GPIO63 */ -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, /* PCI3_CLKRUN# */ .gpio33 = GPIO_MODE_GPIO, /* Onboard Memory Capacity */ .gpio34 = GPIO_MODE_NONE, @@ -185,7 +185,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio63 = GPIO_MODE_NATIVE, /* CHP3_SLPS5# */ }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, .gpio33 = GPIO_DIR_INPUT, .gpio34 = GPIO_DIR_INPUT, @@ -220,7 +220,7 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio63 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_LOW, .gpio33 = GPIO_LEVEL_LOW, .gpio34 = GPIO_LEVEL_LOW, @@ -259,7 +259,7 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { * GPIO SET 3 includes GPIO64 to GPIO75 */ -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_NONE, .gpio65 = GPIO_MODE_NONE, .gpio66 = GPIO_MODE_NONE, @@ -274,7 +274,7 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio75 = GPIO_MODE_NATIVE, /* SIO3_THERM_SMDATA# */ }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_INPUT, .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, @@ -289,7 +289,7 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio75 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_LOW, .gpio65 = GPIO_LEVEL_LOW, .gpio66 = GPIO_LEVEL_LOW, @@ -304,7 +304,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio75 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set2 pch_gpio_set2_reset = { +static const struct pch_gpio_set2 pch_gpio_set2_reset = { .gpio38 = GPIO_RESET_RSMRST, .gpio43 = GPIO_RESET_RSMRST, }; diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 9ec4218b01..f316b2256f 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -28,13 +29,10 @@ #define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1 -#if ENV_RAMSTAGE -#include - void fill_lb_gpios(struct lb_gpios *gpios) { - struct device *dev = pcidev_on_root(0x1f, 0); - u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); struct lb_gpio chromeos_gpios[] = { /* Write Protect: GPIO68 = CHP3_SPI_WP */ @@ -57,36 +55,23 @@ void fill_lb_gpios(struct lb_gpios *gpios) }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif int get_write_protect_state(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; } int get_recovery_mode_switch(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; } void init_bootmode_straps(void) { u32 flags = 0; -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif /* Write Protect: GPIO68 = CHP3_SPI_WP, active high */ if (get_gpio(GPIO_SPI_WP)) @@ -95,7 +80,7 @@ void init_bootmode_straps(void) if (!get_gpio(GPIO_REC_MODE)) flags |= (1 << FLAG_REC_MODE); - pci_write_config32(dev, SATA_SP, flags); + pci_s_write_config32(dev, SATA_SP, flags); } static const struct cros_gpio cros_gpios[] = { diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index 060fc40bb6..034e166ca1 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -48,7 +48,6 @@ chip northbridge/intel/sandybridge register "sata_port_map" = "0x3" register "c2_latency" = "1" - register "p_cnt_throttling_supported" = "0" register "gen1_dec" = "0x00fc1601" # SuperIO range is 0x700-0x73f diff --git a/src/mainboard/samsung/stumpy/gpio.c b/src/mainboard/samsung/stumpy/gpio.c index eb04c784e2..282f816c53 100644 --- a/src/mainboard/samsung/stumpy/gpio.c +++ b/src/mainboard/samsung/stumpy/gpio.c @@ -22,7 +22,7 @@ * GPIO SET 1 includes GPIO0 to GPIO31 */ -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, /* CHP3_SERDBG */ .gpio1 = GPIO_MODE_GPIO, /* SIO3_EXTSMI# */ .gpio2 = GPIO_MODE_NONE, @@ -57,7 +57,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio31 = GPIO_MODE_NATIVE, /* ACPRESENT (pullup) */ }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_OUTPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -92,7 +92,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio31 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_LOW, .gpio1 = GPIO_LEVEL_LOW, .gpio2 = GPIO_LEVEL_LOW, @@ -131,7 +131,7 @@ const struct pch_gpio_set1 pch_gpio_set1_level = { * GPIO SET 2 includes GPIO32 to GPIO63 */ -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, /* PCI3_CLKRUN# */ .gpio33 = GPIO_MODE_NONE, .gpio34 = GPIO_MODE_NONE, @@ -166,7 +166,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio63 = GPIO_MODE_NATIVE, /* CHP3_SLPS5# */ }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, .gpio33 = GPIO_DIR_INPUT, .gpio34 = GPIO_DIR_INPUT, @@ -201,7 +201,7 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio63 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_LOW, .gpio33 = GPIO_LEVEL_LOW, .gpio34 = GPIO_LEVEL_LOW, @@ -240,7 +240,7 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { * GPIO SET 3 includes GPIO64 to GPIO75 */ -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_NATIVE, /* CLK3_SIO48 */ .gpio65 = GPIO_MODE_NONE, .gpio66 = GPIO_MODE_NONE, @@ -255,7 +255,7 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio75 = GPIO_MODE_NATIVE, /* SIO3_THERM_SMDATA# */ }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio64 = GPIO_DIR_INPUT, .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, @@ -270,7 +270,7 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio75 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_LOW, .gpio65 = GPIO_LEVEL_LOW, .gpio66 = GPIO_LEVEL_LOW, diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index 95c59dfca3..aff01302b2 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -50,7 +50,6 @@ chip northbridge/intel/sandybridge register "gen2_dec" = "0x000c0a01" register "gen3_dec" = "0x00000000" register "gen4_dec" = "0x00000000" - register "p_cnt_throttling_supported" = "0" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/sapphire/pureplatinumh61/gpio.c b/src/mainboard/sapphire/pureplatinumh61/gpio.c index 5dbb223bfc..b58e0edca4 100644 --- a/src/mainboard/sapphire/pureplatinumh61/gpio.c +++ b/src/mainboard/sapphire/pureplatinumh61/gpio.c @@ -89,7 +89,7 @@ static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio29 = GPIO_NO_INVERT, }; -const struct pch_gpio_set1 pch_gpio_set1_reset = { +static const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio6 = GPIO_RESET_PWROK, .gpio7 = GPIO_RESET_PWROK, .gpio8 = GPIO_RESET_PWROK, @@ -135,7 +135,7 @@ static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio60 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set2 pch_gpio_set2_reset = { +static const struct pch_gpio_set2 pch_gpio_set2_reset = { .gpio35 = GPIO_RESET_PWROK, .gpio37 = GPIO_RESET_PWROK, .gpio38 = GPIO_RESET_PWROK, @@ -144,22 +144,22 @@ const struct pch_gpio_set2 pch_gpio_set2_reset = { .gpio60 = GPIO_RESET_PWROK, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio68 = GPIO_MODE_GPIO, .gpio69 = GPIO_MODE_GPIO, .gpio72 = GPIO_MODE_GPIO, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio68 = GPIO_DIR_INPUT, .gpio69 = GPIO_DIR_INPUT, .gpio72 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { }; -const struct pch_gpio_set3 pch_gpio_set3_reset = { +static const struct pch_gpio_set3 pch_gpio_set3_reset = { .gpio68 = GPIO_RESET_PWROK, .gpio69 = GPIO_RESET_PWROK, .gpio72 = GPIO_RESET_PWROK, diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index c931e1008a..22d37bfdc2 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -83,6 +83,10 @@ #define SPI_REG_OPMENU_L 0xa8 #define SPI_REG_OPMENU_H 0xac +#define SD_CAP_BYP 0x810 +#define SD_CAP_BYP_EN 0x5A +#define SD_CAP_BYP_REG1 0x814 + /** \brief This function can decide if a given MAC address is valid or not. * Currently, addresses filled with 0xff or 0x00 are not valid. * @param mac Buffer to the MAC address to check @@ -265,6 +269,21 @@ static void mainboard_final(void *chip_info) ((SPI_OPTYPE << 16) | SPI_OPPREFIX)); write32((spi_base + SPI_REG_OPMENU_L), SPI_OPMENU_LOWER); write32((spi_base + SPI_REG_OPMENU_H), SPI_OPMENU_UPPER); + + /* Set SD-Card speed to HS mode only. */ + dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); + if (dev) { + uint32_t reg; + struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + + write32(res2mmio(res, SD_CAP_BYP, 0), SD_CAP_BYP_EN); + reg = read32(res2mmio(res, SD_CAP_BYP_REG1, 0)); + /* Disable all UHS-I SD-Card speed modes, keep only HS mode. */ + reg &= ~0x2000f800; + write32(res2mmio(res, SD_CAP_BYP_REG1, 0), reg); + } } /* The following function performs board specific things. */ diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c index 91a30bfe0e..dd9736401a 100644 --- a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c @@ -47,12 +47,12 @@ static const struct pad_config gpio_table[] = { /* SDIO -- unused */ PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), /* SDIO_CLK */ - PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* SDIO_D0 */ + PAD_CFG_GPI(GPIO_167, DN_20K, DEEP), /* SDIO_D0 */ /* Configure SDIO to enable power gating. */ PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1), /* SDIO_D1 */ - PAD_CFG_GPI(GPIO_169, NONE, DEEP), /* SDIO_D2 */ - PAD_CFG_GPI(GPIO_170, NONE, DEEP), /* SDIO_D3 */ - PAD_CFG_GPI(GPIO_171, NONE, DEEP), /* SDIO_CMD */ + PAD_CFG_GPI(GPIO_169, DN_20K, DEEP), /* SDIO_D2 */ + PAD_CFG_GPI(GPIO_170, DN_20K, DEEP), /* SDIO_D3 */ + PAD_CFG_GPI(GPIO_171, DN_20K, DEEP), /* SDIO_CMD */ /* SDCARD */ /* Pull down clock by 20K. */ @@ -135,7 +135,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(OSC_CLK_OUT_4, DN_20K, DEEP), /* PMU Signals */ - PAD_CFG_GPI(PMU_AC_PRESENT, NONE, DEEP), /* PMU_AC_PRESENT */ + PAD_CFG_GPI(PMU_AC_PRESENT, DN_20K, DEEP), /* PMU_AC_PRESENT */ PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1), /* PMU_BATLOW_N */ PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */ PAD_CFG_NF(PMU_PWRBTN_B, NONE, DEEP, NF1), /* PMU_PWRBTN_N */ @@ -173,7 +173,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_198, DN_20K, DEEP), /* PNL1_BKLTCTL */ /* DDI[0:1]_HPD -- unused */ - PAD_CFG_GPI(GPIO_199, NONE, DEEP), /* XHPD_DP */ + PAD_CFG_GPI(GPIO_199, DN_20K, DEEP), /* XHPD_DP */ PAD_CFG_GPI(GPIO_200, DN_20K, DEEP), /* unused */ /* MDSI signals -- unused */ @@ -193,7 +193,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(PMC_SPI_CLK, DN_20K, DEEP), /* PMIC Signals unused signals related to an old PMIC interface. */ - PAD_CFG_GPO(PMIC_PWRGOOD, 1, DEEP), /* PMIC_PWRGOOD */ + PAD_CFG_NF(PMIC_PWRGOOD, UP_20K, DEEP, NF1), /* PMIC_PWRGOOD */ PAD_CFG_GPI(PMIC_RESET_B, DN_20K, DEEP), /* PMIC_RESET_B */ PAD_CFG_TERM_GPO(GPIO_213, 0, DN_20K, DEEP), /* NFC_OUT_RESERVE */ PAD_CFG_TERM_GPO(GPIO_214, 0, DN_20K, DEEP), /* NFC_EN */ diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c index d1ca6793ea..b316d9727d 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c @@ -123,9 +123,9 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, UP_1K, DEEP, NF1, Tx1RxDCRx1, MASK), /* Not connected */ - PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_134, NONE, DEEP, Tx0RxDCRx0, MASK), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_134, UP_20K, DEEP, Tx0RxDCRx0, MASK), /* Not connected */ - PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_135, NONE, DEEP, Tx0RxDCRx0, MASK), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_135, UP_20K, DEEP, Tx0RxDCRx0, MASK), /* GPIO_PWRBTN# */ PAD_CFG_GPI_SCI_IOS(GPIO_136, UP_20K, DEEP, EDGE_SINGLE, INVERT, TxDRxE, SAME), @@ -276,7 +276,7 @@ static const struct pad_config gpio_table[] = { SAME), /* Not connected */ - PAD_CFG_GPO_GPIO_DRIVER(PMIC_PWRGOOD, 1, DEEP, UP_1K), + PAD_CFG_NF(PMIC_PWRGOOD, UP_20K, DEEP, NF1), PAD_CFG_GPO_GPIO_DRIVER(GPIO_214, 1, DEEP, DN_20K), PAD_CFG_GPO_GPIO_DRIVER(GPIO_215, 1, DEEP, DN_20K), /* THERMTRIP_1V8# - Connected to CPLD */ diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c index 7890ee0211..2502a921fe 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c @@ -26,10 +26,6 @@ #include #include -#define SD_CAP_BYP 0x810 -#define SD_CAP_BYP_EN 0x5A -#define SD_CAP_BYP_REG1 0x814 - void variant_mainboard_final(void) { struct device *dev; @@ -42,21 +38,6 @@ void variant_mainboard_final(void) cmd |= PCI_COMMAND_MASTER; pci_write_config16(dev, PCI_COMMAND, cmd); } - - /* Reduce SD-Card speed to DDR50 because of PCB constraints. */ - dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); - if (dev) { - uint32_t reg; - struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (!res) - return; - - write32(res2mmio(res, SD_CAP_BYP, 0), SD_CAP_BYP_EN); - reg = read32(res2mmio(res, SD_CAP_BYP_REG1, 0)); - /* Disable HS400 and SDR104, keep SDR50 and DDR50 modes. */ - reg &= ~0x20005800; - write32(res2mmio(res, SD_CAP_BYP_REG1, 0), reg); - } } static void wait_for_legacy_dev(void *unused) diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c index c7262cad9e..492dae6418 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c @@ -178,7 +178,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(PMC_SPI_CLK, DN_20K, DEEP), /* unused */ /* PMIC Signals unused signals related to an old PMIC interface. */ - PAD_CFG_GPI(PMIC_PWRGOOD, DN_20K, DEEP), /* PMIC_PWRGOOD */ + PAD_CFG_NF(PMIC_PWRGOOD, DN_20K, DEEP, NF1), /* PMIC_PWRGOOD */ PAD_CFG_GPI(PMIC_RESET_B, DN_20K, DEEP), /* PMIC_RESET_B */ PAD_CFG_GPI(GPIO_213, UP_20K, DEEP), /* PMIC_SDWN_B */ PAD_CFG_GPI(GPIO_214, DN_20K, DEEP), /* PMIC_BCUDISW2 */ @@ -318,16 +318,16 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_73, DN_20K, DEEP), /* pin open */ /* no TAP controller pins available on SMARC of APL4 */ - PAD_CFG_GPI(TCK, DN_20K, DEEP), /* pin open */ - PAD_CFG_GPI(TRST_B, DN_20K, DEEP), /* pin open */ - PAD_CFG_GPI(TMS, DN_20K, DEEP), /* pin open */ - PAD_CFG_GPI(TDI, DN_20K, DEEP), /* pin open */ + PAD_CFG_NF(TCK, DN_20K, DEEP, NF1), /* pin open */ + PAD_CFG_NF(TRST_B, DN_20K, DEEP, NF1), /* pin open */ + PAD_CFG_NF(TMS, DN_20K, DEEP, NF1), /* pin open */ + PAD_CFG_NF(TDI, DN_20K, DEEP, NF1), /* pin open */ - PAD_CFG_GPI(CX_PMODE, DN_20K, DEEP), /* pin open */ - PAD_CFG_GPI(CX_PREQ_B, DN_20K, DEEP), /* pin open */ - PAD_CFG_GPI(JTAGX, DN_20K, DEEP), /* pin open */ - PAD_CFG_GPI(CX_PRDY_B, DN_20K, DEEP), /* pin open */ - PAD_CFG_GPI(TDO, DN_20K, DEEP), /* pin open */ + PAD_CFG_NF(CX_PMODE, DN_20K, DEEP, NF1), /* pin open */ + PAD_CFG_NF(CX_PREQ_B, DN_20K, DEEP, NF1), /* pin open */ + PAD_CFG_NF(JTAGX, DN_20K, DEEP, NF1), /* pin open */ + PAD_CFG_NF(CX_PRDY_B, DN_20K, DEEP, NF1), /* pin open */ + PAD_CFG_NF(TDO, DN_20K, DEEP, NF1), /* pin open */ /* GPIO_[216:219] described into EDS Vol1. */ PAD_CFG_GPO(CNV_BRI_DT, 0, DEEP), /* Disable eDP to LVDS bridge */ @@ -335,7 +335,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(CNV_RGI_DT, DN_20K, DEEP), /* pin open */ /* Writing to following GPIO registers leads to 0xFFFF FFFF in CFG0/1 */ - PAD_CFG_GPI(CNV_RGI_RSP, DN_20K, DEEP), /* pin open */ + PAD_CFG_NF(CNV_RGI_RSP, DN_20K, DEEP, NF1), /* pin open */ /* Serial Voltage Identification */ PAD_CFG_NF(SVID0_ALERT_B, NONE, DEEP, NF1), /* SVID0_ALERT_B */ diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c index 1fb0c89b78..f6578cb866 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c @@ -135,7 +135,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(OSC_CLK_OUT_4, DN_20K, DEEP), /* PMU Signals */ - PAD_CFG_GPI(PMU_AC_PRESENT, NONE, DEEP), /* PMU_AC_PRESENT */ + PAD_CFG_GPI(PMU_AC_PRESENT, DN_20K, DEEP), /* PMU_AC_PRESENT */ PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1), /* PMU_BATLOW_N */ PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */ PAD_CFG_NF(PMU_PWRBTN_B, NONE, DEEP, NF1), /* PMU_PWRBTN_N */ @@ -193,7 +193,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(PMC_SPI_CLK, DN_20K, DEEP), /* PMIC Signals unused signals related to an old PMIC interface. */ - PAD_CFG_GPO(PMIC_PWRGOOD, 1, DEEP), /* PMIC_PWRGOOD */ + PAD_CFG_NF(PMIC_PWRGOOD, UP_20K, DEEP, NF1), /* PMIC_PWRGOOD */ PAD_CFG_GPI(PMIC_RESET_B, DN_20K, DEEP), /* PMIC_RESET_B */ PAD_CFG_TERM_GPO(GPIO_213, 0, DN_20K, DEEP), /* NFC_OUT_RESERVE */ PAD_CFG_TERM_GPO(GPIO_214, 0, DN_20K, DEEP), /* NFC_EN */ diff --git a/src/mainboard/sifive/hifive-unleashed/Makefile.inc b/src/mainboard/sifive/hifive-unleashed/Makefile.inc index 263297eb74..207898e973 100644 --- a/src/mainboard/sifive/hifive-unleashed/Makefile.inc +++ b/src/mainboard/sifive/hifive-unleashed/Makefile.inc @@ -20,7 +20,7 @@ ramstage-y += memlayout.ld ramstage-y += fixup_fdt.c -DTB=build/hifive-unleashed.dtb +DTB=$(obj)/hifive-unleashed.dtb DTS=src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts $(DTB): $(DTS) dtc -I dts -O dtb -o $(DTB) $(DTS) diff --git a/src/mainboard/up/squared/Kconfig b/src/mainboard/up/squared/Kconfig index b9f5b27a6d..5db76fd544 100644 --- a/src/mainboard/up/squared/Kconfig +++ b/src/mainboard/up/squared/Kconfig @@ -13,6 +13,8 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_16384 select ONBOARD_VGA_IS_PRIMARY select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_CRB_TPM + select HAVE_INTEL_PTT config VBOOT select VBOOT_NO_BOARD_SUPPORT diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb index 2a49db6a9e..66be75cc05 100644 --- a/src/mainboard/up/squared/devicetree.cb +++ b/src/mainboard/up/squared/devicetree.cb @@ -49,4 +49,7 @@ chip soc/intel/apollolake device pci 1f.0 on end # - LPC device pci 1f.1 on end # - SMBUS end + chip drivers/crb + device mmio 0xfed40000 on end + end end diff --git a/src/northbridge/amd/agesa/family15tn/iommu.c b/src/northbridge/amd/agesa/family15tn/iommu.c index d6dc7dac67..8bfd0b14fb 100644 --- a/src/northbridge/amd/agesa/family15tn/iommu.c +++ b/src/northbridge/amd/agesa/family15tn/iommu.c @@ -65,5 +65,5 @@ static struct device_operations iommu_ops = { static const struct pci_driver iommu_driver __pci_driver = { .ops = &iommu_ops, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_15H_NB_IOMMU, + .device = PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_IOMMU, }; diff --git a/src/northbridge/amd/amdht/AsPsNb.c b/src/northbridge/amd/amdht/AsPsNb.c index 2e6c1038e6..70dbacfbab 100644 --- a/src/northbridge/amd/amdht/AsPsNb.c +++ b/src/northbridge/amd/amdht/AsPsNb.c @@ -13,9 +13,6 @@ * GNU General Public License for more details. */ -#undef FILECODE -#define FILECODE 0xCCCC - #include "comlib.h" #include "AsPsDefs.h" #include "AsPsNb.h" diff --git a/src/northbridge/amd/amdht/comlib.c b/src/northbridge/amd/amdht/comlib.c index 3c2477c2ab..b36d4b4fe9 100644 --- a/src/northbridge/amd/amdht/comlib.c +++ b/src/northbridge/amd/amdht/comlib.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ -#undef FILECODE -#define FILECODE 0xCCCC #include "comlib.h" #include @@ -239,55 +237,3 @@ void CALLCONV AmdMSRWrite(uint32 Address, uint64 *Value) msr.hi = Value->hi; wrmsr(Address, msr); } - - -void ErrorStop(u32 value) -{ - printk(BIOS_DEBUG, "Error: %08x ", value); - -} - -/*;---------------------------------------------------------------------------- -; void __pascal ErrorStop(DWORD Value); -; -; This implementation provides a rotating display of the error code on the -; a port 80h POST display card. The rotation is used to make it easier to -; view the error on both a 16-bit as well as a 32-bit display card. -; -; For use with SimNow the unrotated error code is also written to port 84h -ErrorStop PROC FAR PASCAL PUBLIC Value:DWORD - pushad - mov eax, Value - mov bx, 0DEADh - out 84h, eax - -ErrorStopTop: - out 80h, eax - - mov cx, 4 ; Rotate the display by one nibble -@@: - bt bx, 15 - rcl eax, 1 - rcl bx, 1 - loop @B - - - push eax ; Delay a few hundred milliseconds - push ebx - mov ecx, 10h ; TSC - db 00Fh, 032h ; RDMSR - mov ebx, eax -@@: - db 00Fh, 032h ; RDMSR - sub eax, ebx - cmp eax, 500000000 - jb @B - pop ebx - pop eax - - jmp ErrorStopTop - - popad - ret -ErrorStop ENDP -*/ diff --git a/src/northbridge/amd/amdht/comlib.h b/src/northbridge/amd/amdht/comlib.h index d497fd28e4..dbc19f3cfa 100644 --- a/src/northbridge/amd/amdht/comlib.h +++ b/src/northbridge/amd/amdht/comlib.h @@ -16,25 +16,15 @@ #ifndef COMLIB_H #define COMLIB_H -#undef FILECODE -#define FILECODE 0xF001 - +#include #include #include #include "porting.h" -#ifdef AMD_DEBUG - #define ASSERT(x) ((x) ? 0 : ErrorStop(((uint32)FILECODE)*0x10000 + ((__LINE__)%10) + (((__LINE__/10)%10)*0x10) + (((__LINE__/100)%10)*0x100) +(((__LINE__/1000)%10)*0x1000))) -#else - #define ASSERT(x) -#endif - #ifdef AMD_DEBUG_ERROR_STOP - /* Macro to aid debugging, causes program to halt and display the line number of the halt in decimal */ - #define STOP_HERE ErrorStop(((uint32)FILECODE)*0x10000 + ((__LINE__)%10) + (((__LINE__/10)%10)*0x10) + (((__LINE__/100)%10)*0x100) +(((__LINE__/1000)%10)*0x1000)) + /* Macro to aid debugging, causes program to halt and display the line number of the halt */ + #define STOP_HERE ASSERT(0) #else - /* Macro to aid debugging, causes program to halt and display the line number of the halt in decimal */ - /* #define STOP_HERE STOP_HERE_OnlyForDebugUse */ #define STOP_HERE #endif diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index 8370b5893c..830e9888c9 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -21,8 +21,6 @@ *---------------------------------------------------------------------------- */ -#undef FILECODE -#define FILECODE 0xF002 #include "h3ncmn.h" #include "h3finit.h" #include "h3ffeat.h" diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index bad8993395..89ff46eae3 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -36,7 +36,6 @@ #endif /* Debugging Options */ -#define AMD_DEBUG 1 //#define AMD_DEBUG_ERROR_STOP 1 /*---------------------------------------------------------------------------- @@ -45,8 +44,6 @@ *---------------------------------------------------------------------------- */ -#undef FILECODE -#define FILECODE 0xFF01 #include "comlib.h" #include "h3gtopo.h" #include "h3finit.h" diff --git a/src/northbridge/amd/amdht/porting.h b/src/northbridge/amd/amdht/porting.h index a0f88786cf..9058d4d0e1 100644 --- a/src/northbridge/amd/amdht/porting.h +++ b/src/northbridge/amd/amdht/porting.h @@ -71,7 +71,6 @@ void CALLCONV AmdMemWrite(uint8 MemSize, uint64 *Address, uint32 *Value); void CALLCONV AmdPCIRead(SBDFO loc, uint32 *Value); void CALLCONV AmdPCIWrite(SBDFO loc, uint32 *Value); void CALLCONV AmdCPUIDRead(uint32 Address, uint32 Regs[4]); -void CALLCONV ErrorStop(uint32 Value); #define BYTESIZE 1 #define WORDSIZE 2 diff --git a/src/northbridge/intel/fsp_rangeley/Makefile.inc b/src/northbridge/intel/fsp_rangeley/Makefile.inc index f9bf0507dc..a2f80546d7 100644 --- a/src/northbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/northbridge/intel/fsp_rangeley/Makefile.inc @@ -18,12 +18,12 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY),y) subdirs-y += fsp ramstage-y += northbridge.c -ramstage-y += raminit.c +ramstage-y += memmap.c ramstage-y += acpi.c ramstage-y += port_access.c -romstage-y += raminit.c +romstage-y += memmap.c romstage-y += ../../../arch/x86/walkcbfs.S romstage-y += port_access.c diff --git a/src/northbridge/intel/fsp_rangeley/raminit.c b/src/northbridge/intel/fsp_rangeley/memmap.c similarity index 100% rename from src/northbridge/intel/fsp_rangeley/raminit.c rename to src/northbridge/intel/fsp_rangeley/memmap.c diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index c3d24820a5..576ae475d1 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -29,7 +29,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select POSTCAR_STAGE select POSTCAR_CONSOLE select PARALLEL_MP - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM config CBFS_SIZE hex diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index e74f475987..0ab1c94a27 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -25,22 +25,18 @@ romstage-y += pcie.c romstage-y += thermal.c romstage-y += igd.c romstage-y += pm.c -romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += iommu.c romstage-y += romstage.c ramstage-y += acpi.c -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += gma.c smm-y += ../../../cpu/x86/lapic/apic_timer.c -postcar-y += ram_calc.c - -romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/memmap.c similarity index 91% rename from src/northbridge/intel/gm45/ram_calc.c rename to src/northbridge/intel/gm45/memmap.c index c6140824f0..6795f7a61f 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include "gm45.h" @@ -123,6 +124,16 @@ void *cbmem_top(void) return (void *) top_of_ram; } +void stage_cache_external_region(void **base, size_t *size) +{ + /* The stage cache lives at the end of the TSEG region. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 3678cb803d..dbf91bf60d 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -19,7 +19,6 @@ config NORTHBRIDGE_INTEL_HASWELL select CACHE_MRC_SETTINGS select INTEL_DDI select INTEL_GMA_ACPI - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select POSTCAR_STAGE select POSTCAR_CONSOLE select C_ENVIRONMENT_BOOTBLOCK diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index ca1c04fa13..b9863367c9 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -17,14 +17,14 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_HASWELL),y) bootblock-y += bootblock.c -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += gma.c ramstage-y += acpi.c ramstage-y += minihd.c -romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += raminit.c romstage-y += early_init.c romstage-y += report_platform.c @@ -37,6 +37,6 @@ mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) mrc.bin-position := 0xfffa0000 mrc.bin-type := mrc -postcar-y += ram_calc.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/memmap.c similarity index 64% rename from src/northbridge/intel/haswell/ram_calc.c rename to src/northbridge/intel/haswell/memmap.c index bdf54d2435..3a63afcde6 100644 --- a/src/northbridge/intel/haswell/ram_calc.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -18,6 +18,7 @@ #include #include +#include #include "haswell.h" static uintptr_t smm_region_start(void) @@ -34,3 +35,16 @@ void *cbmem_top(void) { return (void *)smm_region_start(); } + +/* Region of SMM space is reserved for multipurpose use. It falls below + * the IED region and above the SMM handler. */ +#define RESERVED_SMM_OFFSET \ + (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE) + +void stage_cache_external_region(void **base, size_t *size) +{ + /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); +} diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 9beb23cc8e..2fdbe07c8d 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -155,6 +156,11 @@ void sdram_initialize(struct pei_data *pei_data) asm volatile ( "call *%%ecx\n\t" :"=a" (rv) : "c" (entry), "a" (pei_data)); + + /* mrc.bin reconfigures USB, so reinit it to have debug */ + if (CONFIG(USBDEBUG_IN_PRE_RAM)) + usbdebug_hw_init(true); + if (rv) { switch (rv) { case -1: diff --git a/src/northbridge/intel/i440bx/Makefile.inc b/src/northbridge/intel/i440bx/Makefile.inc index d41f65d755..2c503c63c1 100644 --- a/src/northbridge/intel/i440bx/Makefile.inc +++ b/src/northbridge/intel/i440bx/Makefile.inc @@ -17,12 +17,12 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BX),y) ramstage-y += northbridge.c -ramstage-y += ram_calc.c +ramstage-y += memmap.c romstage-y += raminit.c romstage-$(CONFIG_DEBUG_RAM_SETUP) += debug.c -romstage-y += ram_calc.c +romstage-y += memmap.c -postcar-y += ram_calc.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/memmap.c similarity index 100% rename from src/northbridge/intel/i440bx/ram_calc.c rename to src/northbridge/intel/i440bx/memmap.c diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index b151e8fb92..1a4d8875e9 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -30,7 +30,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select POSTCAR_STAGE select POSTCAR_CONSOLE select PARALLEL_MP - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index 47014bc291..47b4c5166b 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -15,12 +15,12 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I945),y) -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += gma.c ramstage-y += acpi.c -romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += raminit.c romstage-y += early_init.c romstage-y += errata.c @@ -29,10 +29,6 @@ romstage-y += rcven.c smm-y += udelay.c -postcar-y += ram_calc.c - -romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 54ff47cc64..d08b77d3e2 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -703,9 +703,8 @@ static void gma_func0_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); - int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; - if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { + int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; if (acpi_is_wakeup_s3()) { printk(BIOS_INFO, "Skipping native VGA initialization when resuming from ACPI S3.\n"); diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/memmap.c similarity index 89% rename from src/northbridge/intel/i945/ram_calc.c rename to src/northbridge/intel/i945/memmap.c index 525a5b9c0e..ac1499e0fc 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/memmap.c @@ -25,6 +25,8 @@ #include #include #include +#include +#include /* Decodes TSEG region size to bytes. */ u32 decode_tseg_size(const u8 esmramc) @@ -88,6 +90,16 @@ u32 decode_igd_memory_size(const u32 gms) return ggc2uma[gms] << 10; } +void stage_cache_external_region(void **base, size_t *size) +{ + /* The stage cache lives at the end of the TSEG region. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index c42c34cf39..dd9843300f 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1657,7 +1657,6 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo) printk(BIOS_DEBUG, "Voltage: %s ", (voltage == VOLTAGE_1_05)?"1.05V":"1.5V"); /* Gate graphics hardware for frequency change */ - reg8 = pci_read_config16(PCI_DEV(0, 2, 0), GCFC + 1); reg8 = (1<<3) | (1<<1); /* disable crclk, gate cdclk */ pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8); diff --git a/src/northbridge/intel/i945/stage_cache.c b/src/northbridge/intel/i945/stage_cache.c deleted file mode 100644 index 47f08c1397..0000000000 --- a/src/northbridge/intel/i945/stage_cache.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -void stage_cache_external_region(void **base, size_t *size) -{ - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)(northbridge_get_tseg_base() - + CONFIG_SMM_RESERVED_SIZE); -} diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index c0d46c9a0c..52374acee8 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -15,20 +15,20 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_NEHALEM),y) -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += smi.c ramstage-y += gma.c ramstage-y += acpi.c -romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += raminit.c romstage-y += early_init.c romstage-y += ../../../arch/x86/walkcbfs.S smm-y += finalize.c -postcar-y += ram_calc.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/memmap.c similarity index 83% rename from src/northbridge/intel/nehalem/ram_calc.c rename to src/northbridge/intel/nehalem/memmap.c index ba3761065b..ec036c9d7c 100644 --- a/src/northbridge/intel/nehalem/ram_calc.c +++ b/src/northbridge/intel/nehalem/memmap.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include "nehalem.h" @@ -38,11 +39,25 @@ u32 northbridge_get_tseg_base(void) return (u32)smm_region_start(); } +u32 northbridge_get_tseg_size(void) +{ + return CONFIG_SMM_TSEG_SIZE; +} + void *cbmem_top(void) { return (void *) smm_region_start(); } +void stage_cache_external_region(void **base, size_t *size) +{ + /* The stage cache lives at the end of TSEG region. + * The top of RAM is defined to be the TSEG base address. */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index b220c2d7a9..93024f69d8 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -122,9 +122,6 @@ typedef struct { #define IVB_STEP_K0 (BASE_REV_IVB + 5) #define IVB_STEP_D0 (BASE_REV_IVB + 6) -/* Intel Enhanced Debug region must be 4MB */ -#define IED_SIZE 0x400000 - /* Northbridge BARs */ #ifndef __ACPI__ #define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 485cb27f45..a058d3fa26 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -171,11 +171,6 @@ static void mc_read_resources(struct device *dev) add_fixed_resources(dev, 10); } -u32 northbridge_get_tseg_size(void) -{ - return CONFIG_SMM_TSEG_SIZE; -} - static void mc_set_resources(struct device *dev) { /* And call the normal set_resources */ diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index b4ff85cdd4..fadf0e0801 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -595,6 +595,8 @@ static void calculate_timings(struct raminfo *info) info-> spd[channel][slot][CAS_LATENCY_TIME]); } + if (cycletime > min_cycletime[0]) + die("RAM init: Decoded SPD DRAM freq is slower than the controller minimum!"); for (clock_speed_index = 0; clock_speed_index < 3; clock_speed_index++) { if (cycletime == min_cycletime[clock_speed_index]) break; diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 37959dd2e6..8acfaf8fec 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -31,7 +31,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select POSTCAR_STAGE select POSTCAR_CONSOLE select PARALLEL_MP - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select C_ENVIRONMENT_BOOTBLOCK config BOOTBLOCK_NORTHBRIDGE_INIT diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index 2d166138b6..81ee783304 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -19,19 +19,16 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_PINEVIEW),y) bootblock-y += ../../../cpu/x86/early_reset.S bootblock-y += bootblock.c -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += gma.c ramstage-y += acpi.c romstage-y += romstage.c -romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += raminit.c romstage-y += early_init.c -postcar-y += ram_calc.c -romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/memmap.c similarity index 91% rename from src/northbridge/intel/pineview/ram_calc.c rename to src/northbridge/intel/pineview/memmap.c index d1b43aa42d..2f3ff6e921 100644 --- a/src/northbridge/intel/pineview/ram_calc.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -26,6 +26,8 @@ #include #include #include +#include +#include u8 decode_pciebar(u32 *const base, u32 *const len) { @@ -138,6 +140,16 @@ void *cbmem_top(void) } +void stage_cache_external_region(void **base, size_t *size) +{ + /* The stage cache lives at the end of the TSEG region. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 1d24ea2217..5cece4147f 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -498,28 +498,12 @@ static void sdram_detect_ram_speed(struct sysinfo *s) lowcas = lsbp; while (cas == 0 && highcas >= lowcas) { FOR_EACH_POPULATED_DIMM(s->dimms, i) { - switch (freq) { - case MEM_CLOCK_800MHz: - if ((s->dimms[i].spd_data[9] > 0x25) || - (s->dimms[i].spd_data[10] > 0x40)) { - // CAS too fast, lower it - highcas--; - break; - } else { - cas = highcas; - } - break; - case MEM_CLOCK_667MHz: - default: - if ((s->dimms[i].spd_data[9] > 0x30) || - (s->dimms[i].spd_data[10] > 0x45)) { - // CAS too fast, lower it - highcas--; - break; - } else { - cas = highcas; - } - break; + if ((s->dimms[i].spd_data[9] > 0x30) || + (s->dimms[i].spd_data[10] > 0x45)) { + // CAS too fast, lower it + highcas--; + } else { + cas = highcas; } } } diff --git a/src/northbridge/intel/pineview/stage_cache.c b/src/northbridge/intel/pineview/stage_cache.c deleted file mode 100644 index 47f08c1397..0000000000 --- a/src/northbridge/intel/pineview/stage_cache.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -void stage_cache_external_region(void **base, size_t *size) -{ - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)(northbridge_get_tseg_base() - + CONFIG_SMM_RESERVED_SIZE); -} diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 8a0b67b2c9..77d1fdbb84 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -15,14 +15,14 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE),y) -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += pcie.c ramstage-y += gma.c ramstage-y += acpi.c -romstage-y += ram_calc.c +romstage-y += memmap.c ramstage-y += common.c romstage-y += common.c @@ -48,6 +48,6 @@ romstage-y += ../../../arch/x86/walkcbfs.S smm-y += finalize.c -postcar-y += ram_calc.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 09b8892141..4c4a509686 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -31,24 +31,24 @@ Device (MCHC) Offset (0x40), // EPBAR EPEN, 1, // Enable , 11, // - EPBR, 24, // EPBAR + EPBR, 27, // EPBAR Offset (0x48), // MCHBAR MHEN, 1, // Enable - , 13, // - MHBR, 22, // MCHBAR + , 14, // + MHBR, 24, // MCHBAR Offset (0x54), DVEN, 32, Offset (0x60), // PCIe BAR PXEN, 1, // Enable PXSZ, 2, // BAR size , 23, // - PXBR, 10, // PCIe BAR + PXBR, 13, // PCIe BAR Offset (0x68), // DMIBAR DMEN, 1, // Enable , 11, // - DMBR, 24, // DMIBAR + DMBR, 27, // DMIBAR Offset (0x70), // ME Base Address MEBA, 64, @@ -103,7 +103,7 @@ Device (MCHC) Name (CTCD, 1) /* CTDP Down Select */ Name (CTCU, 2) /* CTDP Up Select */ - OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000) + OperationRegion (MCHB, SystemMemory, \_SB.PCI0.MCHC.MHBR << 15, 0x8000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x5930), diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index dce9f67029..7fdfe4283c 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include "../sandybridge.h" #include "hostbridge.asl" #include "peg.asl" @@ -27,12 +26,13 @@ Device (PDRC) Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) - Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) - Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) + // Filled by _CRS + Memory32Fixed(ReadWrite, 0, 0x00008000, MCHB) + Memory32Fixed(ReadWrite, 0, 0x00001000, DMIB) + Memory32Fixed(ReadWrite, 0, 0x00001000, EGPB) + Memory32Fixed(ReadWrite, 0, 0x04000000, PCIX) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH - Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH + Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // TPM TIS Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH #if CONFIG(CHROMEOS_RAMOOPS) @@ -48,6 +48,21 @@ Device (PDRC) // Current Resource Settings Method (_CRS, 0, Serialized) { + CreateDwordField (PDRS, ^MCHB._BAS, MBR0) + MBR0 = \_SB.PCI0.MCHC.MHBR << 15 + + CreateDwordField (PDRS, ^DMIB._BAS, DBR0) + DBR0 = \_SB.PCI0.MCHC.DMBR << 12 + + CreateDwordField (PDRS, ^EGPB._BAS, EBR0) + EBR0 = \_SB.PCI0.MCHC.EPBR << 12 + + CreateDwordField (PDRS, ^PCIX._BAS, XBR0) + XBR0 = \_SB.PCI0.MCHC.PXBR << 26 + + CreateDwordField (PDRS, ^PCIX._LEN, XSZ0) + XSZ0 = 0x10000000 << \_SB.PCI0.MCHC.PXSZ + Return(PDRS) } } diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/memmap.c similarity index 80% rename from src/northbridge/intel/sandybridge/ram_calc.c rename to src/northbridge/intel/sandybridge/memmap.c index 343ae62711..7d5c173829 100644 --- a/src/northbridge/intel/sandybridge/ram_calc.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -20,17 +20,12 @@ #include #include #include +#include #include #include +#include #include "sandybridge.h" -#if (CONFIG_SMM_TSEG_SIZE < 0x800000) -# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" -#endif -#if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0) -# error "CONFIG_SMM_TSEG_SIZE is not a power of 2" -#endif - static uintptr_t smm_region_start(void) { /* Base of TSEG is top of usable DRAM */ @@ -43,6 +38,25 @@ void *cbmem_top(void) return (void *) smm_region_start(); } +u32 northbridge_get_tseg_base(void) +{ + return ALIGN_DOWN(smm_region_start(), 1*MiB); +} + +u32 northbridge_get_tseg_size(void) +{ + return CONFIG_SMM_TSEG_SIZE; +} + +void stage_cache_external_region(void **base, size_t *size) +{ + /* The stage cache lives at the end of TSEG region. + * The top of RAM is defined to be the TSEG base address. */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + northbridge_get_tseg_size() + - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE); +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 5aa06c8e4f..233384cd15 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -444,28 +444,6 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static u32 northbridge_get_base_reg(struct device *dev, int reg) -{ - u32 value; - - value = pci_read_config32(dev, reg); - /* Base registers are at 1MiB granularity. */ - value &= ~((1 << 20) - 1); - return value; -} - -u32 northbridge_get_tseg_base(void) -{ - struct device *dev = pcidev_on_root(0, 0); - - return northbridge_get_base_reg(dev, TSEG); -} - -u32 northbridge_get_tseg_size(void) -{ - return CONFIG_SMM_TSEG_SIZE; -} - void northbridge_write_smram(u8 smram) { pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram); diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 88b7b56864..b488f2c249 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -34,10 +34,6 @@ #define IVB_STEP_K0 (BASE_REV_IVB + 5) #define IVB_STEP_D0 (BASE_REV_IVB + 6) -/* Intel Enhanced Debug region must be 4MB */ - -#define IED_SIZE CONFIG_IED_REGION_SIZE - /* Northbridge BARs */ #ifndef __ACPI__ #define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index ce43936c37..a819f57af2 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -29,7 +29,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select POSTCAR_STAGE select POSTCAR_CONSOLE select PARALLEL_MP - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM config CBFS_SIZE hex diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index cc0a97d052..b7fd2fe7ae 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -19,19 +19,16 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_X4X),y) romstage-y += early_init.c romstage-y += raminit.c romstage-y += raminit_ddr23.c -romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += rcven.c romstage-y += raminit_tables.c romstage-y += dq_dqs.c ramstage-y += acpi.c -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += gma.c ramstage-y += northbridge.c -postcar-y += ram_calc.c -romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/memmap.c similarity index 91% rename from src/northbridge/intel/x4x/ram_calc.c rename to src/northbridge/intel/x4x/memmap.c index be9c10f001..dda838760d 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -29,6 +29,7 @@ #include #include #include +#include /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ u32 decode_igd_memory_size(const u32 gms) @@ -134,6 +135,16 @@ void *cbmem_top(void) return (void *) top_of_ram; } +void stage_cache_external_region(void **base, size_t *size) +{ + /* The stage cache lives at the end of the TSEG region. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 32618e8c88..1e40b9c511 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -41,8 +41,8 @@ u32 ddr_to_mhz(u32 speed) { static const u16 mhz[] = { 0, 0, 667, 800, 1067, 1333 }; - if (speed >= ARRAY_SIZE(mhz)) - return 0; + if (speed <= 1 || speed >= ARRAY_SIZE(mhz)) + die("RAM init: invalid memory speed %u\n", speed); return mhz[speed]; } diff --git a/src/northbridge/intel/x4x/stage_cache.c b/src/northbridge/intel/x4x/stage_cache.c deleted file mode 100644 index 47f08c1397..0000000000 --- a/src/northbridge/intel/x4x/stage_cache.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -void stage_cache_external_region(void **base, size_t *size) -{ - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)(northbridge_get_tseg_base() - + CONFIG_SMM_RESERVED_SIZE); -} diff --git a/src/northbridge/via/vx900/memmap.c b/src/northbridge/via/vx900/memmap.c index 0c3b7bfc76..d11dc65fd6 100644 --- a/src/northbridge/via/vx900/memmap.c +++ b/src/northbridge/via/vx900/memmap.c @@ -21,6 +21,7 @@ #include #include #include +#include #include "vx900.h" @@ -78,12 +79,16 @@ void vx900_set_chrome9hd_fb_size(u32 size_mb) size_mb = max_size_mb; } - /* Now round the framebuffer size to the closest power of 2 */ - u8 fb_pow = 0; - while (size_mb >> fb_pow) - fb_pow++; - fb_pow--; - size_mb = (1 << fb_pow); + /* Now round down the framebuffer size to the closest power of 2 */ + if (size_mb == 0) + die("Framebuffer size is 0\n"); + + int fb_pow = log2(size_mb); + + size_mb = 1U << fb_pow; + + if (size_mb < CHROME_9_HD_MIN_FB_SIZE || size_mb > CHROME_9_HD_MAX_FB_SIZE) + die("Framebuffer size %u is out of range\n", size_mb); pci_update_config8(MCU, 0xa1, ~(7 << 4), (fb_pow - 2) << 4); } diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index e6414d385f..3af6d69e2b 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -28,7 +28,7 @@ config TPM2 default y if MAINBOARD_HAS_TPM2 || USER_TPM2 depends on MAINBOARD_HAS_I2C_TPM_GENERIC || MAINBOARD_HAS_LPC_TPM \ || MAINBOARD_HAS_I2C_TPM_ATMEL || MAINBOARD_HAS_I2C_TPM_CR50 \ - || MAINBOARD_HAS_SPI_TPM_CR50 + || MAINBOARD_HAS_SPI_TPM_CR50 || MAINBOARD_HAS_CRB_TPM config MAINBOARD_HAS_TPM1 bool @@ -58,7 +58,7 @@ config USER_TPM2 bool "2.0" depends on MAINBOARD_HAS_I2C_TPM_GENERIC || MAINBOARD_HAS_LPC_TPM \ || MAINBOARD_HAS_I2C_TPM_ATMEL || MAINBOARD_HAS_I2C_TPM_CR50 \ - || MAINBOARD_HAS_SPI_TPM_CR50 + || MAINBOARD_HAS_SPI_TPM_CR50 || MAINBOARD_HAS_CRB_TPM help Enable this option to enable TPM 2.0 support in coreboot. diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index 6ab906710e..4019962a22 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -22,6 +22,7 @@ #include #include #include +#include static struct tcpa_table *tcpa_cbmem_init(void) { diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index 548a39a774..30e2a7b4b8 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -1,4 +1,5 @@ /* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2018-2019 Eltan B.V. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -65,6 +66,13 @@ uint32_t tlcl_define_space(uint32_t space_index, size_t space_size, const TPMA_NV nv_attributes, const uint8_t *nv_policy, size_t nv_policy_size); +/* + * Issue TPM2_GetCapability command + */ +uint32_t tlcl_get_capability(TPM_CAP capability, uint32_t property, + uint32_t property_count, + TPMS_CAPABILITY_DATA *capability_data); + /* * Makes tpm_process_command available for on top implementations of * custom tpm standards like cr50 diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index c4b553840f..08a7caa1a9 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -1,5 +1,6 @@ /* * Copyright 2016 The Chromium OS Authors. All rights reserved. + * Copyright 2017-2019 Eltan B.V. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -366,3 +367,31 @@ uint32_t tlcl_disable_platform_hierarchy(void) return TPM_SUCCESS; } + +uint32_t tlcl_get_capability(TPM_CAP capability, uint32_t property, + uint32_t property_count, + TPMS_CAPABILITY_DATA *capability_data) +{ + struct tpm2_get_capability cmd; + struct tpm2_response *response; + + cmd.capability = capability; + cmd.property = property; + cmd.propertyCount = property_count; + + if (property_count > 1) { + printk(BIOS_ERR, "%s: property_count more than one not " + "supported yet\n", __func__); + return TPM_E_IOERROR; + } + + response = tpm_process_command(TPM2_GetCapability, &cmd); + + if (!response) { + printk(BIOS_ERR, "%s: Command Failed\n", __func__); + return TPM_E_IOERROR; + } + + memcpy(capability_data, &response->gc.cd, sizeof(TPMS_CAPABILITY_DATA)); + return TPM_SUCCESS; +} diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 21da73a885..345aec5124 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -1,5 +1,6 @@ /* * Copyright 2016 The Chromium OS Authors. All rights reserved. + * Copyright (c) 2018 Eltan B.V. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,6 +13,7 @@ #include "tss_marshaling.h" #include +#include static uint16_t tpm_tag CAR_GLOBAL; /* Depends on the command type. */ @@ -421,6 +423,22 @@ static int unmarshal_get_capability(struct ibuf *ib, rc |= ibuf_read_be32(ib, &pp->value); } break; + case TPM_CAP_PCRS: + if (ibuf_read_be32(ib, &gcr->cd.data.assignedPCR.count)) + return -1; + if (gcr->cd.data.assignedPCR.count > + ARRAY_SIZE(gcr->cd.data.assignedPCR.pcrSelections)) { + printk(BIOS_INFO, "%s:%s:%d - %d - too many properties\n", + __FILE__, __func__, __LINE__, + gcr->cd.data.assignedPCR.count); + return -1; + } + for (i = 0; i < gcr->cd.data.assignedPCR.count; i++) { + TPMS_PCR_SELECTION *pp = + &gcr->cd.data.assignedPCR.pcrSelections[i]; + rc |= ibuf_read(ib, pp, sizeof(TPMS_PCR_SELECTION)); + } + break; default: printk(BIOS_ERR, "%s:%d - unable to unmarshal capability response", diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index 991cbcf502..7332739582 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -22,6 +22,8 @@ #define TPM2_RC_SUCCESS 0 #define TPM2_RC_NV_DEFINED 0x14c +#define HASH_COUNT 2 /* SHA-1 and SHA-256 are supported */ + /* Basic TPM2 types. */ typedef uint16_t TPM_SU; typedef uint16_t TPM_ALG_ID; @@ -144,7 +146,9 @@ struct tpm2_shutdown { }; /* Various TPM capability types to use when querying the device. */ +/* Table 21 - TPM_CAP Constants */ typedef uint32_t TPM_CAP; +#define TPM_CAP_PCRS ((TPM_CAP)0x00000005) #define TPM_CAP_TPM_PROPERTIES ((TPM_CAP)0x00000006) typedef TPM_HANDLE TPMI_RH_NV_AUTH; @@ -224,9 +228,29 @@ typedef struct { sizeof(TPMI_YES_NO) - sizeof(TPM_CAP) - sizeof(uint32_t)) #define MAX_TPM_PROPERTIES (MAX_CAP_DATA/sizeof(TPMS_TAGGED_PROPERTY)) +#define IMPLEMENTATION_PCR 24 +#define PLATFORM_PCR 24 + +#define PCR_SELECT_MIN (ALIGN_UP(PLATFORM_PCR, 8)/8) +#define PCR_SELECT_MAX (ALIGN_UP(IMPLEMENTATION_PCR, 8)/8) + /* Somewhat arbitrary, leave enough room for command wrappers. */ #define MAX_NV_BUFFER_SIZE (TPM_BUFFER_SIZE - sizeof(struct tpm_header) - 50) +/* Table 81 - TPMS_PCR_SELECTION Structure */ +typedef struct { + TPMI_ALG_HASH hash; + uint8_t sizeofSelect; + uint8_t pcrSelect[PCR_SELECT_MAX]; +} __packed TPMS_PCR_SELECTION; + +/* Table 98 - TPML_PCR_SELECTION Structure */ +typedef struct { + uint32_t count; + TPMS_PCR_SELECTION pcrSelections[HASH_COUNT]; +} __packed TPML_PCR_SELECTION; + +/* Table 100 - TPML_TAGGED_TPM_PROPERTY Structure */ typedef struct { uint32_t count; TPMS_TAGGED_PROPERTY tpmProperty[MAX_TPM_PROPERTIES]; @@ -234,6 +258,7 @@ typedef struct { typedef union { TPML_TAGGED_TPM_PROPERTY tpmProperties; + TPML_PCR_SELECTION assignedPCR; } TPMU_CAPABILITIES; typedef struct { diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index fa9893520a..c5146c61e7 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -26,10 +26,13 @@ config VBOOT if VBOOT +comment "Anti-Rollback Protection disabled because mocking secdata is enabled." + depends on VBOOT_MOCK_SECDATA + config VBOOT_MEASURED_BOOT bool "Enable Measured Boot" default n - depends on !VBOOT_MOCK_SECDATA + depends on TPM1 || TPM2 depends on !VBOOT_RETURN_FROM_VERSTAGE help Enables measured boot mode in vboot (experimental) @@ -154,21 +157,10 @@ config VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT reboots caused after vboot verification is run. e.g. reboots caused by FSP components on Intel platforms. -config VBOOT_MAY_SKIP_DISPLAY_INIT - bool "Skip display initialization in normal mode" - default y if CHROMEOS - default n - help - Set this option to indicate that coreboot should skip display - initialization on a normal (non-recovery, non-developer) boot. - This is useful for platforms that do not support firmware - user-interface in normal mode. - config VBOOT_MUST_REQUEST_DISPLAY bool default y if VGA_ROM_RUN default n - depends on VBOOT_MAY_SKIP_DISPLAY_INIT help Set this option to indicate to vboot that this platform will skip its display initialization on a normal (non-recovery, non-developer) boot. diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 6d195292e2..d554f103d6 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -88,6 +88,11 @@ else verstage-y += secdata_tpm.c romstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += secdata_tpm.c endif + +ifneq ($(CONFIG_TPM1)$(CONFIG_TPM2),) +verstage-y += tpm_common.c +endif + romstage-y += vboot_logic.c romstage-y += common.c diff --git a/src/security/vboot/antirollback.h b/src/security/vboot/antirollback.h index 62d2e20f03..5af923600d 100644 --- a/src/security/vboot/antirollback.h +++ b/src/security/vboot/antirollback.h @@ -83,11 +83,4 @@ uint32_t antirollback_write_space_rec_hash(const uint8_t *data, uint32_t size); /* Lock down recovery hash space in TPM. */ uint32_t antirollback_lock_space_rec_hash(void); -/* Start of the root of trust */ -uint32_t vboot_setup_tpm(struct vb2_context *ctx); - -/* vboot_extend_pcr function for vb2 context */ -uint32_t vboot_extend_pcr(struct vb2_context *ctx, int pcr, - enum vb2_pcr_digest which_digest); - #endif /* ANTIROLLBACK_H_ */ diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 4d4dc0ddfd..4625bcdff2 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -43,7 +43,7 @@ void vboot_save_recovery_reason_vbnv(void) set_recovery_mode_into_vbnv(reason); } -static void vb2_clear_recovery_reason_vbnv(void *unused) +static void vboot_clear_recovery_reason_vbnv(void *unused) { if (!CONFIG(VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT)) return; @@ -62,7 +62,7 @@ static void vb2_clear_recovery_reason_vbnv(void *unused) * only in FSP stages which run before BS_DEV_INIT. */ BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, - vb2_clear_recovery_reason_vbnv, NULL); + vboot_clear_recovery_reason_vbnv, NULL); /* * Returns 1 if vboot is being used and currently in a stage which might have diff --git a/src/security/vboot/secdata_mock.c b/src/security/vboot/secdata_mock.c index 3075d335f6..43206df6b9 100644 --- a/src/security/vboot/secdata_mock.c +++ b/src/security/vboot/secdata_mock.c @@ -43,12 +43,6 @@ int vb2ex_tpm_clear_owner(struct vb2_context *ctx) return VB2_SUCCESS; } -uint32_t vboot_extend_pcr(struct vb2_context *ctx, int pcr, - enum vb2_pcr_digest which_digest) -{ - return VB2_SUCCESS; -} - uint32_t antirollback_read_space_firmware(struct vb2_context *ctx) { vb2api_secdata_create(ctx); @@ -60,7 +54,7 @@ uint32_t antirollback_write_space_firmware(struct vb2_context *ctx) return VB2_SUCCESS; } -uint32_t antirollback_lock_space_firmware() +uint32_t antirollback_lock_space_firmware(void) { return VB2_SUCCESS; } diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 39cd6141fd..09c7e72b9b 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -33,6 +33,7 @@ */ #include +#include #include #include #include @@ -65,31 +66,6 @@ static uint32_t safe_write(uint32_t index, const void *data, uint32_t length); -uint32_t vboot_extend_pcr(struct vb2_context *ctx, int pcr, - enum vb2_pcr_digest which_digest) -{ - uint8_t buffer[VB2_PCR_DIGEST_RECOMMENDED_SIZE]; - uint32_t size = sizeof(buffer); - int rv; - - rv = vb2api_get_pcr_digest(ctx, which_digest, buffer, &size); - if (rv != VB2_SUCCESS) - return rv; - if (size < TPM_PCR_MINIMUM_DIGEST_SIZE) - return VB2_ERROR_UNKNOWN; - - switch (which_digest) { - case BOOT_MODE_PCR: - return tpm_extend_pcr(pcr, VB2_HASH_SHA1, buffer, size, - TPM_PCR_GBB_FLAGS_NAME); - case HWID_DIGEST_PCR: - return tpm_extend_pcr(pcr, VB2_HASH_SHA256, buffer, - size, TPM_PCR_GBB_HWID_NAME); - default: - return VB2_ERROR_UNKNOWN; - } -} - static uint32_t read_space_firmware(struct vb2_context *ctx) { int attempts = 3; @@ -443,25 +419,10 @@ static uint32_t factory_initialize_tpm(struct vb2_context *ctx) return TPM_SUCCESS; } -uint32_t vboot_setup_tpm(struct vb2_context *ctx) -{ - uint32_t result; - - result = tpm_setup(ctx->flags & VB2_CONTEXT_S3_RESUME); - if (result == TPM_E_MUST_REBOOT) - ctx->flags |= VB2_CONTEXT_SECDATA_WANTS_REBOOT; - - return result; -} - uint32_t antirollback_read_space_firmware(struct vb2_context *ctx) { uint32_t rv; - rv = vboot_setup_tpm(ctx); - if (rv) - return rv; - /* Read the firmware space. */ rv = read_space_firmware(ctx); if (rv == TPM_E_BADINDEX) { diff --git a/src/security/vboot/tpm_common.c b/src/security/vboot/tpm_common.c new file mode 100644 index 0000000000..1a07ef6def --- /dev/null +++ b/src/security/vboot/tpm_common.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include +#include +#include + +#define TPM_PCR_BOOT_MODE "VBOOT: boot mode" +#define TPM_PCR_GBB_HWID_NAME "VBOOT: GBB HWID" + +uint32_t vboot_setup_tpm(struct vb2_context *ctx) +{ + uint32_t result; + + result = tpm_setup(ctx->flags & VB2_CONTEXT_S3_RESUME); + if (result == TPM_E_MUST_REBOOT) + ctx->flags |= VB2_CONTEXT_SECDATA_WANTS_REBOOT; + + return result; +} + +uint32_t vboot_extend_pcr(struct vb2_context *ctx, int pcr, + enum vb2_pcr_digest which_digest) +{ + uint8_t buffer[VB2_PCR_DIGEST_RECOMMENDED_SIZE]; + uint32_t size = sizeof(buffer); + int rv; + + rv = vb2api_get_pcr_digest(ctx, which_digest, buffer, &size); + if (rv != VB2_SUCCESS) + return rv; + if (size < TPM_PCR_MINIMUM_DIGEST_SIZE) + return VB2_ERROR_UNKNOWN; + + switch (which_digest) { + /* SHA1 of (devmode|recmode|keyblock) bits */ + case BOOT_MODE_PCR: + return tpm_extend_pcr(pcr, VB2_HASH_SHA1, buffer, size, + TPM_PCR_BOOT_MODE); + /* SHA256 of HWID */ + case HWID_DIGEST_PCR: + return tpm_extend_pcr(pcr, VB2_HASH_SHA256, buffer, + size, TPM_PCR_GBB_HWID_NAME); + default: + return VB2_ERROR_UNKNOWN; + } +} diff --git a/src/security/vboot/tpm_common.h b/src/security/vboot/tpm_common.h new file mode 100644 index 0000000000..6bb32bbf1d --- /dev/null +++ b/src/security/vboot/tpm_common.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#if CONFIG(TPM1) || CONFIG(TPM2) + +/* Start of the root of trust */ +uint32_t vboot_setup_tpm(struct vb2_context *ctx); + +/* vboot_extend_pcr function for vb2 context */ +uint32_t vboot_extend_pcr(struct vb2_context *ctx, int pcr, + enum vb2_pcr_digest which_digest); + +#else + +#define vboot_setup_tpm(ctx) 0 + +#define vboot_extend_pcr(ctx, pcr, which_digest) 0 + +#endif diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index 8456dcfc22..cbd7a2ee23 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -51,30 +51,6 @@ int vboot_can_enable_udc(void) return 0; } -/* ========================== VBOOT HANDOFF APIs =========================== */ -int vboot_get_handoff_info(void **addr, uint32_t *size) -{ - /* - * vboot_handoff is present only after cbmem comes online. If we are in - * pre-ram stage, then bail out early. - */ - if (ENV_BOOTBLOCK || - (ENV_VERSTAGE && CONFIG(VBOOT_STARTS_IN_BOOTBLOCK))) - return -1; - - struct vboot_handoff *vboot_handoff; - vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - - if (vboot_handoff == NULL) - return -1; - - *addr = vboot_handoff; - - if (size) - *size = sizeof(*vboot_handoff); - return 0; -} - /* ============================ VBOOT REBOOT ============================== */ void __weak vboot_platform_prepare_reboot(void) { diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index 241dc90e95..8aadf9e420 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -32,27 +32,6 @@ int vboot_named_region_device_rw(const char *name, struct region_device *rdev); */ int vboot_check_recovery_request(void); -/* ========================== VBOOT HANDOFF APIs =========================== */ -/* - * The vboot_handoff structure contains the data to be consumed by downstream - * firmware after firmware selection has been completed. Namely it provides - * vboot shared data as well as the flags from VbInit. - */ -struct vboot_handoff { - uint32_t reserved0; /* originally from VbInitParams */ - uint32_t out_flags; - uint32_t selected_firmware; - char shared_data[VB_SHARED_DATA_MIN_SIZE]; -} __packed; - -/* - * vboot_get_handoff_info returns pointer to the vboot_handoff structure if - * available. vboot_handoff is available only after CBMEM comes online. If size - * is not NULL, size of the vboot_handoff structure is returned in it. - * Returns 0 on success and -1 on error. - */ -int vboot_get_handoff_info(void **addr, uint32_t *size); - /* ============================ VBOOT REBOOT ============================== */ /* * vboot_reboot handles the reboot requests made by vboot_reference library. It diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index af4a3fd880..3aac48d174 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -41,7 +41,6 @@ static void vboot_prepare(void) /* Note: this path is not used for VBOOT_RETURN_FROM_VERSTAGE */ verstage_main(); car_set_var(vboot_executed, 1); - vboot_save_recovery_reason_vbnv(); } else if (verstage_should_load()) { struct cbfsf file; struct prog verstage = diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 62e033a0de..7f00df5796 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "antirollback.h" @@ -334,7 +335,8 @@ void verstage_main(void) * check the return value here because vb2api_fw_phase1 will catch * invalid secdata and tell us what to do (=reboot). */ timestamp_add_now(TS_START_TPMINIT); - antirollback_read_space_firmware(&ctx); + if (vboot_setup_tpm(&ctx) == TPM_SUCCESS) + antirollback_read_space_firmware(&ctx); timestamp_add_now(TS_END_TPMINIT); /* Enable measured boot mode */ @@ -474,6 +476,9 @@ void verstage_main(void) if (ENV_ROMSTAGE && CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) vboot_log_and_clear_recovery_mode_switch(0); + /* Save recovery reason in case of unexpected reboots on x86. */ + vboot_save_recovery_reason_vbnv(); + vboot_finalize_work_context(&ctx); timestamp_add_now(TS_END_VBOOT); } diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 7b33d7ad11..ab913b2df0 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -114,6 +114,7 @@ #define LPC_WIDEIO2_GENERIC_PORT 0x90 #define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_ALIGNMENT BIT(6) #define SPI_BASE_RESERVED (BIT(4) | BIT(5)) #define ROUTE_TPM_2_SPI BIT(3) #define SPI_ABORT_ENABLE BIT(2) diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c index 6734b55fde..299a98abe9 100644 --- a/src/soc/amd/common/block/pi/def_callouts.c +++ b/src/soc/amd/common/block/pi/def_callouts.c @@ -220,8 +220,8 @@ AGESA_STATUS agesa_RunFuncOnAp(uint32_t Func, uintptr_t Data, void *ConfigPtr) agesadata.Func = Func; agesadata.Data = Data; agesadata.ConfigPtr = ConfigPtr; - mp_run_on_aps(callout_ap_entry, NULL, MP_RUN_ON_ALL_CPUS, - 100 * USECS_PER_MSEC); + if (mp_run_on_aps(callout_ap_entry, NULL, MP_RUN_ON_ALL_CPUS, 100 * USECS_PER_MSEC)) + return AGESA_ERROR; return AGESA_SUCCESS; } @@ -234,8 +234,8 @@ AGESA_STATUS agesa_RunFcnOnAllAps(uint32_t Func, uintptr_t Data, agesadata.Func = Func; agesadata.Data = Data; agesadata.ConfigPtr = ConfigPtr; - mp_run_on_aps(callout_ap_entry, NULL, MP_RUN_ON_ALL_CPUS, - 100 * USECS_PER_MSEC); + if (mp_run_on_aps(callout_ap_entry, NULL, MP_RUN_ON_ALL_CPUS, 100 * USECS_PER_MSEC)) + return AGESA_ERROR; return AGESA_SUCCESS; } diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index d654e9494e..1c2ec8400f 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -52,7 +52,6 @@ config CPU_SPECIFIC_OPTIONS select C_ENVIRONMENT_BOOTBLOCK select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select PARALLEL_MP select PARALLEL_MP_AP_WORK select HAVE_SMI_HANDLER @@ -72,6 +71,10 @@ config UDELAY_LAPIC_FIXED_FSB int default 200 +config HAVE_BOOTBLOCK + bool + default n + # TODO: Sync these with definitions in PI vendorcode. # DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR. # DCACHE_RAM_SIZE must equal BSP_STACK_SIZE. @@ -293,10 +296,6 @@ comment "AMD Firmware Directory Table set to location for 8MB ROM" comment "AMD Firmware Directory Table set to location for 16MB ROM" depends on AMD_FWM_POSITION_INDEX = 5 -config DIMM_SPD_SIZE - int - default 512 # DDR4 - config RO_REGION_ONLY string depends on CHROMEOS diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 93a8bbbbf2..7f371928c1 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -37,13 +37,6 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/pae subdirs-y += ../../../cpu/x86/smm -# TODO: Make coreboot modifications so bootblock can be removed. This soc -# also selects C_ENVIRONMENT_BOOTBLOCK to enforce certain codepaths -# in romstage. As a result, the bootblock build also needs a -# dummy cache_as_ram.S -bootblock-y += cache_as_ram.S -bootblock-y += bootblock/bootblock.c - romstage-y += i2c.c romstage-y += romstage.c romstage-y += gpio.c diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index bee2b4b49f..5c2ca432f1 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -62,21 +63,21 @@ static int get_cpu_count(void) static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; - void *handler_base; + uintptr_t handler_base; size_t handler_size; /* Initialize global tracking state. */ - smm_region_info(&smm_base, &smm_size); + smm_region(&smm_base, &smm_size); smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); - relo_attrs.smbase = (uint32_t)smm_base; + relo_attrs.smbase = smm_base; relo_attrs.tseg_base = relo_attrs.smbase; relo_attrs.tseg_mask = ALIGN_DOWN(~(smm_size - 1), 128 * KiB); relo_attrs.tseg_mask |= SMM_TSEG_WB; - *perm_smbase = (uintptr_t)handler_base; + *perm_smbase = handler_base; *perm_smsize = handler_size; *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); } diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h index 65705b93f3..57373c9a08 100644 --- a/src/soc/amd/picasso/include/soc/northbridge.h +++ b/src/soc/amd/picasso/include/soc/northbridge.h @@ -99,29 +99,8 @@ #define NB_CAPABILITIES2 0x84 #define CMP_CAP_MASK 0xff -enum { - /* SMM handler area. */ - SMM_SUBREGION_HANDLER, - /* SMM cache region. */ - SMM_SUBREGION_CACHE, - /* Chipset specific area. */ - SMM_SUBREGION_CHIPSET, - /* Total sub regions supported. */ - SMM_SUBREGION_NUM, -}; - void amd_initcpuio(void); -/* - * Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. - */ -void smm_region_info(void **start, size_t *size); -/* - * Fills in the start and size for the requested SMM subregion. Returns - * 0 on success, < 0 on failure. - */ -int smm_subregion(int sub, void **start, size_t *size); void domain_enable_resources(struct device *dev); void domain_set_resources(struct device *dev); void fam15_finalize(void *chip_info); diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 565ab3084d..6fc37f009a 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -225,9 +225,6 @@ #define SATA_CAPABILITIES_REG 0xfc #define SATA_CAPABILITY_SPM BIT(12) -/* SPI Controller (base address in D14F3xA0) */ -#define SPI_BASE_ALIGNMENT BIT(6) - #define SPI_CNTRL0 0x00 #define SPI_BUSY BIT(31) #define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) diff --git a/src/soc/amd/picasso/ramtop.c b/src/soc/amd/picasso/ramtop.c index 7c855bb1e1..672fdd8194 100644 --- a/src/soc/amd/picasso/ramtop.c +++ b/src/soc/amd/picasso/ramtop.c @@ -19,10 +19,10 @@ #include #include #include +#include #include #include #include -#include #include #include #include @@ -81,18 +81,9 @@ static size_t smm_region_size(void) return CONFIG_SMM_TSEG_SIZE; } -void stage_cache_external_region(void **base, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { - printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; - *size = 0; - } -} - -void smm_region_info(void **start, size_t *size) -{ - *start = (void *)smm_region_start(); + *start = smm_region_start(); *size = smm_region_size(); } @@ -118,17 +109,21 @@ static void clear_tvalid(void) wrmsr(SMM_MASK_MSR, mask); } -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { + static int once; uintptr_t sub_base; size_t sub_size; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - sub_base = smm_region_start(); - sub_size = smm_region_size(); - + smm_region(&sub_base, &sub_size); assert(sub_size > CONFIG_SMM_RESERVED_SIZE); + if (!once) { + clear_tvalid(); + once = 1; + } + switch (sub) { case SMM_SUBREGION_HANDLER: /* Handler starts at the base of TSEG. */ @@ -138,9 +133,10 @@ int smm_subregion(int sub, void **start, size_t *size) /* External cache is in the middle of TSEG. */ sub_base += sub_size - cache_size; sub_size = cache_size; - clear_tvalid(); break; default: + *start = 0; + *size = 0; return -1; } diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 950b41f5a3..dae64cc420 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -42,9 +43,8 @@ asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; uintptr_t top_of_ram; - void *smm_base; + uintptr_t smm_base; size_t smm_size; - uintptr_t tseg_base; int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); console_init(); @@ -90,9 +90,8 @@ asmlinkage void car_stage_entry(void) * when relocating the SMM handler as well as using the TSEG * region for other purposes. */ - smm_region_info(&smm_base, &smm_size); - tseg_base = (uintptr_t)smm_base; - postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); + smm_region(&smm_base, &smm_size); + postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); post_code(0x45); run_postcar_phase(&pcf); diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 78b89e3025..5f1d2f3ad5 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -23,7 +23,20 @@ config SOC_AMD_STONEYRIDGE_FT4 help AMD Stoney Ridge FT4 support -if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 +config SOC_AMD_MERLINFALCON + bool + help + AMD Merlin Falcon FP4 support + +config HAVE_MERLINFALCON_BINARIES + depends on SOC_AMD_MERLINFALCON + bool "Merlinfalcon binaries are present" + default n + help + This config option will be removed once the binaries are merged + to the blobs repo. See 33615. + +if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON config CPU_SPECIFIC_OPTIONS def_bool y @@ -60,7 +73,6 @@ config CPU_SPECIFIC_OPTIONS select C_ENVIRONMENT_BOOTBLOCK select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select PARALLEL_MP select PARALLEL_MP_AP_WORK select HAVE_SMI_HANDLER @@ -68,7 +80,6 @@ config CPU_SPECIFIC_OPTIONS select POSTCAR_CONSOLE select SSE2 select RTC - select SOC_AMD_PSP_SELECTABLE_SMU_FW config VBOOT select VBOOT_SEPARATE_VERSTAGE @@ -133,6 +144,7 @@ config MMCONF_BUS_NUMBER config VGA_BIOS_ID string + default "1002,9874" if SOC_AMD_MERLINFALCON default "1002,98e4" help The default VGA BIOS PCI vendor/device ID should be set to the @@ -140,6 +152,7 @@ config VGA_BIOS_ID config VGA_BIOS_FILE string + default "3rdparty/blobs/soc/amd/merlinfalcon/VBIOS.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES default "3rdparty/blobs/soc/amd/stoneyridge/VBIOS.bin" config S3_VGA_ROM_RUN @@ -188,6 +201,7 @@ config STONEYRIDGE_GEC_FWM_FILE config AMD_PUBKEY_FILE string "AMD public Key" + default "3rdparty/blobs/soc/amd/merlinfalcon/PSP/AmdPubKeyCZ.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES default "3rdparty/blobs/soc/amd/stoneyridge/PSP/AmdPubKeyST.bin" config STONEYRIDGE_SATA_MODE @@ -306,6 +320,17 @@ config USE_PSPSECUREOS If unsure, answer 'y' +config SOC_AMD_PSP_SELECTABLE_SMU_FW + bool + default n if SOC_AMD_MERLINFALCON + default y + help + Some ST implementations allow storing SMU firmware into cbfs and + calling the PSP to load the blobs at the proper time. + + Merlin Falcon does not support it. If you are using 00670F00 SOC, + ask your AMD representative if it supports it or not. + config SOC_AMD_SMU_FANLESS bool depends on SOC_AMD_PSP_SELECTABLE_SMU_FW @@ -384,4 +409,4 @@ config MAINBOARD_POWER_RESTORE return to S0. Otherwise the system will remain in S5 once power is restored. -endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 +endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index babd878524..150df3abd9 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -27,7 +27,7 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # #***************************************************************************** -ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +ifeq ($(CONFIG_SOC_AMD_MERLINFALCON)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) subdirs-y += ../../../cpu/amd/mtrr/ subdirs-y += ../../../cpu/x86/tsc @@ -142,7 +142,11 @@ STONEYRIDGE_FWM_POSITION=$(call int-add, \ ### 0 FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) +ifeq ($(CONFIG_HAVE_MERLINFALCON_BINARIES),y) +FIRMWARE_TYPE=CZ +else FIRMWARE_TYPE=ST +endif ###5 PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key @@ -191,6 +195,11 @@ SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).s SMUFIRMWARE2_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE)_FN.sbin endif +ifeq ("$(wildcard $(SMUFWM_FN_FILE))","") +SMUFWM_FN_FILE= +SMUFIRMWARE2_FN_FILE= +endif + add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) OPT_STONEYRIDGE_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE), --xhci) @@ -214,6 +223,9 @@ SUBPROG_FN_SMU_FW=1 OPT_SMUFWM_FN_FILE=$(call add_opt_prefix, $(SMUFWM_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware) OPT_SMUFIRMWARE2_FN_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware2) +ifeq ($(FIRMWARE_TYPE),ST) +OPT_COMBOCAPABLE=--combo-capable +endif $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE)) \ @@ -263,7 +275,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ $(OPT_SMUFIRMWARE2_FILE) \ $(OPT_SMUFIRMWARE2_FN_FILE) \ $(OPT_SMUSCS_FILE) \ - --combo-capable \ + $(OPT_COMBOCAPABLE)\ --flashsize $(CONFIG_ROM_SIZE) \ --location $(shell printf "0x%x" $(STONEYRIDGE_FWM_POSITION)) \ --output $@ @@ -313,4 +325,4 @@ endif endif # ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) -endif # ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +endif # ($(CONFIG_SOC_AMD_MERLINFALCON)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl index 414326ecf1..94638b043d 100644 --- a/src/soc/amd/stoneyridge/acpi/cpu.asl +++ b/src/soc/amd/stoneyridge/acpi/cpu.asl @@ -34,7 +34,15 @@ External (\_PR.P007, DeviceObj) /* Return a package containing enabled processor entries */ Method (PPKG) { - If (LGreaterEqual (\PCNT, 2)) { + If (LGreaterEqual (\PCNT, 4)) { + Return (Package () + { + \_PR.P000, + \_PR.P001, + \_PR.P002, + \_PR.P003 + }) + } ElseIf (LGreaterEqual (\PCNT, 2)) { Return (Package () { \_PR.P000, diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index d1a7d30199..00b675cbb0 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -23,9 +23,15 @@ #include #include +/* Merlin Falcon supports 2 channels, Prairie Falcon only 1 (channel B) */ #define MAX_NODES 1 +#if CONFIG(SOC_AMD_MERLINFALCON) && CONFIG(HAVE_MERLINFALCON_BINARIES) +#define MAX_DRAM_CH 2 +#define MAX_DIMMS_PER_CH 2 +#else #define MAX_DRAM_CH 1 #define MAX_DIMMS_PER_CH 2 +#endif #define STONEY_I2C_DEV_MAX 4 diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 1d9804d99c..4684aeaf8c 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -62,21 +63,21 @@ static int get_cpu_count(void) static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; - void *handler_base; + uintptr_t handler_base; size_t handler_size; /* Initialize global tracking state. */ - smm_region_info(&smm_base, &smm_size); + smm_region(&smm_base, &smm_size); smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); - relo_attrs.smbase = (uint32_t)smm_base; + relo_attrs.smbase = smm_base; relo_attrs.tseg_base = relo_attrs.smbase; relo_attrs.tseg_mask = ALIGN_DOWN(~(smm_size - 1), 128 * KiB); relo_attrs.tseg_mask |= SMM_TSEG_WB; - *perm_smbase = (uintptr_t)handler_base; + *perm_smbase = handler_base; *perm_smsize = handler_size; *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); } @@ -145,6 +146,7 @@ static struct device_operations cpu_dev_ops = { }; static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, 0x660f01 }, { X86_VENDOR_AMD, 0x670f00 }, { 0, 0 }, }; diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 60a6ea22bb..a0d7ce88dd 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -99,27 +99,6 @@ #define NB_CAPABILITIES2 0x84 #define CMP_CAP_MASK 0xff -enum { - /* SMM handler area. */ - SMM_SUBREGION_HANDLER, - /* SMM cache region. */ - SMM_SUBREGION_CACHE, - /* Chipset specific area. */ - SMM_SUBREGION_CHIPSET, - /* Total sub regions supported. */ - SMM_SUBREGION_NUM, -}; - -/* - * Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. - */ -void smm_region_info(void **start, size_t *size); -/* - * Fills in the start and size for the requested SMM subregion. Returns - * 0 on success, < 0 on failure. - */ -int smm_subregion(int sub, void **start, size_t *size); void domain_enable_resources(struct device *dev); void domain_set_resources(struct device *dev); void fam15_finalize(void *chip_info); diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index 02fed7ab1e..01a0b7cd8b 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -39,17 +39,24 @@ #define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC) #define SOC_IOMMU_DEV _SOC_DEV(IOMMU_DEV, IOMMU_FUNC) -/* Internal Graphics */ +/* + * Internal Graphics + * Device IDs subject to SKU/OPN variation + * GFX_DEVID for merlinfalcon PCI_DEVICE_ID_AMD_15H_MODEL_606F_GFX + * GFX_DEVID for stoneyridge PCI_DEVICE_ID_AMD_15H_MODEL_707F_GFX + */ #define GFX_DEV 0x1 #define GFX_FUNC 0 -#define GFX_DEVID 0x98e4 /* subject to SKU/OPN variation */ #define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) #define SOC_GFX_DEV _SOC_DEV(GFX_DEV, GFX_FUNC) -/* HD Audio 0 */ +/* HD Audio 0 + * Device IDs + * HDA0_DEVID PCI_DEVICE_ID_AMD_15H_MODEL_606F_HDA + * HDA0_DEVID PCI_DEVICE_ID_AMD_15H_MODEL_707F_HDA + */ #define HDA0_DEV 0x1 #define HDA0_FUNC 1 -#define HDA0_DEVID 0x15b3 #define HDA0_DEVFN PCI_DEVFN(HDA0_DEV, HDA0_FUNC) #define SOC_HDA0_DEV _SOC_DEV(HDA0_DEV, HDA0_FUNC) @@ -109,45 +116,63 @@ #define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC) #define SOC_HDA1_DEV _SOC_DEV(HDA1_DEV, HDA1_FUNC) -/* HT Configuration */ +/* HT Configuration + * Device IDs + * HT_DEVID for merlinfalcon PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT + * HT_DEVID for stoneyridge PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT + */ #define HT_DEV 0x18 #define HT_FUNC 0 -#define HT_DEVID 0x15b0 #define HT_DEVFN PCI_DEVFN(HT_DEV, HT_FUNC) #define SOC_HT_DEV _SOC_DEV(HT_DEV, HT_FUNC) -/* Address Maps */ +/* Address Maps + * Device IDs + * ADDR_DEVID for merlinfalcon 0x1571 + * ADDR_DEVID for stoneyridge 0x15b1 + */ #define ADDR_DEV 0x18 #define ADDR_FUNC 1 -#define ADDR_DEVID 0x15b1 #define ADDR_DEVFN PCI_DEVFN(ADDR_DEV, ADDR_FUNC) #define SOC_ADDR_DEV _SOC_DEV(ADDR_DEV, ADDR_FUNC) -/* DRAM Configuration */ +/* DRAM Configuration + * Device IDs + * DCT_DEVID for merlinfalcon 0x1572 + * DCT_DEVID for stoneyridge 0x15b2 + */ #define DCT_DEV 0x18 #define DCT_FUNC 2 -#define DCT_DEVID 0x15b2 #define DCT_DEVFN PCI_DEVFN(DCT_DEV, DCT_FUNC) #define SOC_DCT_DEV _SOC_DEV(DCT_DEV, DCT_FUNC) -/* Misc. Configuration */ +/* Misc. Configuration + * Device IDs + * MISC_DEVID for merlinfalcon 0x1573 + * MISC_DEVID for stoneyridge 0x15b3 + */ #define MISC_DEV 0x18 #define MISC_FUNC 3 -#define MISC_DEVID 0x15b3 #define MISC_DEVFN PCI_DEVFN(MISC_DEV, MISC_FUNC) #define SOC_MISC_DEV _SOC_DEV(MISC_DEV, MISC_FUNC) -/* PM Configuration */ +/* PM Configuration + * Device IDs + * PM_DEVID for merlinfalcon 0x1574 + * PM_DEVID for stoneyridge 0x15b4 + */ #define PM_DEV 0x18 #define PM_FUNC 4 -#define PM_DEVID 0x15b4 #define PM_DEVFN PCI_DEVFN(PM_DEV, PM_FUNC) #define SOC_PM_DEV _SOC_DEV(PM_DEV, PM_FUNC) -/* Northbridge Configuration */ +/* Northbridge Configuration + * Device IDs + * NB_DEVID for merlinfalcon 0x1575 + * NB_DEVID for stoneyridge 0x15b5 + */ #define NB_DEV 0x18 #define NB_FUNC 5 -#define NB_DEVID 0x15b5 #define NB_DEVFN PCI_DEVFN(NB_DEV, NB_FUNC) #define SOC_NB_DEV _SOC_DEV(NB_DEV, NB_FUNC) diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index ad4040759c..07c92a185c 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -254,9 +254,6 @@ #define SATA_CAPABILITIES_REG 0xfc #define SATA_CAPABILITY_SPM BIT(12) -/* SPI Controller (base address in D14F3xA0) */ -#define SPI_BASE_ALIGNMENT BIT(6) - #define SPI_CNTRL0 0x00 #define SPI_BUSY BIT(31) #define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 5985832c81..044a1b05ca 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -347,10 +347,15 @@ static struct device_operations northbridge_operations = { .ops_pci = 0, }; +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT, + PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT, + 0 }; + static const struct pci_driver family15_northbridge __pci_driver = { .ops = &northbridge_operations, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT, + .devices = pci_device_ids, }; /* @@ -464,9 +469,13 @@ void domain_set_resources(struct device *dev) u32 map_oprom_vendev(u32 vendev) { u32 new_vendev; - new_vendev = - ((vendev >= 0x100298e0) && (vendev <= 0x100298ef)) ? - 0x100298e0 : vendev; + + if ((vendev >= 0x100298e0) && (vendev <= 0x100298ef)) + new_vendev = 0x100298e0; + else if ((vendev >= 0x10029870) && (vendev <= 0x1002987f)) + new_vendev = 0x10029870; + else + new_vendev = vendev; if (vendev != new_vendev) printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index 7c855bb1e1..e2b0f7d6bc 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -19,10 +19,10 @@ #include #include #include +#include #include #include #include -#include #include #include #include @@ -81,18 +81,9 @@ static size_t smm_region_size(void) return CONFIG_SMM_TSEG_SIZE; } -void stage_cache_external_region(void **base, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { - printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; - *size = 0; - } -} - -void smm_region_info(void **start, size_t *size) -{ - *start = (void *)smm_region_start(); + *start = smm_region_start(); *size = smm_region_size(); } @@ -118,17 +109,21 @@ static void clear_tvalid(void) wrmsr(SMM_MASK_MSR, mask); } -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { + static int once; uintptr_t sub_base; size_t sub_size; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - sub_base = smm_region_start(); - sub_size = smm_region_size(); - + smm_region(&sub_base, &sub_size); assert(sub_size > CONFIG_SMM_RESERVED_SIZE); + if (!once) { + clear_tvalid(); + once = 1; + } + switch (sub) { case SMM_SUBREGION_HANDLER: /* Handler starts at the base of TSEG. */ @@ -138,14 +133,14 @@ int smm_subregion(int sub, void **start, size_t *size) /* External cache is in the middle of TSEG. */ sub_base += sub_size - cache_size; sub_size = cache_size; - clear_tvalid(); break; default: + *start = 0; + *size = 0; return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; - return 0; } diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 000d100fa3..42b08338d4 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -83,9 +84,8 @@ asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; uintptr_t top_of_ram; - void *smm_base; + uintptr_t smm_base; size_t smm_size; - uintptr_t tseg_base; msr_t base, mask; msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT; @@ -175,9 +175,8 @@ asmlinkage void car_stage_entry(void) * when relocating the SMM handler as well as using the TSEG * region for other purposes. */ - smm_region_info(&smm_base, &smm_size); - tseg_base = (uintptr_t)smm_base; - postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); + smm_region(&smm_base, &smm_size); + postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); post_code(0x45); run_postcar_phase(&pcf); diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index cf3d2446b4..ee74dbf997 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -40,7 +40,6 @@ config CPU_SPECIFIC_OPTIONS # Misc options select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COLLECT_TIMESTAMPS select COMMON_FADT select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS @@ -156,10 +155,6 @@ config DCACHE_BSP_STACK_SIZE The amount of anticipated stack usage in CAR by bootblock and other stages. -config CPU_ADDR_BITS - int - default 39 - config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 100 diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4fc16d5891..60b1a3c4f5 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -39,11 +39,13 @@ romstage-y += reset.c romstage-y += spi.c smm-y += mmap_boot.c +smm-y += pmc.c smm-y += pmutil.c smm-y += smihandler.c smm-y += spi.c smm-y += uart.c smm-y += elog.c +smm-y += xhci.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c @@ -67,6 +69,7 @@ ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += xdci.c ramstage-y += sd.c +ramstage-y += xhci.c postcar-y += memmap.c postcar-y += mmap_boot.c diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index cec706f5e0..f729f3139e 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -90,7 +90,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) void acpi_create_gnvs(struct global_nvs_t *gnvs) { struct soc_intel_apollolake_config *cfg; - struct device *dev = SA_DEV_ROOT; + cfg = config_of_path(SA_DEVFN_ROOT); /* Clear out GNVS. */ memset(gnvs, 0, sizeof(*gnvs)); @@ -110,12 +110,6 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs) /* CPU core count */ gnvs->pcnt = dev_count_cpu(); - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); - return; - } - cfg = dev->chip_info; - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = cfg->dptf_enable; @@ -158,7 +152,7 @@ int soc_madt_sci_irq_polarity(int sci) void soc_fill_fadt(acpi_fadt_t *fadt) { const struct soc_intel_apollolake_config *cfg; - struct device *dev = SA_DEV_ROOT; + cfg = config_of_path(SA_DEVFN_ROOT); fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR; @@ -174,13 +168,8 @@ void soc_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.addrl = ACPI_BASE_ADDRESS + PM1_TMR; - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); - return; - } - cfg = dev->chip_info; - if(cfg->lpss_s0ix_enable) + if (cfg->lpss_s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; } diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 1d5e6d95ba..361e6a417e 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -294,25 +294,19 @@ static void pcie_override_devicetree_after_silicon_init(void) /* Configure package power limits */ static void set_power_limits(void) { - static struct soc_intel_apollolake_config *cfg; - struct device *dev = SA_DEV_ROOT; + struct soc_intel_apollolake_config *cfg; msr_t rapl_msr_reg, limit; uint32_t power_unit; uint32_t tdp, min_power, max_power; uint32_t pl2_val; + cfg = config_of_path(SA_DEVFN_ROOT); + if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { printk(BIOS_INFO, "Skip the RAPL settings.\n"); return; } - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); - return; - } - - cfg = dev->chip_info; - /* Get units */ rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU_UNIT); power_unit = 1 << (rapl_msr_reg.lo & 0xf); @@ -367,16 +361,10 @@ static void set_power_limits(void) /* Overwrites the SCI IRQ if another IRQ number is given by device tree. */ static void set_sci_irq(void) { - static struct soc_intel_apollolake_config *cfg; - struct device *dev = SA_DEV_ROOT; + struct soc_intel_apollolake_config *cfg; uint32_t scis; - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); - return; - } - - cfg = dev->chip_info; + cfg = config_of_path(SA_DEVFN_ROOT); /* Change only if a device tree entry exists. */ if (cfg->sci_irq) { @@ -550,7 +538,7 @@ static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig) static void parse_devicetree(FSP_S_CONFIG *silconfig) { - struct device *dev = SA_DEV_ROOT; + struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); if (!dev) { printk(BIOS_ERR, "Could not find root device\n"); @@ -678,22 +666,17 @@ void __weak mainboard_devtree_update(struct device *dev) void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) { FSP_S_CONFIG *silconfig = &silupd->FspsConfig; - static struct soc_intel_apollolake_config *cfg; + struct soc_intel_apollolake_config *cfg; + struct device *dev; /* Load VBT before devicetree-specific config. */ silconfig->GraphicsConfigPtr = (uintptr_t)vbt_get(); - struct device *dev = SA_DEV_ROOT; - - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); - return; - } + dev = pcidev_path_on_root(SA_DEVFN_ROOT); + cfg = config_of(dev); mainboard_devtree_update(dev); - cfg = dev->chip_info; - /* Parse device tree and disable unused device*/ parse_devicetree(silconfig); diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index aad0f6b522..9b9b722bb3 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -29,10 +29,10 @@ #include #include #include +#include #include #include #include -#include #include #include #include @@ -205,24 +205,24 @@ void get_microcode_info(const void **microcode, int *parallel) static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; - void *handler_base; + uintptr_t handler_base; size_t handler_size; /* All range registers are aligned to 4KiB */ const uint32_t rmask = ~((1 << 12) - 1); /* Initialize global tracking state. */ - smm_region_info(&smm_base, &smm_size); + smm_region(&smm_base, &smm_size); smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); - relo_attrs.smbase = (uint32_t)smm_base; + relo_attrs.smbase = smm_base; relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; - *perm_smbase = (uintptr_t)handler_base; + *perm_smbase = handler_base; *perm_smsize = handler_size; *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); } @@ -295,14 +295,7 @@ void cpu_lock_sgx_memory(void) int soc_fill_sgx_param(struct sgx_param *sgx_param) { - struct device *dev = SA_DEV_ROOT; - assert(dev != NULL); - config_t *conf = dev->chip_info; - - if (!conf) { - printk(BIOS_ERR, "Failed to get chip_info for SGX param\n"); - return -1; - } + config_t *conf = config_of_path(SA_DEVFN_ROOT); sgx_param->enable = conf->sgx_enable; return 0; diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c index c138b346e1..02afb6c5cc 100644 --- a/src/soc/intel/apollolake/elog.c +++ b/src/soc/intel/apollolake/elog.c @@ -25,23 +25,6 @@ #include #include -#define XHCI_USB2_PORT_STATUS_REG 0x480 -#if CONFIG(SOC_INTEL_GLK) -#define XHCI_USB3_PORT_STATUS_REG 0x510 -#define XHCI_USB2_PORT_NUM 9 -#else -#define XHCI_USB3_PORT_STATUS_REG 0x500 -#define XHCI_USB2_PORT_NUM 8 -#endif -#define XHCI_USB3_PORT_NUM 7 - -static const struct xhci_usb_info usb_info = { - .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, - .num_usb2_ports = XHCI_USB2_PORT_NUM, - .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, - .num_usb3_ports = XHCI_USB3_PORT_NUM, -}; - static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { int i; @@ -74,7 +57,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) /* XHCI */ if (ps->gpe0_sts[GPE0_A] & XHCI_PME_STS) - pch_xhci_update_wake_event(&usb_info); + pch_xhci_update_wake_event(soc_get_xhci_usb_info()); /* SMBUS Wake */ if (ps->gpe0_sts[GPE0_A] & SMB_WAK_STS) diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index a334f63468..6544b7a019 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -17,35 +17,34 @@ #include -#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) #if !defined(__SIMPLE_DEVICE__) #include -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #else -#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) #endif /* System Agent Devices */ #define SA_DEV_SLOT_ROOT 0x00 -#define SA_DEVFN_ROOT _SA_DEVFN(ROOT) -#define SA_DEV_ROOT _SA_DEV(ROOT) +#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) +#if defined(__SIMPLE_DEVICE__) +#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) +#endif #define SA_DEV_SLOT_PUNIT 0x01 -#define SA_DEVFN_PUNIT _SA_DEVFN(PUNIT) -#define SA_DEV_PUNIT _SA_DEV(PUNIT) +#define SA_DEVFN_PUNIT PCI_DEVFN(SA_DEV_SLOT_PUNIT, 0) +#define SA_DEV_PUNIT PCI_DEV(0, SA_DEV_SLOT_PUNIT, 0) #define SA_DEV_SLOT_IGD 0x02 -#define SA_DEVFN_IGD _SA_DEVFN(IGD) -#define SA_DEV_IGD _SA_DEV(IGD) +#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) +#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) #define SA_DEV_SLOT_IPU 0x03 -#define SA_DEVFN_IPU _SA_DEVFN(IPU) -#define SA_DEV_IPU _SA_DEV(IPU) +#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) +#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) /* PCH Devices */ diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index d3538342b0..d0b0421561 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -172,6 +172,7 @@ #define SRS (1 << 20) #define MS4V (1 << 18) #define RPS (1 << 2) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) #define GEN_PMCON1_CLR1_BITS (COLD_BOOT_STS | COLD_RESET_STS | \ WARM_RESET_STS | GLOBAL_RESET_STS | \ SRS | MS4V) diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index ceed8f268f..2d59f7de22 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -91,12 +91,7 @@ void lpc_configure_pads(void) void lpc_soc_init(struct device *dev) { const struct soc_intel_apollolake_config *cfg; - - cfg = dev->chip_info; - if (!cfg) { - printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); - return; - } + cfg = config_of(dev); /* Set LPC Serial IRQ mode */ lpc_set_serirq_mode(cfg->serirq_mode); diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 3436364b64..17dfb3f545 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -18,8 +18,8 @@ #include #include #include +#include #include -#include #include #include #include @@ -28,20 +28,13 @@ void *cbmem_top(void) { - const struct device *dev; const config_t *config; void *tolum = (void *)sa_get_tseg_base(); if (!CONFIG(SOC_INTEL_GLK)) return tolum; - dev = pcidev_path_on_root(PCH_DEVFN_LPC); - assert(dev != NULL); - config = dev->chip_info; - - if (!config) - die_with_post_code(POST_HW_INIT_FAILURE, - "Failed to get chip_info\n"); + config = config_of_path(PCH_DEVFN_LPC); /* FSP allocates 2x PRMRR Size Memory for alignment */ if (config->sgx_enable) @@ -50,17 +43,19 @@ void *cbmem_top(void) return tolum; } -int smm_subregion(int sub, void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) +{ + *start = sa_get_tseg_base(); + *size = sa_get_tseg_size(); +} + +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; size_t sub_size; - void *smm_base; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - smm_region_info(&smm_base, &sub_size); - sub_base = (uintptr_t)smm_base; - - assert(sub_size > CONFIG_SMM_RESERVED_SIZE); + smm_region(&sub_base, &sub_size); switch (sub) { case SMM_SUBREGION_HANDLER: @@ -73,11 +68,12 @@ int smm_subregion(int sub, void **start, size_t *size) sub_size = cache_size; break; default: + *start = 0; + *size = 0; return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; - return 0; } diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c index 0400a9df85..286cd8a286 100644 --- a/src/soc/intel/apollolake/pmc.c +++ b/src/soc/intel/apollolake/pmc.c @@ -92,9 +92,22 @@ static void set_slp_s3_assertion_width(int width_usecs) write32((void *)gen_pmcon3, reg); } +void pmc_soc_set_afterg3_en(const bool on) +{ + void *const gen_pmcon1 = (void *)(soc_read_pmc_base() + GEN_PMCON1); + uint32_t reg32; + + reg32 = read32(gen_pmcon1); + if (on) + reg32 &= ~SLEEP_AFTER_POWER_FAIL; + else + reg32 |= SLEEP_AFTER_POWER_FAIL; + write32(gen_pmcon1, reg32); +} + void pmc_soc_init(struct device *dev) { - const struct soc_intel_apollolake_config *cfg = dev->chip_info; + const struct soc_intel_apollolake_config *cfg = config_of(dev); /* Set up GPE configuration */ pmc_gpe_init(); @@ -108,4 +121,6 @@ void pmc_soc_init(struct device *dev) /* Now that things have been logged clear out the PMC state. */ pmc_clear_prsts(); + + pmc_set_power_failure_state(true); } diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 1bf3202f27..84b61da6b1 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -148,13 +148,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_apollolake_config *config; - /* Look up the device in devicetree */ - DEVTREE_CONST struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); - return; - } - config = dev->chip_info; + config = config_of_path(SA_DEVFN_ROOT); /* Assign to out variable */ *dw0 = config->gpe0_dw1; diff --git a/src/soc/intel/apollolake/pnpconfig.c b/src/soc/intel/apollolake/pnpconfig.c index f9d493ed3e..0e9e93118a 100644 --- a/src/soc/intel/apollolake/pnpconfig.c +++ b/src/soc/intel/apollolake/pnpconfig.c @@ -37,8 +37,10 @@ static void pnp_settings(void *unused) int index; size_t arrsize; const struct pnpconfig *pnpconfigarr; - struct device *dev = SA_DEV_ROOT; - struct soc_intel_apollolake_config *config = dev->chip_info; + struct soc_intel_apollolake_config *config; + + config = config_of_path(SA_DEVFN_ROOT); + switch (config->pnp_settings) { case PNP_PERF: pnpconfigarr = perf; diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 72a566a763..3ce63704fb 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -27,10 +27,10 @@ #include #include #include +#include #include #include #include -#include #include #include #include @@ -100,17 +100,8 @@ static void soc_early_romstage_init(void) /* Thermal throttle activation offset */ static void configure_thermal_target(void) { - const struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); - if (!dev) { - printk(BIOS_ERR, "Could not find SOC devicetree config\n"); - return; - } - const config_t *conf = dev->chip_info; - if (!dev->chip_info) { - printk(BIOS_ERR, "Could not find chip info\n"); - return; - } msr_t msr; + const config_t *conf = config_of_path(SA_DEVFN_ROOT); if (!conf->tcc_offset) return; @@ -211,10 +202,9 @@ asmlinkage void car_stage_entry(void) uintptr_t top_of_ram; bool s3wake; struct chipset_power_state *ps = pmc_get_power_state(); - void *smm_base; + uintptr_t smm_base; size_t smm_size, var_size; const void *new_var_data; - uintptr_t tseg_base; timestamp_add_now(TS_START_ROMSTAGE); @@ -266,9 +256,8 @@ asmlinkage void car_stage_entry(void) * when relocating the SMM handler as well as using the TSEG * region for other purposes. */ - smm_region_info(&smm_base, &smm_size); - tseg_base = (uintptr_t)smm_base; - postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); + smm_region(&smm_base, &smm_size); + postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); run_postcar_phase(&pcf); } @@ -320,13 +309,9 @@ static void soc_memory_init_params(FSPM_UPD *mupd) { #if CONFIG(SOC_INTEL_GLK) /* Only for GLK */ - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); - assert(dev != NULL); - const config_t *config = dev->chip_info; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - if (!config) - die("Can not find SoC devicetree\n"); + const config_t *config = config_of_path(PCH_DEVFN_LPC); m_cfg->PrmrrSize = config->PrmrrSize; diff --git a/src/soc/intel/apollolake/sd.c b/src/soc/intel/apollolake/sd.c index 35db8040a0..e34d53ed21 100644 --- a/src/soc/intel/apollolake/sd.c +++ b/src/soc/intel/apollolake/sd.c @@ -18,7 +18,7 @@ int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, struct device *dev) { - config_t *config = dev->chip_info; + config_t *config = config_of(dev); if (!config->sdcard_cd_gpio) return -1; diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index 27be4e65f9..f8c4aafec2 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -74,7 +74,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); -struct device *soc_uart_console_to_device(int uart_console) +DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) { /* * if index is valid, this function will return corresponding structure @@ -82,13 +82,13 @@ struct device *soc_uart_console_to_device(int uart_console) */ switch (uart_console) { case 0: - return (struct device *)PCH_DEV_UART0; + return pcidev_path_on_root(PCH_DEVFN_UART0); case 1: - return (struct device *)PCH_DEV_UART1; + return pcidev_path_on_root(PCH_DEVFN_UART1); case 2: - return (struct device *)PCH_DEV_UART2; + return pcidev_path_on_root(PCH_DEVFN_UART2); case 3: - return (struct device *)PCH_DEV_UART3; + return pcidev_path_on_root(PCH_DEVFN_UART3); default: printk(BIOS_ERR, "Invalid UART console index\n"); return NULL; diff --git a/src/soc/intel/apollolake/xhci.c b/src/soc/intel/apollolake/xhci.c new file mode 100644 index 0000000000..131610756f --- /dev/null +++ b/src/soc/intel/apollolake/xhci.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#if CONFIG(SOC_INTEL_GLK) +#define XHCI_USB3_PORT_STATUS_REG 0x510 +#define XHCI_USB2_PORT_NUM 9 +#else +#define XHCI_USB3_PORT_STATUS_REG 0x500 +#define XHCI_USB2_PORT_NUM 8 +#endif +#define XHCI_USB3_PORT_NUM 7 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + +const struct xhci_usb_info *soc_get_xhci_usb_info(void) +{ + return &usb_info; +} diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 6e6eb9cc44..d9663462c6 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -9,50 +9,51 @@ subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common -ramstage-y += memmap.c -romstage-y += memmap.c -postcar-y += memmap.c -ramstage-y += tsc_freq.c -romstage-y += tsc_freq.c -postcar-y += tsc_freq.c -smm-y += tsc_freq.c -romstage-y += spi.c -postcar-y += spi.c -ramstage-y += spi.c -smm-y += spi.c -ramstage-y += chip.c -ramstage-y += gfx.c -ramstage-y += iosf.c romstage-y += iosf.c -smm-y += iosf.c -postcar-y += iosf.c -ramstage-y += northcluster.c -ramstage-y += ramstage.c -ramstage-y += gpio.c -ramstage-y += cpu.c +romstage-y += memmap.c romstage-y += pmutil.c +romstage-y += spi.c +romstage-y += tsc_freq.c + +postcar-y += iosf.c +postcar-y += memmap.c +postcar-y += spi.c +postcar-y += tsc_freq.c + +ramstage-y += acpi.c +ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-y += dptf.c +ramstage-y += ehci.c +ramstage-y += emmc.c +ramstage-y += gfx.c +ramstage-y += gpio.c +ramstage-y += hda.c +ramstage-y += iosf.c +ramstage-y += lpe.c +ramstage-y += lpss.c +ramstage-y += memmap.c +ramstage-y += northcluster.c +ramstage-y += pcie.c +ramstage-y += perf_power.c ramstage-y += pmutil.c +ramstage-y += ramstage.c +ramstage-y += sata.c +ramstage-y += scc.c +ramstage-y += sd.c +ramstage-y += smm.c +ramstage-y += southcluster.c +ramstage-y += spi.c +ramstage-y += tsc_freq.c +ramstage-y += xhci.c +ramstage-$(CONFIG_ELOG) += elog.c +ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c + +smm-y += iosf.c smm-y += pmutil.c smm-y += smihandler.c -ramstage-y += smm.c -ramstage-y += ehci.c -ramstage-y += xhci.c -ramstage-y += southcluster.c -ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c -ramstage-y += sata.c -ramstage-y += acpi.c -ramstage-y += lpe.c -ramstage-y += scc.c -ramstage-y += emmc.c -ramstage-y += lpss.c -ramstage-y += pcie.c -ramstage-y += sd.c -ramstage-y += dptf.c -ramstage-y += perf_power.c -ramstage-y += stage_cache.c -romstage-y += stage_cache.c -ramstage-$(CONFIG_ELOG) += elog.c -ramstage-y += hda.c +smm-y += spi.c +smm-y += tsc_freq.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index 7736e721af..00e7fd6f73 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -69,7 +69,7 @@ struct soc_intel_baytrail_config { /* Allow PCIe devices to wake system from suspend. */ int pcie_wake_enable; - int gpu_pipea_port_select; /* Port select: 1=DP_B 2=DP_C */ + uint8_t gpu_pipea_port_select; /* Port select: 1=DP_B 2=DP_C */ uint16_t gpu_pipea_power_on_delay; uint16_t gpu_pipea_light_on_delay; uint16_t gpu_pipea_power_off_delay; @@ -77,7 +77,7 @@ struct soc_intel_baytrail_config { uint16_t gpu_pipea_power_cycle_delay; int gpu_pipea_pwm_freq_hz; - int gpu_pipeb_port_select; /* Port select: 1=DP_B 2=DP_C */ + uint8_t gpu_pipeb_port_select; /* Port select: 1=DP_B 2=DP_C */ uint16_t gpu_pipeb_power_on_delay; uint16_t gpu_pipeb_light_on_delay; uint16_t gpu_pipeb_power_off_delay; diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c index 002d38c633..9082feaa16 100644 --- a/src/soc/intel/baytrail/ehci.c +++ b/src/soc/intel/baytrail/ehci.c @@ -88,7 +88,7 @@ static const struct reg_script ehci_hc_reset[] = { static void usb2_phy_init(struct device *dev) { - struct soc_intel_baytrail_config *config = dev->chip_info; + struct soc_intel_baytrail_config *config = config_of(dev); u32 usb2_comp_bg = (config->usb2_comp_bg == 0 ? 0x4700 : config->usb2_comp_bg); struct reg_script usb2_phy_script[] = { @@ -123,7 +123,7 @@ static void usb2_phy_init(struct device *dev) static void ehci_init(struct device *dev) { - struct soc_intel_baytrail_config *config = dev->chip_info; + struct soc_intel_baytrail_config *config = config_of(dev); struct reg_script ehci_hc_init[] = { /* Controller init */ REG_SCRIPT_NEXT(ehci_init_script), diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index bf5a8dd42f..a99fe5a424 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -46,7 +46,7 @@ static const struct reg_script emmc_ops[] = { static void emmc_init(struct device *dev) { - struct soc_intel_baytrail_config *config = dev->chip_info; + struct soc_intel_baytrail_config *config = config_of(dev); printk(BIOS_DEBUG, "eMMC init\n"); reg_script_run_on_dev(dev, emmc_ops); diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 2048c13824..5100c8e777 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -313,20 +313,20 @@ static void set_backlight_pwm(struct device *dev, uint32_t bklt_reg, int req_hz) static void gfx_panel_setup(struct device *dev) { - struct soc_intel_baytrail_config *config = dev->chip_info; + struct soc_intel_baytrail_config *config = config_of(dev); struct reg_script gfx_pipea_init[] = { /* CONTROL */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_CONTROL), PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), /* POWER ON */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_ON_DELAYS), - (config->gpu_pipea_port_select << 30 | - config->gpu_pipea_power_on_delay << 16 | - config->gpu_pipea_light_on_delay)), + ((u32)config->gpu_pipea_port_select << 30 | + (u32)config->gpu_pipea_power_on_delay << 16 | + (u32)config->gpu_pipea_light_on_delay)), /* POWER OFF */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_OFF_DELAYS), - (config->gpu_pipea_power_off_delay << 16 | - config->gpu_pipea_light_off_delay)), + ((u32)config->gpu_pipea_power_off_delay << 16 | + (u32)config->gpu_pipea_light_off_delay)), /* DIVISOR */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_DIVISOR), ~0x1f, config->gpu_pipea_power_cycle_delay), @@ -338,13 +338,13 @@ static void gfx_panel_setup(struct device *dev) PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), /* POWER ON */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_ON_DELAYS), - (config->gpu_pipeb_port_select << 30 | - config->gpu_pipeb_power_on_delay << 16 | - config->gpu_pipeb_light_on_delay)), + ((u32)config->gpu_pipeb_port_select << 30 | + (u32)config->gpu_pipeb_power_on_delay << 16 | + (u32)config->gpu_pipeb_light_on_delay)), /* POWER OFF */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_OFF_DELAYS), - (config->gpu_pipeb_power_off_delay << 16 | - config->gpu_pipeb_light_off_delay)), + ((u32)config->gpu_pipeb_power_off_delay << 16 | + (u32)config->gpu_pipeb_light_off_delay)), /* DIVISOR */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_DIVISOR), ~0x1f, config->gpu_pipeb_power_cycle_delay), diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index 1843f08073..9636640108 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -91,7 +91,7 @@ static void setup_codec_clock(struct device *dev) struct soc_intel_baytrail_config *config; const char *freq_str; - config = dev->chip_info; + config = config_of(dev); switch (config->lpe_codec_clk_freq) { case 19: freq_str = "19.2"; @@ -150,7 +150,7 @@ static void lpe_stash_firmware_info(struct device *dev) static void lpe_init(struct device *dev) { - struct soc_intel_baytrail_config *config = dev->chip_info; + struct soc_intel_baytrail_config *config = config_of(dev); lpe_stash_firmware_info(dev); diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index a21a788134..4ffdca9d63 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -148,7 +148,7 @@ static void i2c_disable_resets(struct device *dev) static void lpss_init(struct device *dev) { - struct soc_intel_baytrail_config *config = dev->chip_info; + struct soc_intel_baytrail_config *config = config_of(dev); int iosf_reg, nvs_index; dev_ctl_reg(dev, &iosf_reg, &nvs_index); diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index 211f476712..94e91ca7a1 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -14,6 +14,7 @@ */ #include +#include #include #include @@ -26,3 +27,16 @@ void *cbmem_top(void) { return (void *) smm_region_start(); } + +void stage_cache_external_region(void **base, size_t *size) +{ + char *smm_base; + /* 1MiB cache size */ + const long cache_size = CONFIG_SMM_RESERVED_SIZE; + + /* Ramstage cache lives in TSEG region which is the definition of + * cbmem_top(). */ + smm_base = cbmem_top(); + *size = cache_size; + *base = &smm_base[smm_region_size() - cache_size]; +} diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 33c5455c50..b2b2d3c3b4 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -108,11 +108,11 @@ static void byt_pcie_init(struct device *dev) reg_script_run_on_dev(dev, init_script); if (is_first_port(dev)) { - struct soc_intel_baytrail_config *config = dev->chip_info; + struct soc_intel_baytrail_config *config = config_of(dev); uint32_t reg = pci_read_config32(dev, RPPGEN); reg |= SRDLCGEN | SRDBCGEN; - if (config && config->clkreq_enable) + if (config->clkreq_enable) reg |= LCLKREQEN | BBCLKREQEN; pci_write_config32(dev, RPPGEN, reg); @@ -208,13 +208,13 @@ static void check_device_present(struct device *dev) static void byt_pcie_enable(struct device *dev) { if (is_first_port(dev)) { - struct soc_intel_baytrail_config *config = dev->chip_info; + struct soc_intel_baytrail_config *config = config_of(dev); uint32_t reg = pci_read_config32(dev, PHYCTL2_IOSFBCTL); pll_en_off = !!(reg & PLL_OFF_EN); strpfusecfg = pci_read_config32(dev, STRPFUSECFG); - if (config && config->pcie_wake_enable) + if (config->pcie_wake_enable) southcluster_smm_save_param( SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1); } diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index 596ed11fa4..882edf0a60 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -47,8 +47,7 @@ void punit_init(void) rid = pci_read_config8(IOSF_PCI_DEV, REVID); dev = pcidev_on_root(SOC_DEV, SOC_FUNC); - if (dev) - cfg = dev->chip_info; + cfg = config_of(dev); reg = iosf_punit_read(SB_BIOS_CONFIG); /* Write bits 17:16 of SB_BIOS_CONFIG in the PUNIT. */ diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c index e7636fe4f4..084d7865b4 100644 --- a/src/soc/intel/baytrail/sata.c +++ b/src/soc/intel/baytrail/sata.c @@ -36,18 +36,13 @@ static inline void sir_write(struct device *dev, int idx, u32 value) static void sata_init(struct device *dev) { - config_t *config = dev->chip_info; + config_t *config = config_of(dev); u32 reg32; u16 reg16; u8 reg8; printk(BIOS_DEBUG, "SATA: Initializing...\n"); - if (config == NULL) { - printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); - return; - } - if (!config->sata_ahci) { /* Set legacy or native decoding mode */ if (config->ide_legacy_combined) { @@ -158,14 +153,12 @@ static void sata_init(struct device *dev) static void sata_enable(struct device *dev) { - config_t *config = dev->chip_info; + config_t *config = config_of(dev); u8 reg8; u16 reg16; u32 reg32; southcluster_enable_dev(dev); - if (!config) - return; /* Port mapping -- mask off SPD + SMS + SC bits, then re-set */ reg16 = pci_read_config16(dev, 0x90); diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c index cbdb7bb181..dcb20734e3 100644 --- a/src/soc/intel/baytrail/sd.c +++ b/src/soc/intel/baytrail/sd.c @@ -32,10 +32,7 @@ static void sd_init(struct device *dev) { - struct soc_intel_baytrail_config *config = dev->chip_info; - - if (config == NULL) - return; + struct soc_intel_baytrail_config *config = config_of(dev); if (config->sdcard_cap_low != 0 || config->sdcard_cap_high != 0) { printk(BIOS_DEBUG, "Overriding SD Card controller caps.\n"); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 0289e8b4de..8f65433f05 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -177,7 +177,7 @@ static void sc_init(struct device *dev) u32 *gen_pmcon1 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1); u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); const struct baytrail_irq_route *ir = &global_baytrail_irq_route; - struct soc_intel_baytrail_config *config = dev->chip_info; + struct soc_intel_baytrail_config *config = config_of(dev); /* Set up the PIRQ PIC routing based on static config. */ for (i = 0; i < NUM_PIRQS; i++) { diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 6408cd9a9c..d9f2c53eaa 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -197,7 +197,7 @@ static void xhci_route_all(struct device *dev) static void xhci_init(struct device *dev) { - struct soc_intel_baytrail_config *config = dev->chip_info; + struct soc_intel_baytrail_config *config = config_of(dev); struct reg_script xhci_hc_init[] = { /* Initialize clock gating */ REG_SCRIPT_NEXT(xhci_clock_gating_script), diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 7887156716..5d6438fee5 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -14,7 +14,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COLLECT_TIMESTAMPS select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_NOT_IN_BLOB_REPO @@ -74,10 +73,6 @@ config MAX_CPUS int default 4 -config CPU_ADDR_BITS - int - default 36 - config SMM_TSEG_SIZE hex default 0x800000 @@ -130,10 +125,6 @@ config ENABLE_BUILTIN_COM1 configure the pads and enable it. This serial port can be used for the debug console. -config IED_REGION_SIZE - hex - default 0x400000 - config DISABLE_HPET bool "Disable the HPET device" default n diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 900b2f33fd..d179cead25 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -96,7 +96,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) return; } - config = dev->chip_info; + config = config_of(dev); /* Set the parameters for SiliconInit */ printk(BIOS_DEBUG, "Updating UPD values for SiliconInit\n"); diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 5f86a11db1..1cee4b9ca4 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -151,7 +150,7 @@ static int get_cpu_count(void) static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; /* All range registers are aligned to 4KiB */ @@ -159,7 +158,7 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, /* Initialize global tracking state. */ smm_region(&smm_base, &smm_size); - relo_attrs.smbase = (uint32_t)smm_base; + relo_attrs.smbase = smm_base; relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; diff --git a/src/soc/intel/braswell/emmc.c b/src/soc/intel/braswell/emmc.c index 09e801daaa..aae496a276 100644 --- a/src/soc/intel/braswell/emmc.c +++ b/src/soc/intel/braswell/emmc.c @@ -33,7 +33,7 @@ static const struct reg_script emmc_ops[] = { static void emmc_init(struct device *dev) { - struct soc_intel_braswell_config *config = dev->chip_info; + struct soc_intel_braswell_config *config = config_of(dev); printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index a06d7a658f..58e3492771 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -96,7 +96,7 @@ static void setup_codec_clock(struct device *dev) struct soc_intel_braswell_config *config; const char *freq_str; - config = dev->chip_info; + config = config_of(dev); switch (config->lpe_codec_clk_src) { case LPE_CLK_SRC_XTAL: /* XTAL driven bit2=0 */ @@ -152,7 +152,7 @@ static void lpe_stash_firmware_info(struct device *dev) static void lpe_init(struct device *dev) { - struct soc_intel_braswell_config *config = dev->chip_info; + struct soc_intel_braswell_config *config = config_of(dev); printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c index d1ce76a5d6..245fc4ff3f 100644 --- a/src/soc/intel/braswell/lpss.c +++ b/src/soc/intel/braswell/lpss.c @@ -139,7 +139,7 @@ static void i2c_disable_resets(struct device *dev) static void lpss_init(struct device *dev) { - struct soc_intel_braswell_config *config = dev->chip_info; + struct soc_intel_braswell_config *config = config_of(dev); int iosf_reg, nvs_index; printk(BIOS_SPEW, "%s/%s (%s)\n", diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index 207c843d52..51b7b36db4 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -15,7 +15,7 @@ */ #include -#include +#include #include #include @@ -28,19 +28,12 @@ static size_t smm_region_size(void) return smm_size; } -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)((iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20); + *start = (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20; *size = smm_region_size(); } -size_t mmap_region_granularity(void) -{ - /* Align to TSEG size when SMM is in use, and 8MiB by default */ - return CONFIG(HAVE_SMI_HANDLER) ? smm_region_size() - : 8 << 20; -} - /* * Subregions within SMM * +-------------------------+ BUNIT_SMRRH @@ -50,15 +43,13 @@ size_t mmap_region_granularity(void) * | (TSEG) | * +-------------------------+ BUNIT_SMRRL */ -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; - void *sub_ptr; size_t sub_size; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - smm_region(&sub_ptr, &sub_size); - sub_base = (uintptr_t)sub_ptr; + smm_region(&sub_base, &sub_size); switch (sub) { case SMM_SUBREGION_HANDLER: @@ -71,18 +62,19 @@ int smm_subregion(int sub, void **start, size_t *size) sub_size = cache_size; break; default: + *start = 0; + *size = 0; return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; - return 0; } void *cbmem_top(void) { - char *smm_base; + uintptr_t smm_base; size_t smm_size; /* @@ -113,6 +105,6 @@ void *cbmem_top(void) * +-------------------------+ */ - smm_region((void **)&smm_base, &smm_size); + smm_region(&smm_base, &smm_size); return (void *)smm_base; } diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 9267448697..ff58ebfeec 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -21,8 +21,8 @@ #include #include #include -#include #include +#include #include #include #include @@ -87,7 +87,7 @@ static void nc_read_resources(struct device *dev) unsigned long mmconf; unsigned long bmbound_k; unsigned long bmbound_hi; - void *smm_base; + uintptr_t smm_base; size_t smm_size; unsigned long tseg_base_k; unsigned long tseg_top_k; @@ -102,7 +102,7 @@ static void nc_read_resources(struct device *dev) /* Determine TSEG data */ smm_region(&smm_base, &smm_size); - tseg_base_k = RES_IN_KIB((unsigned long) smm_base); + tseg_base_k = RES_IN_KIB(smm_base); tseg_top_k = tseg_base_k + RES_IN_KIB(smm_size); /* Determine the base of the FSP reserved memory */ diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c index 6e387d1d6b..dc779bbb80 100644 --- a/src/soc/intel/braswell/pcie.c +++ b/src/soc/intel/braswell/pcie.c @@ -141,13 +141,13 @@ static void pcie_enable(struct device *dev) printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); if (is_first_port(dev)) { - struct soc_intel_braswell_config *config = dev->chip_info; + struct soc_intel_braswell_config *config = config_of(dev); uint32_t reg = pci_read_config32(dev, PHYCTL2_IOSFBCTL); pll_en_off = !!(reg & PLL_OFF_EN); strpfusecfg = pci_read_config32(dev, STRPFUSECFG); - if (config && config->pcie_wake_enable) + if (config->pcie_wake_enable) southcluster_smm_save_param( SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1); } diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index e0e22f220e..38a0c2e693 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -124,7 +124,7 @@ void soc_memory_init_params(struct romstage_params *params, return; } - config = dev->chip_info; + config = config_of(dev); printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n"); upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ? config->PcdMrcInitTsegSize : 0; diff --git a/src/soc/intel/braswell/sd.c b/src/soc/intel/braswell/sd.c index 2f3dadb1d0..3816fc46e2 100644 --- a/src/soc/intel/braswell/sd.c +++ b/src/soc/intel/braswell/sd.c @@ -33,14 +33,11 @@ static void sd_init(struct device *dev) { - struct soc_intel_braswell_config *config = dev->chip_info; + struct soc_intel_braswell_config *config = config_of(dev); printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); - if (config == NULL) - return; - if (config->sdcard_cap_low != 0 || config->sdcard_cap_high != 0) { printk(BIOS_DEBUG, "Overriding SD Card controller caps.\n"); pci_write_config32(dev, CAP_OVERRIDE_LOW, diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index bf9f689c2a..67e941c511 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -286,7 +286,7 @@ static void sc_init(struct device *dev) const unsigned long ilb_base = ILB_BASE_ADDRESS; void *gen_pmcon1 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON1); const struct soc_irq_route *ir = &global_soc_irq_route; - struct soc_intel_braswell_config *config = dev->chip_info; + struct soc_intel_braswell_config *config = config_of(dev); printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); diff --git a/src/soc/intel/braswell/xhci.c b/src/soc/intel/braswell/xhci.c index 6c9048238f..42288f9e18 100644 --- a/src/soc/intel/braswell/xhci.c +++ b/src/soc/intel/braswell/xhci.c @@ -33,9 +33,9 @@ static void xhci_init(struct device *dev) { - struct soc_intel_braswell_config *config = dev->chip_info; + struct soc_intel_braswell_config *config = config_of(dev); - if (config && config->usb_comp_bg) { + if (config->usb_comp_bg) { struct reg_script ops[] = { REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG, config->usb_comp_bg), diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index bf6b78c222..696cf98ef9 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -15,7 +15,6 @@ config CPU_SPECIFIC_OPTIONS select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index a79fa464a9..91a3da02c6 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -68,9 +68,6 @@ romstage-y += spi.c postcar-y += spi.c ramstage-y += spi.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c -ramstage-y += stage_cache.c -romstage-y += stage_cache.c -postcar-y += stage_cache.c ramstage-y += systemagent.c bootblock-y += tsc_freq.c ramstage-y += tsc_freq.c diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 25867c5677..705bc0089e 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -386,12 +386,12 @@ static void generate_T_state_entries(int core, int cores_per_package) static void generate_C_state_entries(void) { - struct device *dev = SA_DEV_ROOT; - config_t *config = dev->chip_info; acpi_cstate_t map[3]; int *set; int i; + config_t *config = config_of_path(SA_DEVFN_ROOT); + if (config->s0ix_enable) set = cstate_set_s0ix; else diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index 7658515c12..c4023cc84a 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -31,7 +31,7 @@ static void adsp_init(struct device *dev) { - config_t *config = dev->chip_info; + config_t *config = config_of(dev); struct resource *bar0, *bar1; u32 tmp32; diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 5592538ab3..5ccaeaf810 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -195,8 +195,7 @@ static int pcode_mailbox_write(u32 command, u32 data) static void initialize_vr_config(void) { - struct device *dev = SA_DEV_ROOT; - config_t *conf = dev->chip_info; + config_t *conf = config_of_path(SA_DEVFN_ROOT); msr_t msr; printk(BIOS_DEBUG, "Initializing VR config.\n"); @@ -325,8 +324,8 @@ void set_power_limits(u8 power_limit_1_time) unsigned int tdp, min_power, max_power, max_time; u8 power_limit_1_val; - if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr)) - power_limit_1_time = 28; + if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) + power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; if (!(msr.lo & PLATFORM_INFO_SET_TDP)) return; @@ -450,10 +449,10 @@ static void configure_c_states(void) static void configure_thermal_target(void) { - struct device *dev = SA_DEV_ROOT; - config_t *conf = dev->chip_info; + config_t *conf = config_of_path(SA_DEVFN_ROOT); msr_t msr; + /* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); if ((msr.lo & (1 << 30)) && conf->tcc_offset) { diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 1adbbc8aa2..06cc18d67a 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -96,9 +96,11 @@ const struct reg_script pch_finalize_script[] = { static void broadwell_finalize(void *unused) { + struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + printk(BIOS_DEBUG, "Finalizing chipset.\n"); - reg_script_run_on_dev(SA_DEV_ROOT, system_agent_finalize_script); + reg_script_run_on_dev(sa_dev, system_agent_finalize_script); reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script); /* Lock */ diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 9107b23eb9..dab2d15750 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -298,7 +298,7 @@ static int gtt_poll(u32 reg, u32 mask, u32 value) static void igd_setup_panel(struct device *dev) { - config_t *conf = dev->chip_info; + config_t *conf = config_of(dev); u32 reg32; /* Setup Digital Port Hotplug */ @@ -349,7 +349,7 @@ static void igd_setup_panel(struct device *dev) static int igd_get_cdclk_haswell(u32 *const cdsel, int *const inform_pc, struct device *const dev) { - const config_t *const conf = dev->chip_info; + const config_t *const conf = config_of(dev); int cdclk = conf->cdclk; /* Check for ULX GT1 or GT2 */ @@ -383,7 +383,7 @@ static int igd_get_cdclk_broadwell(u32 *const cdsel, int *const inform_pc, struct device *const dev) { static const u32 cdsel_by_cdclk[] = { 0, 2, 0, 1, 3 }; - const config_t *const conf = dev->chip_info; + const config_t *const conf = config_of(dev); int cdclk = conf->cdclk; /* Check for ULX */ diff --git a/src/soc/intel/broadwell/include/soc/pci_devs.h b/src/soc/intel/broadwell/include/soc/pci_devs.h index 522e3eb166..423f0d6635 100644 --- a/src/soc/intel/broadwell/include/soc/pci_devs.h +++ b/src/soc/intel/broadwell/include/soc/pci_devs.h @@ -16,32 +16,31 @@ #ifndef _BROADWELL_PCI_DEVS_H_ #define _BROADWELL_PCI_DEVS_H_ -#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) #if defined(__SIMPLE_DEVICE__) -#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) #else #include #include -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #endif /* System Agent Devices */ #define SA_DEV_SLOT_ROOT 0x00 -#define SA_DEVFN_ROOT _SA_DEVFN(ROOT) -#define SA_DEV_ROOT _SA_DEV(ROOT) +#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) +#if defined(__SIMPLE_DEVICE__) +#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) +#endif #define SA_DEV_SLOT_IGD 0x02 -#define SA_DEVFN_IGD _SA_DEVFN(IGD) -#define SA_DEV_IGD _SA_DEV(IGD) +#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) +#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) #define SA_DEV_SLOT_MINIHD 0x03 -#define SA_DEVFN_MINIHD _SA_DEVFN(MINIHD) -#define SA_DEV_MINIHD _SA_DEV(MINIHD) +#define SA_DEVFN_MINIHD PCI_DEVFN(SA_DEV_SLOT_MINIHD, 0) +#define SA_DEV_MINIHD PCI_DEV(0, SA_DEV_SLOT_MINIHD, 0) /* PCH Devices */ diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index df1d857a2d..b385d6b637 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -104,7 +104,7 @@ static void enable_hpet(struct device *dev) static void pch_pirq_init(struct device *dev) { struct device *irq_dev; - config_t *config = dev->chip_info; + config_t *config = config_of(dev); pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); @@ -151,7 +151,7 @@ static void pch_power_options(struct device *dev) u16 reg16; const char *state; /* Get the chip configuration */ - config_t *config = dev->chip_info; + config_t *config = config_of(dev); int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; /* Which state do we want to goto after g3 (power restored)? @@ -318,7 +318,7 @@ static void pch_enable_mphy(void) static void pch_init_deep_sx(struct device *dev) { - config_t *config = dev->chip_info; + config_t *config = config_of(dev); if (config->deep_sx_enable_ac) { RCBA32_OR(DEEP_S3_POL, DEEP_S3_EN_AC); @@ -365,6 +365,7 @@ static void pch_cg_init(struct device *dev) { u32 reg32; u16 reg16; + struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); /* DMI */ RCBA32_OR(0x2234, 0xf); @@ -388,7 +389,7 @@ static void pch_cg_init(struct device *dev) RCBA32_AND_OR(0x2614, ~0x64ff0000, 0x0a206500); /* Check for 0:2.0@0x08 >= 0x0b */ - if (pch_is_wpt() || pci_read_config8(SA_DEV_IGD, 0x8) >= 0x0b) + if (pch_is_wpt() || pci_read_config8(igd_dev, 0x8) >= 0x0b) RCBA32_OR(0x2614, (1 << 26)); RCBA32_OR(0x900, 0x0000031f); @@ -550,7 +551,7 @@ static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, static void pch_lpc_add_io_resources(struct device *dev) { struct resource *res; - config_t *config = dev->chip_info; + config_t *config = config_of(dev); /* Add the default claimed IO range for the LPC device. */ res = new_resource(dev, 0); diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index dd5e5b870c..6be17489e1 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -971,7 +971,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) /* Check whether ME is present and do basic init */ static void intel_me_init(struct device *dev) { - config_t *config = dev->chip_info; + config_t *config = config_of(dev); me_bios_path path = intel_me_path(dev); me_bios_payload mbp_data; int mbp_ret; @@ -1004,7 +1004,7 @@ static void intel_me_init(struct device *dev) intel_me_print_mbp(&mbp_data); /* Set clock enables according to devicetree */ - if (config && config->icc_clock_disable) + if (config->icc_clock_disable) me_icc_set_clock_enables(config->icc_clock_disable); /* Make sure ME is in a mode that expects EOP */ diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 7443121100..7c53fa6468 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -13,11 +13,16 @@ * GNU General Public License for more details. */ -#include +#define __SIMPLE_DEVICE__ + #include #include +#include #include #include +#include +#include +#include static uintptr_t dpr_region_start(void) { @@ -40,3 +45,15 @@ void *cbmem_top(void) { return (void *) dpr_region_start(); } + +void stage_cache_external_region(void **base, size_t *size) +{ + /* The ramstage cache lives in the TSEG region. + * The top of RAM is defined to be the TSEG base address. */ + u32 offset = smm_region_size(); + offset -= CONFIG_IED_REGION_SIZE; + offset -= CONFIG_SMM_RESERVED_SIZE; + + *base = (void *)(cbmem_top() + offset); + *size = CONFIG_SMM_RESERVED_SIZE; +} diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c index d44e1532b3..d51230a3f7 100644 --- a/src/soc/intel/broadwell/minihd.c +++ b/src/soc/intel/broadwell/minihd.c @@ -64,7 +64,8 @@ static const u32 minihd_verb_table[] = { static void minihd_init(struct device *dev) { struct resource *res; - u8 *base, reg32; + u8 *base; + u32 reg32; int codec_mask, i; /* Find base address */ diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index dff4f8139f..bdaced2edd 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -135,10 +135,8 @@ static void root_port_init_config(struct device *dev) root_port_config_update_gbe_port(); pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4)); - if (dev->chip_info != NULL) { - config_t *config = dev->chip_info; - rpc.coalesce = config->pcie_port_coalesce; - } + config_t *config = config_of(dev); + rpc.coalesce = config->pcie_port_coalesce; } rp = root_port_number(dev); @@ -449,7 +447,7 @@ static void pcie_add_0x0202000_iobp(u32 reg) static void pch_pcie_early(struct device *dev) { - config_t *config = dev->chip_info; + config_t *config = config_of(dev); int do_aspm = 0; int rp = root_port_number(dev); @@ -481,7 +479,7 @@ static void pch_pcie_early(struct device *dev) } /* Allow ASPM to be forced on in devicetree */ - if (config && (config->pcie_port_force_aspm & (1 << (rp - 1)))) + if ((config->pcie_port_force_aspm & (1 << (rp - 1)))) do_aspm = 1; printk(BIOS_DEBUG, "PCIe Root Port %d ASPM is %sabled\n", diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index ea2726bfa5..0bd4ccd471 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -76,13 +76,9 @@ const struct reg_script pch_interrupt_init_script[] = { static void pch_enable_lpc(void) { /* Lookup device tree in romstage */ - const struct device *dev; const config_t *config; - dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0); - if (!dev || !dev->chip_info) - return; - config = dev->chip_info; + config = config_of_path(PCH_DEVFN_LPC); pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec); pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec); diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index cb08ae7d3b..e47a78de6c 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -41,7 +41,7 @@ static inline void sir_write(struct device *dev, int idx, u32 value) static void sata_init(struct device *dev) { - config_t *config = dev->chip_info; + config_t *config = config_of(dev); u32 reg32; u8 *abar; u16 reg16; @@ -271,7 +271,7 @@ static void sata_init(struct device *dev) static void sata_enable(struct device *dev) { /* Get the chip configuration */ - config_t *config = dev->chip_info; + config_t *config = config_of(dev); u16 map = 0x0060; map |= (config->sata_port_map ^ 0xf) << 8; diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index 12e458c057..161c8753f2 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -170,7 +170,7 @@ static void serialio_init_once(int acpi_mode) static void serialio_init(struct device *dev) { - config_t *config = dev->chip_info; + config_t *config = config_of(dev); struct resource *bar0, *bar1; int sio_index = -1; u32 reg32; diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 5dd076f14a..9ea73b2054 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -270,7 +270,7 @@ static void setup_ied_area(struct smm_relocation_params *params) void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - struct device *dev = SA_DEV_ROOT; + struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); @@ -319,10 +319,11 @@ void smm_relocate(void) void smm_lock(void) { + struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); /* LOCK the SMM memory window and enable normal SMM. * After running this function, only a full reset can * make the SMM registers writable again. */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); + pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index c6444b15e8..b6b5608a24 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -32,19 +32,22 @@ u8 systemagent_revision(void) { - return pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID); + struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + return pci_read_config8(sa_dev, PCI_REVISION_ID); } uintptr_t sa_get_tolud_base(void) { + struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); /* Bit 0 is lock bit, not part of address */ - return pci_read_config32(SA_DEV_ROOT, TOLUD) & ~1; + return pci_read_config32(sa_dev, TOLUD) & ~1; } uintptr_t sa_get_gsm_base(void) { + struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); /* Bit 0 is lock bit, not part of address */ - return pci_read_config32(SA_DEV_ROOT, BGSM) & ~1; + return pci_read_config32(sa_dev, BGSM) & ~1; } static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, @@ -291,6 +294,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt) uint64_t mc_values[NUM_MAP_ENTRIES]; unsigned long dpr_size = 0; u32 dpr_reg; + struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); /* Read in the MAP registers and report their values. */ mc_read_map_entries(dev, &mc_values[0]); @@ -302,7 +306,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt) * the DPR register reports the TOP of the region, which is the same * as TSEG base. The region size is reported in MiB in bits 11:4. */ - dpr_reg = pci_read_config32(SA_DEV_ROOT, DPR); + dpr_reg = pci_read_config32(sa_dev, DPR); if (dpr_reg & DPR_EPM) { dpr_size = (dpr_reg & DPR_SIZE_MASK) << 16; printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size); diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 4235b7a0ce..4bc6a65448 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -36,6 +36,7 @@ config SOC_INTEL_COMETLAKE bool select SOC_INTEL_CANNONLAKE_BASE select MICROCODE_BLOB_UNDISCLOSED + select FSP_USES_CB_STACK help Intel Cometlake support @@ -58,7 +59,6 @@ config CPU_SPECIFIC_OPTIONS select BOOT_DEVICE_SUPPORTS_WRITES select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COMMON_FADT select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE @@ -121,6 +121,7 @@ config DCACHE_RAM_SIZE config DCACHE_BSP_STACK_SIZE hex + default 0x20000 if FSP_USES_CB_STACK default 0x4000 help The amount of anticipated stack usage in CAR by bootblock and @@ -269,8 +270,7 @@ config MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE choice prompt "Cache-as-ram implementation" - default USE_CANNONLAKE_CAR_NEM_ENHANCED if MAINBOARD_HAS_CHROMEOS - default USE_CANNONLAKE_FSP_CAR + default USE_CANNONLAKE_CAR_NEM_ENHANCED help This option allows you to select how cache-as-ram (CAR) is set up. diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 8a4a8b71f2..724e141d39 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -56,12 +56,15 @@ ramstage-y += systemagent.c ramstage-y += uart.c ramstage-y += vr_config.c ramstage-y += sd.c +ramstage-y += xhci.c smm-y += elog.c smm-y += p2sb.c +smm-y += pmc.c smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c +smm-y += xhci.c postcar-y += memmap.c postcar-y += pmutil.c diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index dce98c4ea6..89770c0586 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -144,8 +144,9 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) ARRAY_SIZE(cstate_set_non_s0ix))]; int *set; int i; - struct device *dev = SA_DEV_ROOT; - config_t *config = dev->chip_info; + + config_t *config = config_of_path(SA_DEVFN_ROOT); + int is_s0ix_enable = config->s0ix_enable; if (is_s0ix_enable) { @@ -165,18 +166,18 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) void soc_power_states_generation(int core_id, int cores_per_package) { - struct device *dev = SA_DEV_ROOT; - config_t *config = dev->chip_info; + config_t *config = config_of_path(SA_DEVFN_ROOT); + + /* Generate P-state tables */ if (config->eist_enable) - /* Generate P-state tables */ generate_p_state_entries(core_id, cores_per_package); } void soc_fill_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; - const struct device *dev = PCH_DEV_LPC; - const struct soc_intel_cannonlake_config *config = dev->chip_info; + const struct soc_intel_cannonlake_config *config; + config = config_of_path(PCH_DEVFN_LPC); if (!config->PmTimerDisabled) { fadt->pm_tmr_blk = pmbase + PM1_TMR; @@ -200,8 +201,8 @@ uint32_t soc_read_sci_irq_select(void) void acpi_create_gnvs(struct global_nvs_t *gnvs) { - const struct device *dev = PCH_DEV_LPC; - const struct soc_intel_cannonlake_config *config = dev->chip_info; + const struct soc_intel_cannonlake_config *config; + config = config_of_path(PCH_DEVFN_LPC); /* Set unknown wake source */ gnvs->pm1i = -1; diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 5555969289..30c2266096 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -59,6 +59,11 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { + /* + * Clear the GPI interrupt status and enable registers. These + * registers do not get reset to default state when booting from S5. + */ + gpi_clear_int_cfg(); report_platform_info(); pch_early_init(); } diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 1cbbd6384d..480b3b835b 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -40,6 +40,9 @@ static struct { { CPUID_WHISKEYLAKE_V0, "Whiskeylake V0" }, { CPUID_WHISKEYLAKE_W0, "Whiskeylake W0" }, { CPUID_COFFEELAKE_U0, "Coffeelake U0 (6+2)" }, + { CPUID_COFFEELAKE_B0, "Coffeelake B0" }, + { CPUID_COFFEELAKE_P0, "Coffeelake P0" }, + { CPUID_COFFEELAKE_R0, "Coffeelake R0" }, { CPUID_COMETLAKE_U_A0, "Cometlake-U A0 (6+2)" }, { CPUID_COMETLAKE_U_K0_S0, "Cometlake-U K0/S0 (6+2)/(4+2)" }, { CPUID_COMETLAKE_H_S_6_2_P0, "Cometlake-H/S P0 (6+2)" }, @@ -53,10 +56,14 @@ static struct { { PCI_DEVICE_ID_INTEL_CNL_ID_U, "Cannonlake-U" }, { PCI_DEVICE_ID_INTEL_CNL_ID_Y, "Cannonlake-Y" }, { PCI_DEVICE_ID_INTEL_CFL_ID_U, "Coffeelake U (4+3e)" }, - { PCI_DEVICE_ID_INTEL_WHL_ID_Wx4, "Whiskeylake W (4+2)" }, - { PCI_DEVICE_ID_INTEL_WHL_ID_Wx2, "Whiskeylake W (2+2)" }, + { PCI_DEVICE_ID_INTEL_WHL_ID_W_4, "Whiskeylake W (4+2)" }, + { PCI_DEVICE_ID_INTEL_WHL_ID_W_2, "Whiskeylake W (2+2)" }, { PCI_DEVICE_ID_INTEL_CFL_ID_H, "Coffeelake-H" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_H_8, "Coffeelake-H (8+2)" }, { PCI_DEVICE_ID_INTEL_CFL_ID_S, "Coffeelake-S" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4, "Coffeelake-S DT(4)" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8, "Coffeelake-S DT(8+2)" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8, "Coffeelake-S WS(8+2)" }, { PCI_DEVICE_ID_INTEL_CML_ULT, "CometLake-U (4+2)" }, { PCI_DEVICE_ID_INTEL_CML_ULT_2_2, "CometLake-U (2+2)" }, { PCI_DEVICE_ID_INTEL_CML_ULT_6_2, "CometLake-U (6+2)" }, @@ -74,8 +81,15 @@ static struct { { PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC, "Cannonlake-U Base" }, { PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC, "Cannonlake-U Premium" }, { PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" }, + { PCI_DEVICE_ID_INTEL_CNP_H_LPC_H310, "Cannonlake-H H310" }, + { PCI_DEVICE_ID_INTEL_CNP_H_LPC_H370, "Cannonlake-H H370" }, + { PCI_DEVICE_ID_INTEL_CNP_H_LPC_Z390, "Cannonlake-H Z390" }, { PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, "Cannonlake-H Q370" }, + { PCI_DEVICE_ID_INTEL_CNP_H_LPC_B360, "Cannonlake-H B360" }, + { PCI_DEVICE_ID_INTEL_CNP_H_LPC_C246, "Cannonlake-H C246" }, + { PCI_DEVICE_ID_INTEL_CNP_H_LPC_C242, "Cannonlake-H C242" }, { PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, "Cannonlake-H QM370" }, + { PCI_DEVICE_ID_INTEL_CNP_H_LPC_HM370, "Cannonlake-H HM370" }, { PCI_DEVICE_ID_INTEL_CNP_H_LPC_CM246, "Cannonlake-H CM246" }, { PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC, "Cometlake-U Super" }, { PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC, "Cometlake-Y Premium" }, @@ -101,7 +115,10 @@ static struct { { PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT2" }, { PCI_DEVICE_ID_INTEL_CFL_H_GT2, "Coffeelake-H GT2" }, { PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2, "Coffeelake-H Xeon GT2" }, - { PCI_DEVICE_ID_INTEL_CFL_S_GT2, "Coffeelake-S GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT2_1, "Coffeelake-S GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT2_2, "Coffeelake-S GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT2_3, "Coffeelake-S GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT2_4, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1, "CometLake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2, "CometLake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1, "CometLake ULT GT2" }, diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index faddbd5a24..4e0dba5cea 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -170,12 +170,7 @@ void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads) static void soc_fill_gpio_pm_configuration(void) { uint8_t value[TOTAL_GPIO_COMM]; - const struct device *dev; - dev = pcidev_on_root(SA_DEV_SLOT_ROOT, 0); - if (!dev || !dev->chip_info) - return; - - const config_t *config = dev->chip_info; + const config_t *config = config_of_path(SA_DEVFN_ROOT); if (config->gpio_override_pm) memcpy(value, config->gpio_pm, sizeof(uint8_t) * diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 7dae615350..6682cdc7b9 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -105,11 +105,11 @@ void set_power_limits(u8 power_limit_1_time) unsigned int power_unit; unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; u8 power_limit_1_val; - struct device *dev = SA_DEV_ROOT; - config_t *conf = dev->chip_info; - if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr)) - power_limit_1_time = 28; + config_t *conf = config_of_path(SA_DEVFN_ROOT); + + if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) + power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; if (!(msr.lo & PLATFORM_INFO_SET_TDP)) return; @@ -234,11 +234,10 @@ static void soc_fsp_load(void) static void configure_isst(void) { - struct device *dev = SA_DEV_ROOT; - config_t *conf = dev->chip_info; + config_t *conf = config_of_path(SA_DEVFN_ROOT); msr_t msr; - if (conf && conf->speed_shift_enable) { + if (conf->speed_shift_enable) { /* * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP * is supported or not. coreboot needs to configure MSR 0x1AA @@ -260,12 +259,7 @@ static void configure_isst(void) static void configure_misc(void) { - struct device *dev = SA_DEV_ROOT; - if (!dev) { - printk(BIOS_ERR, "SA_DEV_ROOT device not found!\n"); - return; - } - config_t *conf = dev->chip_info; + config_t *conf = config_of_path(SA_DEVFN_ROOT); msr_t msr; msr = rdmsr(IA32_MISC_ENABLE); @@ -367,8 +361,7 @@ static void configure_c_states(void) static void configure_thermal_target(void) { - struct device *dev = SA_DEV_ROOT; - config_t *conf = dev->chip_info; + config_t *conf = config_of_path(SA_DEVFN_ROOT); msr_t msr; /* Set TCC activation offset if supported */ @@ -391,8 +384,14 @@ static void configure_thermal_target(void) */ static void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ + const struct soc_intel_cannonlake_config *config; msr_t msr; + + config = config_of_path(SA_DEVFN_ROOT); + + /* Enable PM timer emulation only if ACPI PM timer is disabled */ + if (!config->PmTimerDisabled) + return; /* * The derived frequency is calculated as follows: * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c index 141aa45b02..a2c359fe10 100644 --- a/src/soc/intel/cannonlake/elog.c +++ b/src/soc/intel/cannonlake/elog.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -24,18 +25,85 @@ #include #include -#define XHCI_USB2_PORT_STATUS_REG 0x480 -#define XHCI_USB3_PORT_STATUS_REG 0x580 -#define XHCI_USB2_PORT_NUM 14 -#define XHCI_USB3_PORT_NUM 10 - -static const struct xhci_usb_info usb_info = { - .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, - .num_usb2_ports = XHCI_USB2_PORT_NUM, - .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, - .num_usb3_ports = XHCI_USB3_PORT_NUM, +struct pme_status_info { +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev; +#else + struct device *dev; +#endif + uint8_t reg_offset; + uint32_t elog_event; }; +#define PME_STS_BIT (1 << 15) + +static void pch_log_add_elog_event(const struct pme_status_info *info) +{ + /* + * If wake source is XHCI, check for detailed wake source events on + * USB2/3 ports. + */ + if ((info->dev == PCH_DEV_XHCI) && + pch_xhci_update_wake_event(soc_get_xhci_usb_info())) + return; + + elog_add_event_wake(info->elog_event, 0); +} + +static void pch_log_pme_internal_wake_source(void) +{ + size_t i; +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev; +#else + struct device *dev; +#endif + uint16_t val; + bool dev_found = false; + + struct pme_status_info pme_status_info[] = { + { PCH_DEV_HDA, 0x54, ELOG_WAKE_SOURCE_PME_HDA }, + { PCH_DEV_GBE, 0xcc, ELOG_WAKE_SOURCE_PME_GBE }, + { PCH_DEV_SATA, 0x74, ELOG_WAKE_SOURCE_PME_SATA }, + { PCH_DEV_CSE, 0x54, ELOG_WAKE_SOURCE_PME_CSE }, + { PCH_DEV_XHCI, 0x74, ELOG_WAKE_SOURCE_PME_XHCI }, + { PCH_DEV_USBOTG, 0x84, ELOG_WAKE_SOURCE_PME_XDCI }, + /* + * The power management control/status register is not + * listed in the cannonlake PCH EDS. We have been told + * that the PMCS register is at offset 0xCC. + */ + { PCH_DEV_CNViWIFI, 0xcc, ELOG_WAKE_SOURCE_PME_WIFI }, + }; + + for (i = 0; i < ARRAY_SIZE(pme_status_info); i++) { + dev = pme_status_info[i].dev; + if (!dev) + continue; + + val = pci_read_config16(dev, pme_status_info[i].reg_offset); + + if ((val == 0xFFFF) || !(val & PME_STS_BIT)) + continue; + + pch_log_add_elog_event(&pme_status_info[i]); + dev_found = true; + } + + /* + * If device is still not found, but the wake source is internal PME, + * try probing XHCI ports to see if any of the USB2/3 ports indicate + * that it was the wake source. This path would be taken in case of GSMI + * logging with S0ix where the pci_pm_resume_noirq runs and clears the + * PME_STS_BIT in controller register. + */ + if (!dev_found) + dev_found = pch_xhci_update_wake_event(soc_get_xhci_usb_info()); + + if (!dev_found) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); +} + static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { int i; @@ -68,7 +136,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) /* XHCI - "Power Management Event Bus 0" events include XHCI */ if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) - pch_xhci_update_wake_event(&usb_info); + pch_log_pme_internal_wake_source(); /* SMBUS Wake */ if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index d099d7779a..c99653b75a 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -56,13 +57,22 @@ static void pch_handle_sideband(config_t *config) static void pch_finalize(void) { - struct device *dev; uint32_t reg32; uint8_t *pmcbase; config_t *config; uint8_t reg8; tco_lockdown(); + + /* + * Set low maximum temp threshold value used for dynamic thermal sensor + * shutdown consideration. + * + * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the + * thermal sensor when CPU is in a C-state and DTS Temp <= LTT. + */ + pch_thermal_configuration(); + /* * Disable ACPI PM timer based on dt policy * @@ -74,8 +84,7 @@ static void pch_finalize(void) * point and hence removed from the root bus. pcidev_path_on_root thus * returns NULL for PCH_DEV_PMC device. */ - dev = SA_DEV_ROOT; - config = dev->chip_info; + config = config_of_path(SA_DEVFN_ROOT); pmcbase = pmc_mmio_regs(); if (config->PmTimerDisabled) { reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 4280c6d077..9c4f0ec29c 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -18,7 +18,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -26,7 +28,7 @@ #include "chip.h" -static const int serial_io_dev[] = { +static const pci_devfn_t serial_io_dev[] = { PCH_DEVFN_I2C0, PCH_DEVFN_I2C1, PCH_DEVFN_I2C2, @@ -97,13 +99,7 @@ static void parse_devicetree_param(const config_t *config, FSP_S_CONFIG *params) static void parse_devicetree(FSP_S_CONFIG *params) { - struct device *dev = SA_DEV_ROOT; - if (!dev) { - printk(BIOS_ERR, "Could not find root device\n"); - return; - } - - const config_t *config = dev->chip_info; + const config_t *config = config_of_path(SA_DEVFN_ROOT); parse_devicetree_param(config, params); } @@ -147,8 +143,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) int i; FSP_S_CONFIG *params = &supd->FspsConfig; FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; - struct device *dev = SA_DEV_ROOT; - config_t *config = dev->chip_info; + struct device *dev; + + config_t *config = config_of_path(SA_DEVFN_ROOT); /* Parse device tree and enable/disable devices */ parse_devicetree(params); @@ -371,6 +368,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchPwrOptEnable = config->dmipwroptimize; params->SataPwrOptEnable = config->satapwroptimize; + /* Disable PCH ACPI timer */ + params->EnableTcoTimer = !config->PmTimerDisabled; + /* Apply minimum assertion width settings if non-zero */ if (config->PchPmSlpS3MinAssert) params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert; @@ -410,6 +410,39 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Set correct Sirq mode based on config */ params->PchSirqMode = config->SerialIrqConfigSirqMode; + + /* Chipset Lockdown */ + if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { + tconfig->PchLockDownGlobalSmi = 0; + tconfig->PchLockDownBiosInterface = 0; + params->PchLockDownBiosLock = 0; + params->PchLockDownRtcMemoryLock = 0; + /* + * TODO: Disable SpiFlashCfgLockDown config after FSP provides + * dedicated UPD + * + * Skip SPI Flash Lockdown from inside FSP. + * Making this config "0" means FSP won't set the FLOCKDN bit + * of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). + * So, it becomes coreboot's responsibility to set this bit + * before end of POST for security concerns. + */ + // params->SpiFlashCfgLockDown = 0; + } else { + tconfig->PchLockDownGlobalSmi = 1; + tconfig->PchLockDownBiosInterface = 1; + params->PchLockDownBiosLock = 1; + params->PchLockDownRtcMemoryLock = 1; + /* + * TODO: Enable SpiFlashCfgLockDown config after FSP provides + * dedicated UPD + * + * Enable SPI Flash Lockdown from inside FSP. + * Making this config "1" means FSP will set the FLOCKDN bit + * of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). + */ + // params->SpiFlashCfgLockDown = 1; + } } /* Mainboard GPIO Configuration */ @@ -417,3 +450,10 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } + +/* Return list of SOC LPSS controllers */ +const pci_devfn_t *soc_lpss_controllers_list(size_t *size) +{ + *size = ARRAY_SIZE(serial_io_dev); + return serial_io_dev; +} diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index 2acfecc5b0..ebe8b0bc6a 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -15,12 +15,14 @@ */ #include +#include #include #include #include #include #include #include +#include #include #include #include @@ -46,25 +48,31 @@ void graphics_soc_init(struct device *dev) graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); } - /* - * GFX PEIM module inside FSP binary is taking care of graphics - * initialization based on INTEL_GMA_ADD_VBT Kconfig - * option and input VBT file. Hence no need to load/execute legacy VGA - * OpROM in order to initialize GFX. - * - * In case of non-FSP solution, SoC need to select VGA_ROM_RUN - * Kconfig to perform GFX initialization through VGA OpRom. - */ - if (CONFIG(INTEL_GMA_ADD_VBT)) - return; - /* IGD needs to Bus Master */ uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; pci_write_config32(dev, PCI_COMMAND, reg32); - /* Initialize PCI device, load/execute BIOS Option ROM */ - pci_dev_init(dev); + /* + * GFX PEIM module inside FSP binary is taking care of graphics + * initialization based on RUN_FSP_GOP Kconfig option and input + * VBT file. + * + * In case of non-FSP solution, SoC need to select another + * Kconfig to perform GFX initialization. + */ + if (CONFIG(RUN_FSP_GOP)) { + /* nothing to do */ + } else if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { + if (!acpi_is_wakeup_s3() && display_init_required()) { + int lightup_ok; + gma_gfxinit(&lightup_ok); + gfx_set_init_done(lightup_ok); + } + } else { + /* Initialize PCI device, load/execute BIOS Option ROM */ + pci_dev_init(dev); + } } uintptr_t graphics_soc_write_acpi_opregion(struct device *device, diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index 1bc028f194..88cfe59902 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -19,35 +19,34 @@ #include -#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) #if !defined(__SIMPLE_DEVICE__) #include -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #else -#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) #endif /* System Agent Devices */ #define SA_DEV_SLOT_ROOT 0x00 -#define SA_DEVFN_ROOT _SA_DEVFN(ROOT) -#define SA_DEV_ROOT _SA_DEV(ROOT) +#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) +#if defined(__SIMPLE_DEVICE__) +#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) +#endif #define SA_DEV_SLOT_IGD 0x02 -#define SA_DEVFN_IGD _SA_DEVFN(IGD) -#define SA_DEV_IGD _SA_DEV(IGD) +#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) +#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) #define SA_DEV_SLOT_DSP 0x04 -#define SA_DEVFN_DSP _SA_DEVFN(DSP) -#define SA_DEV_DSP _SA_DEV(DSP) +#define SA_DEVFN_DSP PCI_DEVFN(SA_DEV_SLOT_DSP, 0) +#define SA_DEV_DSP PCI_DEV(0, SA_DEV_SLOT_DSP, 0) #define SA_DEV_SLOT_IPU 0x05 -#define SA_DEVFN_IPU _SA_DEVFN(IPU) -#define SA_DEV_IPU _SA_DEV(IPU) +#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) +#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) /* PCH Devices */ #define PCH_DEV_SLOT_THERMAL 0x12 diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h index c0ab82f0b7..e2367a7795 100644 --- a/src/soc/intel/cannonlake/include/soc/smm.h +++ b/src/soc/intel/cannonlake/include/soc/smm.h @@ -19,7 +19,7 @@ #include #include -#include +#include #include struct ied_header { @@ -29,10 +29,8 @@ struct ied_header { } __packed; struct smm_relocation_params { - u32 smram_base; - u32 smram_size; - u32 ied_base; - u32 ied_size; + uintptr_t ied_base; + size_t ied_size; msr_t smrr_base; msr_t smrr_mask; msr_t emrr_base; diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index ad841bf112..34d715dd11 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -51,7 +51,7 @@ const struct lpc_mmio_range *soc_get_fixed_mmio_ranges() void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) { - const config_t *config = dev->chip_info; + const config_t *config = config_of(dev); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c index c9748b7343..b8b4245d43 100644 --- a/src/soc/intel/cannonlake/me.c +++ b/src/soc/intel/cannonlake/me.c @@ -298,5 +298,4 @@ void dump_me_status(void *unused) hfsts6.fields.txt_support ? "YES" : "NO"); } -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, dump_me_status, NULL); BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, dump_me_status, NULL); diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 5dfa1cc9f3..9b75f167e8 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -29,9 +29,9 @@ #include "chip.h" -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)sa_get_tseg_base(); + *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } @@ -46,16 +46,14 @@ void smm_region(void **start, size_t *size) * | (TSEG) | * +-------------------------+ TSEG */ -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; size_t sub_size; - void *smm_base; const size_t ied_size = CONFIG_IED_REGION_SIZE; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - smm_region(&smm_base, &sub_size); - sub_base = (uintptr_t)smm_base; + smm_region(&sub_base, &sub_size); switch (sub) { case SMM_SUBREGION_HANDLER: @@ -74,12 +72,13 @@ int smm_subregion(int sub, void **start, size_t *size) sub_size = ied_size; break; default: + *start = 0; + *size = 0; return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; - return 0; } @@ -184,7 +183,7 @@ static size_t calculate_reserved_mem_size(uintptr_t dram_base, size_t reserve_mem_size; const struct soc_intel_cannonlake_config *config; - config = dev->chip_info; + config = config_of(dev); /* Get PRMRR size */ reserve_mem_base -= get_prmrr_size(reserve_mem_base, config); diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index 8eb81b0b40..0e7cc17b4a 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -32,37 +32,19 @@ * Set which power state system will be after reapplying * the power (from G3 State) */ -void pmc_set_afterg3(int s5pwr) +void pmc_soc_set_afterg3_en(const bool on) { uint8_t reg8; - uint8_t *pmcbase = pmc_mmio_regs(); + uint8_t *const pmcbase = pmc_mmio_regs(); reg8 = read8(pmcbase + GEN_PMCON_A); - - switch (s5pwr) { - case MAINBOARD_POWER_STATE_OFF: - reg8 |= 1; - break; - case MAINBOARD_POWER_STATE_ON: - reg8 &= ~1; - break; - case MAINBOARD_POWER_STATE_PREVIOUS: - default: - break; - } - + if (on) + reg8 &= ~SLEEP_AFTER_POWER_FAIL; + else + reg8 |= SLEEP_AFTER_POWER_FAIL; write8(pmcbase + GEN_PMCON_A, reg8); } -/* - * Set PMC register to know which state system should be after - * power reapplied - */ -void pmc_soc_restore_power_failure(void) -{ - pmc_set_afterg3(CONFIG_MAINBOARD_POWER_FAILURE_STATE); -} - static void pm1_enable_pwrbtn_smi(void *unused) { /* @@ -119,47 +101,14 @@ static void config_deep_sx(uint32_t deepsx_config) write32(pmcbase + DSX_CFG, reg); } -static void pch_power_options(void) -{ - const char *state; - - const int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; - - /* - * Which state do we want to goto after g3 (power restored)? - * 0 == S5 Soft Off - * 1 == S0 Full On - * 2 == Keep Previous State - */ - switch (pwr_on) { - case MAINBOARD_POWER_STATE_OFF: - state = "off"; - break; - case MAINBOARD_POWER_STATE_ON: - state = "on"; - break; - case MAINBOARD_POWER_STATE_PREVIOUS: - state = "state keep"; - break; - default: - state = "undefined"; - } - pmc_set_afterg3(pwr_on); - printk(BIOS_INFO, "Set power %s after power failure.\n", state); - - /* Set up GPE configuration. */ - pmc_gpe_init(); -} - static void pmc_init(void *unused) { - struct device *dev = SA_DEV_ROOT; - config_t *config = dev->chip_info; + const config_t *config = config_of_path(SA_DEVFN_ROOT); rtc_init(); - /* Initialize power management */ - pch_power_options(); + pmc_set_power_failure_state(true); + pmc_gpe_init(); config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 9997d164e4..1626e300d8 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -175,14 +175,7 @@ uintptr_t soc_read_pmc_base(void) void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_cannonlake_config *config; - - /* Look up the device in devicetree */ - DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC); - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); - return; - } - config = dev->chip_info; + config = config_of_path(SA_DEVFN_ROOT); /* Assign to out variable */ *dw0 = config->gpe0_dw0; diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index eb71f5dac5..3ba997df48 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -103,7 +103,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); const struct device *smbus = pcidev_path_on_root(PCH_DEVFN_SMBUS); assert(dev != NULL); - const config_t *config = dev->chip_info; + const config_t *config = config_of(dev); FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig; diff --git a/src/soc/intel/cannonlake/sd.c b/src/soc/intel/cannonlake/sd.c index 2c0298fd78..b69cd1a32d 100644 --- a/src/soc/intel/cannonlake/sd.c +++ b/src/soc/intel/cannonlake/sd.c @@ -18,7 +18,7 @@ int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, struct device *dev) { - config_t *config = dev->chip_info; + config_t *config = config_of(dev); if (!config->sdcard_cd_gpio) return -1; diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index cc5a7dd8ec..b8ceec0f1d 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -78,15 +78,8 @@ static void pch_disable_heci(void) void smihandler_soc_at_finalize(void) { const struct soc_intel_cannonlake_config *config; - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_CSE); - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", - __func__); - return ; - } - - config = dev->chip_info; + config = config_of_path(PCH_DEVFN_CSE); if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) pch_disable_heci(); diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 47efa18c6c..9a23d5a8f9 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -171,14 +171,9 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, write_smrr(relo_params); } -static void fill_in_relocation_params(struct device *dev, - struct smm_relocation_params *params) +static void fill_in_relocation_params(struct smm_relocation_params *params) { - void *handler_base; - size_t handler_size; - void *ied_base; - size_t ied_size; - void *tseg_base; + uintptr_t tseg_base; size_t tseg_size; u32 emrr_base; u32 emrr_size; @@ -193,20 +188,12 @@ static void fill_in_relocation_params(struct device *dev, phys_bits = cpu_phys_address_size(); smm_region(&tseg_base, &tseg_size); - smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); - smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size); - - params->smram_size = handler_size; - params->smram_base = (uintptr_t)handler_base; - - params->ied_base = (uintptr_t)ied_base; - params->ied_size = ied_size; + smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) - | MTRR_PHYS_MASK_VALID; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; params->smrr_mask.hi = 0; /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */ @@ -243,8 +230,8 @@ static void setup_ied_area(struct smm_relocation_params *params) ied_base = (void *)params->ied_base; - printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base); - printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size); + printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32)params->ied_base); + printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32)params->ied_size); /* Place IED header at IEDBASE. */ memcpy(ied_base, &ied, sizeof(ied)); @@ -256,17 +243,15 @@ static void setup_ied_area(struct smm_relocation_params *params) void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - struct device *dev = SA_DEV_ROOT; - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - fill_in_relocation_params(dev, &smm_reloc_params); + fill_in_relocation_params(&smm_reloc_params); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); if (smm_reloc_params.ied_size) setup_ied_area(&smm_reloc_params); - *perm_smbase = smm_reloc_params.smram_base; - *perm_smsize = smm_reloc_params.smram_size; *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); } @@ -301,11 +286,12 @@ void smm_relocate(void) void smm_lock(void) { + struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); /* * LOCK the SMM memory window and enable normal SMM. * After running this function, only a full reset can * make the SMM registers writable again. */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); + pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c index 7174a9a58f..ae19acc264 100644 --- a/src/soc/intel/cannonlake/uart.c +++ b/src/soc/intel/cannonlake/uart.c @@ -50,7 +50,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); -struct device *soc_uart_console_to_device(int uart_console) +DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) { /* * if index is valid, this function will return corresponding structure @@ -58,11 +58,11 @@ struct device *soc_uart_console_to_device(int uart_console) */ switch (uart_console) { case 0: - return (struct device *)PCH_DEV_UART0; + return pcidev_path_on_root(PCH_DEVFN_UART0); case 1: - return (struct device *)PCH_DEV_UART1; + return pcidev_path_on_root(PCH_DEVFN_UART1); case 2: - return (struct device *)PCH_DEV_UART2; + return pcidev_path_on_root(PCH_DEVFN_UART2); default: printk(BIOS_ERR, "Invalid UART console index\n"); return NULL; diff --git a/src/soc/intel/cannonlake/xhci.c b/src/soc/intel/cannonlake/xhci.c new file mode 100644 index 0000000000..2741883d88 --- /dev/null +++ b/src/soc/intel/cannonlake/xhci.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#define XHCI_USB3_PORT_STATUS_REG 0x580 +#define XHCI_USB2_PORT_NUM 14 +#define XHCI_USB3_PORT_NUM 10 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + +const struct xhci_usb_info *soc_get_xhci_usb_info(void) +{ + return &usb_info; +} diff --git a/src/soc/intel/common/block/chip/chip.c b/src/soc/intel/common/block/chip/chip.c index eed1ada0e8..9e74803e1a 100644 --- a/src/soc/intel/common/block/chip/chip.c +++ b/src/soc/intel/common/block/chip/chip.c @@ -21,13 +21,8 @@ const struct soc_intel_common_config *chip_get_common_soc_structure(void) { const struct soc_intel_common_config *soc_config; const config_t *config; - int devfn = SA_DEVFN_ROOT; - const struct device *dev = pcidev_path_on_root(devfn); - if (!dev || !dev->chip_info) - die("Could not find SA_DEV_ROOT devicetree config!\n"); - - config = dev->chip_info; + config = config_of_path(SA_DEVFN_ROOT); soc_config = &config->common_soc_config; return soc_config; diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index e98b5dd615..d941ab28bb 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -74,7 +74,10 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_V0 }, { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_W0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_U0 }, + { X86_VENDOR_INTEL, CPUID_COFFEELAKE_B0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_D0 }, + { X86_VENDOR_INTEL, CPUID_COFFEELAKE_P0 }, + { X86_VENDOR_INTEL, CPUID_COFFEELAKE_R0 }, { X86_VENDOR_INTEL, CPUID_ICELAKE_A0 }, { X86_VENDOR_INTEL, CPUID_ICELAKE_B0 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_U_A0 }, diff --git a/src/soc/intel/common/block/fast_spi/Makefile.inc b/src/soc/intel/common/block/fast_spi/Makefile.inc index 9c75f3bc46..e5b50aa0bf 100644 --- a/src/soc/intel/common/block/fast_spi/Makefile.inc +++ b/src/soc/intel/common/block/fast_spi/Makefile.inc @@ -13,8 +13,8 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi_flash.c postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi.c postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi_flash.c -ifeq ($(CONFIG_SPI_FLASH_SMM),y) smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi.c +ifeq ($(CONFIG_SPI_FLASH_SMM),y) smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi_flash.c endif diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index e4ccccb013..2b4c4a74db 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -56,7 +56,7 @@ static uintptr_t graphics_get_bar(struct device *dev, unsigned long index) uintptr_t graphics_get_memory_base(void) { uintptr_t memory_base; - struct device *dev = SA_DEV_IGD; + struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); if (is_graphics_disabled(dev)) return 0; @@ -75,7 +75,7 @@ uintptr_t graphics_get_memory_base(void) static uintptr_t graphics_get_gtt_base(void) { static uintptr_t gtt_base; - struct device *dev = SA_DEV_IGD; + struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); if (is_graphics_disabled(dev)) die("IGD is disabled!"); @@ -150,8 +150,11 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM, PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM, PCI_DEVICE_ID_INTEL_CFL_H_GT2, - PCI_DEVICE_ID_INTEL_CFL_S_GT2, PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2, + PCI_DEVICE_ID_INTEL_CFL_S_GT2_1, + PCI_DEVICE_ID_INTEL_CFL_S_GT2_2, + PCI_DEVICE_ID_INTEL_CFL_S_GT2_3, + PCI_DEVICE_ID_INTEL_CFL_S_GT2_4, PCI_DEVICE_ID_INTEL_ICL_GT0_ULT, PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT, PCI_DEVICE_ID_INTEL_ICL_GT1_ULT, diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 17532bf6db..f937bd6eed 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -446,8 +447,10 @@ static uint32_t gspi_get_clk_div(unsigned int gspi_bus) static int gspi_ctrlr_setup(const struct spi_slave *dev) { struct spi_cfg cfg; + int devfn; uint32_t cs_ctrl, sscr0, sscr1, clocks, sitf, sirf, pol; struct gspi_ctrlr_params params, *p = ¶ms; + const struct device *device; /* Only chip select 0 is supported. */ if (dev->cs != 0) { @@ -466,6 +469,16 @@ static int gspi_ctrlr_setup(const struct spi_slave *dev) return -1; } + devfn = gspi_soc_bus_to_devfn(p->gspi_bus); + /* + * devfn is already validated as part of gspi_ctrlr_params_init. + * No need to revalidate it again. + */ + device = pcidev_path_on_root(devfn); + + /* Ensure controller is in D0 state */ + lpss_set_power_state(device, STATE_D0); + /* Take controller out of reset, keeping DMA in reset. */ gspi_write_mmio_reg(p, RESETS, CTRLR_ACTIVE | DMA_RESET); diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index d551c51abf..854a61a884 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -87,6 +87,9 @@ static int lpss_i2c_early_init_bus(unsigned int bus) /* Take device out of reset */ lpss_reset_release(base); + /* Ensure controller is in D0 state */ + lpss_set_power_state(tree_dev, STATE_D0); + /* Initialize the controller */ if (dw_i2c_init(bus, config) < 0) { printk(BIOS_ERR, "I2C%u failed to initialize\n", bus); @@ -162,6 +165,9 @@ static void dw_i2c_device_init(struct device *dev) if (!base_address) return; + /* Ensure controller is in D0 state */ + lpss_set_power_state(dev, STATE_D0); + /* Take device out of reset if its not done before */ if (lpss_is_controller_in_reset(base_address)) lpss_reset_release(base_address); diff --git a/src/soc/intel/common/block/include/intelblocks/chip.h b/src/soc/intel/common/block/include/intelblocks/chip.h index 555bdaa893..9fe165e5b1 100644 --- a/src/soc/intel/common/block/include/intelblocks/chip.h +++ b/src/soc/intel/common/block/include/intelblocks/chip.h @@ -33,6 +33,8 @@ struct soc_intel_common_config { int chipset_lockdown; struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; struct dw_i2c_bus_config i2c[CONFIG_SOC_INTEL_I2C_DEV_MAX]; + /* PCH Thermal Trip Temperature in deg C */ + uint8_t pch_thermal_trip; }; /* This function to retrieve soc config structure required by common code */ diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index e1ddd4babb..744095207d 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -134,6 +134,15 @@ #define PAD_RESET(value) PAD_CFG0_LOGICAL_RESET_##value #define PAD_PULL(value) PAD_CFG1_PULL_##value +/* Disable the input/output buffer of the pad */ +#define PAD_CFG0_BUF_NO_DISABLE (0) +#define PAD_CFG0_BUF_TX_DISABLE PAD_CFG0_TX_DISABLE +#define PAD_CFG0_BUF_RX_DISABLE PAD_CFG0_RX_DISABLE +#define PAD_CFG0_BUF_TX_RX_DISABLE \ + (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE) + +#define PAD_BUF(value) PAD_CFG0_BUF_##value + #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY) #define PAD_IOSSTATE(value) PAD_CFG1_IOSSTATE_##value #define PAD_IOSTERM(value) PAD_CFG1_IOSTERM_##value @@ -180,6 +189,15 @@ _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ PAD_IOSSTATE(TxLASTRxE)) +/* + * Set native function with RX Level/Edge configuration and disable + * input/output buffer if necessary + */ +#define PAD_CFG_NF_BUF_TRIG(pad, pull, rst, func, bufdis, trig) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_CFG0_TRIG_##trig | \ + PAD_BUF(bufdis) | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) + #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) /* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S Not applicable to all SOCs. Refer EDS @@ -209,25 +227,29 @@ /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO(pad, val, rst) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE)) /* General purpose output, with termination specified */ #define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_GPIO_DRIVER) /* General purpose output. */ #define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm)) /* General purpose input */ diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h index eb38f13a71..e80f3ddec5 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpss.h +++ b/src/soc/intel/common/block/include/intelblocks/lpss.h @@ -16,8 +16,15 @@ #ifndef SOC_INTEL_COMMON_BLOCK_LPSS_H #define SOC_INTEL_COMMON_BLOCK_LPSS_H +#include #include +/* D0 and D3 enable config */ +enum lpss_pwr_state { + STATE_D0 = 0, + STATE_D3 = 3 +}; + /* Gets controller out of reset */ void lpss_reset_release(uintptr_t base); @@ -30,4 +37,16 @@ void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val); /* Check if controller is in reset. */ bool lpss_is_controller_in_reset(uintptr_t base); +/* Set controller power state to D0 or D3*/ +void lpss_set_power_state(const struct device *dev, enum lpss_pwr_state state); + +/* + * Handler to get list of LPSS controllers. The SOC is expected to send out a + * list of pci devfn for all LPSS controllers supported by the SOC. + */ +const pci_devfn_t *soc_lpss_controllers_list(size_t *size); + +/* Check if the device is a LPSS controller */ +bool is_dev_lpss(const struct device *dev); + #endif /* SOC_INTEL_COMMON_BLOCK_LPSS_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 0f37a64345..5ef7641a3a 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -42,7 +42,9 @@ #define CPUID_WHISKEYLAKE_W0 0x806eb #define CPUID_COFFEELAKE_D0 0x806ea #define CPUID_COFFEELAKE_U0 0x906ea - +#define CPUID_COFFEELAKE_B0 0x906eb +#define CPUID_COFFEELAKE_P0 0x906ec +#define CPUID_COFFEELAKE_R0 0x906ed #define CPUID_ICELAKE_A0 0x706e0 #define CPUID_ICELAKE_B0 0x706e1 #define CPUID_COMETLAKE_U_A0 0xa0660 diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index 82eb2ae4c4..caf21f0ca6 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -16,6 +16,7 @@ #ifndef SOC_INTEL_COMMON_BLOCK_PMCLIB_H #define SOC_INTEL_COMMON_BLOCK_PMCLIB_H +#include #include /* Forward declare the power state struct here */ @@ -125,12 +126,6 @@ void pmc_clear_all_gpe_status(void); /* Clear status bits in Power and Reset Status (PRSTS) register */ void pmc_clear_prsts(void); -/* - * Set PMC register to know which state system should be after - * power reapplied - */ -void pmc_soc_restore_power_failure(void); - /* * Enable or disable global reset. If global reset is enabled, hard reset and * soft reset will trigger global reset, where both host and TXE are reset. @@ -214,4 +209,20 @@ enum { MAINBOARD_POWER_STATE_PREVIOUS, }; +/* + * Implemented by SoC code to set PMC register to know which state + * system should go into after power is reapplied. + */ +void pmc_soc_set_afterg3_en(bool on); +/* + * Configure power state to go into when power is reapplied. + * + * To be called by SoC code once during boot and will be called by + * the "sleep" SMI handler when going into S5. + * + * `target_on` signifies that we are currently powering on, so that + * MAINBOARD_POWER_STATE_PREVIOUS can be handled accordingly. + */ +void pmc_set_power_failure_state(bool target_on); + #endif /* SOC_INTEL_COMMON_BLOCK_PMCLIB_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/smm.h b/src/soc/intel/common/block/include/intelblocks/smm.h index c04ec46800..25ff8f4ec9 100644 --- a/src/soc/intel/common/block/include/intelblocks/smm.h +++ b/src/soc/intel/common/block/include/intelblocks/smm.h @@ -32,7 +32,5 @@ */ void smm_southbridge_clear_state(void); void smm_southbridge_enable(uint16_t pm1_events); -/* API to get SMM region start and size based on Host Bridge register */ -void smm_region_info(void **start, size_t *size); #endif diff --git a/src/soc/intel/skylake/include/soc/thermal.h b/src/soc/intel/common/block/include/intelblocks/thermal.h similarity index 82% rename from src/soc/intel/skylake/include/soc/thermal.h rename to src/soc/intel/common/block/include/intelblocks/thermal.h index 31c47c6361..ab18eb6d1d 100644 --- a/src/soc/intel/skylake/include/soc/thermal.h +++ b/src/soc/intel/common/block/include/intelblocks/thermal.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. + * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,10 +13,8 @@ * GNU General Public License for more details. */ -#ifndef _SOC_THERMAL_H_ -#define _SOC_THERMAL_H_ - -#define THERMAL_SENSOR_POWER_MANAGEMENT 0x1c +#ifndef _SOC_INTEL_COMMON_BLOCK_THERMAL_H_ +#define _SOC_INTEL_COMMON_BLOCK_THERMAL_H_ /* Enable thermal sensor power management */ void pch_thermal_configuration(void); diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h index 55f259db7c..1b62421d2b 100644 --- a/src/soc/intel/common/block/include/intelblocks/uart.h +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -40,7 +40,7 @@ struct uart_gpio_pad_config { * Common routine to initialize UART controller PCI config space, take it out of * reset and configure M/N dividers. */ -void uart_common_init(struct device *dev, uintptr_t baseaddr); +void uart_common_init(const struct device *dev, uintptr_t baseaddr); /* * Check if UART debug controller is initialized @@ -72,7 +72,7 @@ void uart_bootblock_init(void); * Pointer to device structure = If device has a UART debug controller. * NULL = otherwise */ -struct device *uart_get_device(void); +const struct device *uart_get_device(void); /**************************** SoC callbacks ***********************************/ @@ -89,6 +89,6 @@ struct device *uart_get_device(void); * Pointer to device structure = If device has a UART debug controller. * NULL = otherwise */ -struct device *soc_uart_console_to_device(int uart_console); +DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console); #endif /* SOC_INTEL_COMMON_BLOCK_UART_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/xhci.h b/src/soc/intel/common/block/include/intelblocks/xhci.h index 86b598fda1..dd95bfb024 100644 --- a/src/soc/intel/common/block/include/intelblocks/xhci.h +++ b/src/soc/intel/common/block/include/intelblocks/xhci.h @@ -46,4 +46,31 @@ bool pch_xhci_update_wake_event(const struct xhci_usb_info *info); void soc_xhci_init(struct device *dev); +/** + * soc_get_xhci_usb_info() - Get the information about USB2 & USB3 ports. + * + * This function is used to get USB ports and status register offset information + * within a XHCI controller. + * + * Return: USB ports and status register offset info for the SoC. + */ +const struct xhci_usb_info *soc_get_xhci_usb_info(void); + +/** + * usb_xhci_disable_unused() - Disable unused USB devices + * @ext_usb_xhci_en_cb: Callback function to be invoked, supplied by mainboard, + * to identify the status of externally visible USB ports. + * (Return true if port is present, false if port is absent) + * + * This function is used to disable unused USB devices/ports that are configured + * in the device tree. For the internal USB ports, the connect status of the port + * is probed from the XHCI controller block and the port is disabled if it is not + * connected. For the external USB ports, the mainboard provides the connect status + * of the concerned port depending on the variants and their SKUs. If the mainboard + * supplied callback function is NULL, then all the externally visible USB devices + * in the device tree are enabled. + */ +void usb_xhci_disable_unused(bool (*ext_usb_xhci_en_cb)(unsigned int port_type, + unsigned int port_id)); + #endif /* SOC_INTEL_COMMON_BLOCK_XHCI_H */ diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 43ac8444a9..d7917d6262 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -124,16 +124,17 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE, PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM, PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM, - PCI_DEVICE_ID_INTEL_SPT_H_CM236, - PCI_DEVICE_ID_INTEL_SPT_H_C236, - PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM, PCI_DEVICE_ID_INTEL_SPT_H_H110, PCI_DEVICE_ID_INTEL_SPT_H_H170, PCI_DEVICE_ID_INTEL_SPT_H_Z170, PCI_DEVICE_ID_INTEL_SPT_H_Q170, PCI_DEVICE_ID_INTEL_SPT_H_Q150, PCI_DEVICE_ID_INTEL_SPT_H_B150, + PCI_DEVICE_ID_INTEL_SPT_H_C236, + PCI_DEVICE_ID_INTEL_SPT_H_C232, PCI_DEVICE_ID_INTEL_SPT_H_QM170, + PCI_DEVICE_ID_INTEL_SPT_H_HM170, + PCI_DEVICE_ID_INTEL_SPT_H_CM236, PCI_DEVICE_ID_INTEL_SPT_H_HM175, PCI_DEVICE_ID_INTEL_SPT_H_QM175, PCI_DEVICE_ID_INTEL_SPT_H_CM238, @@ -154,8 +155,15 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC, PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC, PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, + PCI_DEVICE_ID_INTEL_CNP_H_LPC_H310, + PCI_DEVICE_ID_INTEL_CNP_H_LPC_H370, + PCI_DEVICE_ID_INTEL_CNP_H_LPC_Z390, PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, + PCI_DEVICE_ID_INTEL_CNP_H_LPC_B360, + PCI_DEVICE_ID_INTEL_CNP_H_LPC_C246, + PCI_DEVICE_ID_INTEL_CNP_H_LPC_C242, PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, + PCI_DEVICE_ID_INTEL_CNP_H_LPC_HM370, PCI_DEVICE_ID_INTEL_CNP_H_LPC_CM246, PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI, PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI, diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 975e4300bf..bc89e4ccae 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -270,7 +270,7 @@ static void pch_lpc_interrupt_init(void) const struct device *dev; dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0); - if (!dev || !dev->chip_info) + if (!dev) return; soc_pch_pirq_init(dev); @@ -283,7 +283,7 @@ void pch_enable_lpc(void) uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]; dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0); - if (!dev || !dev->chip_info) + if (!dev) return; soc_get_gen_io_dec_range(dev, gen_io_dec); diff --git a/src/soc/intel/common/block/lpss/lpss.c b/src/soc/intel/common/block/lpss/lpss.c index 6b6d17b106..1722dcde08 100644 --- a/src/soc/intel/common/block/lpss/lpss.c +++ b/src/soc/intel/common/block/lpss/lpss.c @@ -14,6 +14,8 @@ */ #include +#include +#include #include /* Clock register */ @@ -39,6 +41,11 @@ /* DMA Software Reset Control */ #define LPSS_DMA_RST_RELEASE (1 << 2) +/* Power management control and status register */ +#define PME_CTRL_STATUS 0x84 +/* Bit 1:0 Powerstate, controls D0 and D3 state */ +#define POWER_STATE_MASK 3 + bool lpss_is_controller_in_reset(uintptr_t base) { uint8_t *addr = (void *)base; @@ -69,3 +76,34 @@ void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val) write32(addr, clk_sel); } + +/* Set controller power state to D0 or D3 */ +void lpss_set_power_state(const struct device *dev, enum lpss_pwr_state state) +{ +#if defined(__SIMPLE_DEVICE__) + unsigned int devfn = dev->path.pci.devfn; + pci_devfn_t lpss_dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); +#else + const struct device *lpss_dev = dev; +#endif + + pci_update_config8(lpss_dev, PME_CTRL_STATUS, ~POWER_STATE_MASK, state); +} + +bool is_dev_lpss(const struct device *dev) +{ + static size_t size; + static const pci_devfn_t *lpss_devices; + + if (dev->path.type != DEVICE_PATH_PCI) + return false; + + if (!lpss_devices) + lpss_devices = soc_lpss_controllers_list(&size); + + for (int i = 0; i < size; i++) { + if (lpss_devices[i] == dev->path.pci.devfn) + return true; + } + return false; +} diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 564aacb55e..d7362b6dc4 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -21,7 +21,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -79,18 +81,6 @@ __weak uint32_t soc_get_smi_status(uint32_t generic_sts) return generic_sts; } -/* - * Set PMC register to know which state system should be after - * power reapplied - */ -__weak void pmc_soc_restore_power_failure(void) -{ - /* - * SoC code should set PMC config register in order to set - * MAINBOARD_POWER_ON bit as per EDS. - */ -} - int acpi_get_sleep_type(void) { struct chipset_power_state *ps; @@ -579,3 +569,32 @@ void pmc_gpe_init(void) /* Set the routes in the GPIO communities as well. */ gpio_route_gpe(dw0, dw1, dw2); } + +void pmc_set_power_failure_state(const bool target_on) +{ + bool on; + + uint8_t state = CONFIG_MAINBOARD_POWER_FAILURE_STATE; + get_option(&state, "power_on_after_fail"); + + switch (state) { + case MAINBOARD_POWER_STATE_OFF: + printk(BIOS_INFO, "Set power off after power failure.\n"); + on = false; + break; + case MAINBOARD_POWER_STATE_ON: + printk(BIOS_INFO, "Set power on after power failure.\n"); + on = true; + break; + case MAINBOARD_POWER_STATE_PREVIOUS: + printk(BIOS_INFO, "Keep power state after power failure.\n"); + on = target_on; + break; + default: + printk(BIOS_WARNING, "WARNING: Unknown power-failure state: %d\n", state); + on = false; + break; + } + + pmc_soc_set_afterg3_en(on); +} diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 22895676e0..58026cea5f 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -221,7 +222,7 @@ void smihandler_southbridge_sleep( /* Disable all GPE */ pmc_disable_all_gpe(); /* Set which state system will be after power reapplied */ - pmc_soc_restore_power_failure(); + pmc_set_power_failure_state(false); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index a2a7c164c8..12c057b25a 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -18,23 +18,10 @@ #include #include #include -#include #include #include #include #include -#include - -#if !CONFIG(PLATFORM_USES_FSP1_1) -void stage_cache_external_region(void **base, size_t *size) -{ - if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { - printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; - *size = 0; - } -} -#endif void smm_southbridge_clear_state(void) { @@ -105,9 +92,3 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1) "d" (APM_CNT) ); } - -void smm_region_info(void **start, size_t *size) -{ - *start = (void *)sa_get_tseg_base(); - *size = sa_get_tseg_size(); -} diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 85db5cfa4a..af5087f716 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -67,6 +67,10 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNL_SPI1, PCI_DEVICE_ID_INTEL_CNL_SPI2, PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI, + PCI_DEVICE_ID_INTEL_CNP_H_SPI0, + PCI_DEVICE_ID_INTEL_CNP_H_SPI1, + PCI_DEVICE_ID_INTEL_CNP_H_SPI2, + PCI_DEVICE_ID_INTEL_CNP_H_HWSEQ_SPI, PCI_DEVICE_ID_INTEL_ICP_SPI0, PCI_DEVICE_ID_INTEL_ICP_SPI1, PCI_DEVICE_ID_INTEL_ICP_SPI2, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index a93db65af6..c9abb55490 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -344,8 +344,8 @@ static const unsigned short systemagent_ids[] = { PCI_DEVICE_ID_INTEL_SKL_ID_H_2, PCI_DEVICE_ID_INTEL_SKL_ID_S_2, PCI_DEVICE_ID_INTEL_SKL_ID_S_4, - PCI_DEVICE_ID_INTEL_WHL_ID_Wx2, - PCI_DEVICE_ID_INTEL_WHL_ID_Wx4, + PCI_DEVICE_ID_INTEL_WHL_ID_W_2, + PCI_DEVICE_ID_INTEL_WHL_ID_W_4, PCI_DEVICE_ID_INTEL_KBL_ID_S, PCI_DEVICE_ID_INTEL_SKL_ID_H_EM, PCI_DEVICE_ID_INTEL_SKL_ID_DT, @@ -357,7 +357,11 @@ static const unsigned short systemagent_ids[] = { PCI_DEVICE_ID_INTEL_KBL_ID_DT_2, PCI_DEVICE_ID_INTEL_CFL_ID_U, PCI_DEVICE_ID_INTEL_CFL_ID_H, + PCI_DEVICE_ID_INTEL_CFL_ID_H_8, PCI_DEVICE_ID_INTEL_CFL_ID_S, + PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4, + PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8, + PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8, PCI_DEVICE_ID_INTEL_ICL_ID_U, PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2, PCI_DEVICE_ID_INTEL_ICL_ID_Y, diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index c12c64ab53..8c89c07e26 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ + #include #include #include @@ -24,7 +26,6 @@ #include "systemagent_def.h" -#if ENV_BOOTBLOCK void bootblock_systemagent_early_init(void) { uint32_t reg; @@ -63,7 +64,6 @@ void bootblock_systemagent_early_init(void) */ pci_write_config32(SA_DEV_ROOT, TSEG, 0); } -#endif void sa_set_pci_bar(const struct sa_mmio_descriptor *fixed_set_resources, size_t count) diff --git a/src/soc/intel/common/block/thermal/Kconfig b/src/soc/intel/common/block/thermal/Kconfig new file mode 100644 index 0000000000..060517656e --- /dev/null +++ b/src/soc/intel/common/block/thermal/Kconfig @@ -0,0 +1,5 @@ +config SOC_INTEL_COMMON_BLOCK_THERMAL + bool + default n + help + This option allows to configure PCH thermal registers for supported PCH. diff --git a/src/soc/intel/common/block/thermal/Makefile.inc b/src/soc/intel/common/block/thermal/Makefile.inc new file mode 100644 index 0000000000..6f216b3f33 --- /dev/null +++ b/src/soc/intel/common/block/thermal/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL) += thermal.c diff --git a/src/soc/intel/common/block/thermal/thermal.c b/src/soc/intel/common/block/thermal/thermal.c new file mode 100644 index 0000000000..39a98a41d8 --- /dev/null +++ b/src/soc/intel/common/block/thermal/thermal.c @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#define THERMAL_SENSOR_POWER_MANAGEMENT 0x1c +#define CATASTROPHIC_TRIP_POINT_MASK 0x1ff +#define MAX_TRIP_TEMP 205 +/* This is the safest default Trip Temp value */ +#define DEFAULT_TRIP_TEMP 50 +#define GET_LTT_VALUE(x) (((x) + 50) * (2)) + +static uint8_t get_thermal_trip_temp(void) +{ + const struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); + + return common_config->pch_thermal_trip; +} + +/* PCH Low Temp Threshold (LTT) */ +static uint16_t pch_get_ltt_value(struct device *dev) +{ + uint16_t ltt_value; + uint8_t thermal_config; + + thermal_config = get_thermal_trip_temp(); + if (!thermal_config) + thermal_config = DEFAULT_TRIP_TEMP; + + if (thermal_config > MAX_TRIP_TEMP) + die("Input PCH temp trip is higher than allowed range!"); + + /* Trip Point Temp = (LTT / 2 - 50 degree C) */ + ltt_value = GET_LTT_VALUE(thermal_config); + + return ltt_value; +} + +/* Enable thermal sensor power management */ +void pch_thermal_configuration(void) +{ + uint16_t reg16; + uintptr_t thermalbar; + uintptr_t thermalbar_pm; + struct device *dev; + struct resource *res; + + dev = pcidev_path_on_root(PCH_DEVFN_THERMAL); + if (!dev) { + printk(BIOS_ERR, "ERROR: PCH_DEVFN_THERMAL device not found!\n"); + return; + } + + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) { + printk(BIOS_ERR, "ERROR: PCH thermal device not found!\n"); + return; + } + + /* Get the base address of the resource */ + thermalbar = res->base; + + /* Get the required thermal address to write the register value */ + thermalbar_pm = thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT; + + /* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */ + reg16 = read16((uint16_t *)thermalbar_pm); + reg16 &= ~CATASTROPHIC_TRIP_POINT_MASK; + /* Low Temp Threshold (LTT) */ + reg16 |= pch_get_ltt_value(dev); + write16((uint16_t *)thermalbar_pm, reg16); +} diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 9d820ffd7e..f556aed3d6 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -65,15 +65,13 @@ static int uart_get_valid_index(void) return UART_CONSOLE_INVALID_INDEX; } -void uart_common_init(struct device *device, uintptr_t baseaddr) +void uart_common_init(const struct device *device, uintptr_t baseaddr) { #if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = (pci_devfn_t)(uintptr_t)device; + pci_devfn_t dev = PCI_BDF(device); #else - struct device *dev = device; + const struct device *dev = device; #endif - if (!dev) - return; /* Set UART base address */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr); @@ -84,7 +82,7 @@ void uart_common_init(struct device *device, uintptr_t baseaddr) uart_lpss_init(baseaddr); } -struct device *uart_get_device(void) +const struct device *uart_get_device(void) { /* * This function will get called even if INTEL_LPSS_UART_FOR_CONSOLE @@ -105,14 +103,16 @@ struct device *uart_get_device(void) bool uart_is_controller_initialized(void) { uintptr_t base; + const struct device *dev_uart = uart_get_device(); + + if (!dev_uart) + return false; #if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = (pci_devfn_t)(uintptr_t)uart_get_device(); + pci_devfn_t dev = PCI_BDF(dev_uart); #else - struct device *dev = uart_get_device(); + const struct device *dev = dev_uart; #endif - if (!dev) - return false; base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF; if (!base) @@ -136,8 +136,15 @@ static void uart_configure_gpio_pads(void) void uart_bootblock_init(void) { + const struct device *dev_uart; + + dev_uart = uart_get_device(); + + if (!dev_uart) + return; + /* Program UART BAR0, command, reset and clock register */ - uart_common_init(uart_get_device(), CONFIG_CONSOLE_UART_BASE_ADDRESS); + uart_common_init(dev_uart, CONFIG_CONSOLE_UART_BASE_ADDRESS); /* Configure the 2 pads per UART. */ uart_configure_gpio_pads(); diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index c429e7dd58..0bdf1d97ba 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -14,11 +14,96 @@ * GNU General Public License for more details. */ +#include +#include #include #include #include +#include #include #include +#include + +#define XHCI_USB2 2 +#define XHCI_USB3 3 + +/* Current Connect Status */ +#define XHCI_STATUS_CCS (1 << 0) + +static bool is_usb_port_connected(const struct xhci_usb_info *info, + unsigned int port_type, unsigned int port_id) +{ + uintptr_t port_sts_reg; + uint32_t port_status; + const struct resource *res; + + /* Support only USB2 or USB3 ports */ + if (!(port_type == XHCI_USB2 || port_type == XHCI_USB3)) + return false; + + /* Mark out of bound port id as not connected */ + if ((port_type == XHCI_USB2 && port_id >= info->num_usb2_ports) || + (port_type == XHCI_USB3 && port_id >= info->num_usb3_ports)) + return false; + + /* Calculate port status register address and read the status */ + res = find_resource(PCH_DEV_XHCI, PCI_BASE_ADDRESS_0); + /* If the memory BAR is not allocated for XHCI, leave the devices enabled */ + if (!res) + return true; + + if (port_type == XHCI_USB2) + port_sts_reg = (uintptr_t)res->base + + info->usb2_port_status_reg + port_id * 0x10; + else + port_sts_reg = (uintptr_t)res->base + + info->usb3_port_status_reg + port_id * 0x10; + port_status = read32((void *)port_sts_reg); + + /* Ensure that the status is not all 1s */ + if (port_status == 0xffffffff) + return false; + + return !!(port_status & XHCI_STATUS_CCS); +} + +void usb_xhci_disable_unused(bool (*ext_usb_xhci_en_cb)(unsigned int port_type, + unsigned int port_id)) +{ + struct device *xhci, *hub = NULL, *port = NULL; + const struct xhci_usb_info *info = soc_get_xhci_usb_info(); + struct drivers_usb_acpi_config *config; + bool enable; + + xhci = pcidev_path_on_root(PCH_DEVFN_XHCI); + if (!xhci) { + printk(BIOS_ERR, "%s: Could not locate XHCI device in DT\n", __func__); + return; + } + + while ((hub = dev_bus_each_child(xhci->link_list, hub)) != NULL) { + while ((port = dev_bus_each_child(hub->link_list, port)) != NULL) { + enable = true; + config = config_of(port); + if (config->type == UPC_TYPE_INTERNAL) { + /* Probe the connect status of internal ports */ + enable = is_usb_port_connected(info, port->path.usb.port_type, + port->path.usb.port_id); + } else if (ext_usb_xhci_en_cb) { + /* Check the mainboard for the status of external ports */ + enable = ext_usb_xhci_en_cb(port->path.usb.port_type, + port->path.usb.port_id); + } + + if (!enable) { + printk(BIOS_INFO, "%s: Disabling USB Type%d Id%d\n", + __func__, port->path.usb.port_type, + port->path.usb.port_id); + port->enabled = 0; + } + } + } +} __weak void soc_xhci_init(struct device *dev) { /* no-op */ } diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index a832742f5e..7ece95497c 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -39,6 +39,7 @@ config PCH_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_TCO select SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS + select SOC_INTEL_COMMON_BLOCK_THERMAL select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_XDCI diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index fc1024afa7..067f59fb3a 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -125,9 +126,9 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; - void *handler_base; + uintptr_t handler_base; size_t handler_size; /* All range registers are aligned to 4KiB */ @@ -137,12 +138,12 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, smm_region(&smm_base, &smm_size); smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); - relo_attrs.smbase = (uint32_t)smm_base; + relo_attrs.smbase = smm_base; relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; - *perm_smbase = (uintptr_t)handler_base; + *perm_smbase = handler_base; *perm_smsize = handler_size; *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); } diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index 303ba67e65..a8a6283f10 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -21,16 +21,13 @@ /* All these devices live on bus 0 with the associated device and function */ -#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_##slot, 0) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_##slot, func) -#if ENV_RAMSTAGE +#if !defined(__SIMPLE_DEVICE__) #include #include -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #else -#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_##slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_##slot, func) #endif @@ -191,8 +188,10 @@ /* TODO - New added */ #define SA_DEV_SLOT_ROOT 0x00 -#define SA_DEVFN_ROOT _SA_DEVFN(ROOT) -#define SA_DEV_ROOT _SA_DEV(ROOT) +#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) +#if defined(__SIMPLE_DEVICE__) +#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) +#endif #define PCH_DEV_SLOT_LPC 0x1f #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) diff --git a/src/soc/intel/denverton_ns/include/soc/smm.h b/src/soc/intel/denverton_ns/include/soc/smm.h index 771c3d868a..a020891dd5 100644 --- a/src/soc/intel/denverton_ns/include/soc/smm.h +++ b/src/soc/intel/denverton_ns/include/soc/smm.h @@ -24,32 +24,6 @@ struct smm_relocation_attrs { uint32_t smrr_mask; }; -/* - * mmap_region_granularity must to return a size which is a positive non-zero - * integer multiple of the SMM size when SMM is in use. When not using SMM, - * this value should be set to 8 MiB. - */ -size_t mmap_region_granularity(void); - -/* Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); - -enum { - /* SMM handler area. */ - SMM_SUBREGION_HANDLER, - /* SMM cache region. */ - SMM_SUBREGION_CACHE, - /* Chipset specific area. */ - SMM_SUBREGION_CHIPSET, - /* Total sub regions supported. */ - SMM_SUBREGION_NUM, -}; - -/* Fills in the start and size for the requested SMM subregion. Returns - * 0 on success, < 0 on failure. */ -int smm_subregion(int sub, void **start, size_t *size); - #if !defined(__PRE_RAM__) && !defined(__SMM___) #include void southcluster_smm_clear_state(void); diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 25d7c9d390..5af0781422 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -90,7 +90,7 @@ static void pch_pirq_init(struct device *dev) { struct device *irq_dev; /* Get the chip configuration */ - config_t *config = dev->chip_info; + config_t *config = config_of(dev); /* Initialize PIRQ Routings */ write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQA_ROUT), diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index 514d86d5b5..9507d7f238 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -16,12 +16,12 @@ #include #include +#include #include #include #include #include #include -#include #include /* Returns base of requested region encoded in the system agent. */ @@ -30,7 +30,7 @@ static inline uintptr_t system_agent_region_base(size_t reg) #if defined(__SIMPLE_DEVICE__) pci_devfn_t dev = SA_DEV_ROOT; #else - struct device *dev = SA_DEV_ROOT; + struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); #endif /* All regions concerned for have 1 MiB alignment. */ return ALIGN_DOWN(pci_read_config32(dev, reg), 1 * MiB); @@ -70,21 +70,19 @@ static inline size_t smm_region_size(void) return system_agent_region_base(TOLUD) - smm_region_start(); } -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)smm_region_start(); + *start = smm_region_start(); *size = smm_region_size(); } -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; size_t sub_size; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - sub_base = smm_region_start(); - sub_size = smm_region_size(); - + smm_region(&sub_base, &sub_size); assert(sub_size > CONFIG_SMM_RESERVED_SIZE); switch (sub) { @@ -98,11 +96,12 @@ int smm_subregion(int sub, void **start, size_t *size) sub_size = cache_size; break; default: + *start = 0; + *size = 0; return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; - return 0; } diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 2ad78a02df..53c51f488c 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -29,7 +30,6 @@ #include #include #include -#include #include #include @@ -141,9 +141,8 @@ asmlinkage void car_stage_entry(void) struct postcar_frame pcf; uintptr_t top_of_ram; - void *smm_base; + uintptr_t smm_base; size_t smm_size; - uintptr_t tseg_base; console_init(); @@ -183,8 +182,7 @@ asmlinkage void car_stage_entry(void) */ if (CONFIG(HAVE_SMI_HANDLER)) { smm_region(&smm_base, &smm_size); - tseg_base = (uintptr_t)smm_base; - postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); } run_postcar_phase(&pcf); diff --git a/src/soc/intel/denverton_ns/sata.c b/src/soc/intel/denverton_ns/sata.c index ad62e51a68..ddb8b02192 100644 --- a/src/soc/intel/denverton_ns/sata.c +++ b/src/soc/intel/denverton_ns/sata.c @@ -34,16 +34,8 @@ static void sata_init(struct device *dev) u16 reg16; u32 abar; - /* Get the chip configuration */ - config_t *config = dev->chip_info; - printk(BIOS_DEBUG, "SATA: Initializing...\n"); - if (config == NULL) { - printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); - return; - } - /* SATA configuration is handled by the FSP */ /* Enable BARs */ diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 3a58be9afd..fa719320ee 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -17,47 +17,51 @@ ifeq ($(CONFIG_SOC_INTEL_FSP_BAYTRAIL),y) +subdirs-y += fsp subdirs-y += romstage +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/x86/cache subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc -subdirs-y += ../../../cpu/x86/cache -subdirs-y += ../../../cpu/intel/microcode -subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../lib/fsp -subdirs-y += fsp -ramstage-y += memmap.c -romstage-y += memmap.c -ramstage-y += tsc_freq.c -romstage-y += tsc_freq.c -postcar-y += tsc_freq.c -smm-y += tsc_freq.c -ramstage-y += spi.c -romstage-y += spi.c -smm-y += spi.c -ramstage-y += chip.c -ramstage-y += iosf.c -romstage-y += iosf.c -ramstage-y += northcluster.c -ramstage-y += ramstage.c -ramstage-y += gpio.c romstage-y += gpio.c +romstage-y += iosf.c +romstage-y += memmap.c romstage-y += pmutil.c -ramstage-y += pmutil.c -ramstage-y += southcluster.c -ramstage-y += cpu.c +romstage-y += spi.c +romstage-y += tsc_freq.c + +postcar-y += tsc_freq.c + ramstage-y += acpi.c +ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-y += gfx.c +ramstage-y += gpio.c +ramstage-y += i2c.c +ramstage-y += iosf.c ramstage-y += lpe.c ramstage-y += lpss.c -smm-y += pmutil.c -smm-y += smihandler.c +ramstage-y += memmap.c +ramstage-y += northcluster.c +ramstage-y += pmutil.c +ramstage-y += ramstage.c +ramstage-y += southcluster.c +ramstage-y += spi.c +ramstage-y += tsc_freq.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c +smm-y += pmutil.c +smm-y += smihandler.c +smm-y += spi.c +smm-y += tsc_freq.c + +# Remove as ramstage gets fleshed out ramstage-y += placeholders.c -ramstage-y += i2c.c -ramstage-y += gfx.c CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/include CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 371581b77a..fb941ab24b 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -177,7 +177,7 @@ void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) acpi_header_t *header = &(fadt->header); struct device *lpcdev = pcidev_path_on_root(FADT_SOC_LPC_DEVFN); u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0; - config_t *config = lpcdev->chip_info; + config_t *config = config_of(lpcdev); memset((void *) fadt, 0, sizeof(acpi_fadt_t)); diff --git a/src/soc/intel/fsp_baytrail/fsp/Makefile.inc b/src/soc/intel/fsp_baytrail/fsp/Makefile.inc index 09c5bc506d..024dd70855 100644 --- a/src/soc/intel/fsp_baytrail/fsp/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/fsp/Makefile.inc @@ -13,5 +13,5 @@ # GNU General Public License for more details. # -ramstage-y += chipset_fsp_util.c romstage-y += chipset_fsp_util.c +ramstage-y += chipset_fsp_util.c diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index 7e90142250..f11b206ed4 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -87,7 +87,7 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U printk(FSP_INFO_LEVEL, "Configure Default UPD Data\n"); dev = pcidev_path_on_root(SOC_DEV_FUNC); - config = dev->chip_info; + config = config_of(dev); /* Set up default verb tables - Just HDMI audio */ UpdData->AzaliaConfigPtr = (UINT32)&mAzaliaConfig; diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c index 8d4e090a40..2409eaa541 100644 --- a/src/soc/intel/fsp_baytrail/gpio.c +++ b/src/soc/intel/fsp_baytrail/gpio.c @@ -192,6 +192,10 @@ static void setup_gpio_route(const struct soc_gpio_map *sus, uint32_t route_reg = 0; int i; + /* FIXME: SCI interrupts should be routed regardlessy. */ + if (!CONFIG(HAVE_SMI_HANDLER)) + return; + for (i = 0; i < 8; i++) { /* SMI takes precedence and wake_en implies SCI. */ if (sus[i].smi) { @@ -207,9 +211,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sus, } } -#if CONFIG(HAVE_SMI_HANDLER) southcluster_smm_save_gpio_route(route_reg); -#endif } static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS], diff --git a/src/soc/intel/fsp_baytrail/lpe.c b/src/soc/intel/fsp_baytrail/lpe.c index 8373b91931..8baba3e295 100644 --- a/src/soc/intel/fsp_baytrail/lpe.c +++ b/src/soc/intel/fsp_baytrail/lpe.c @@ -91,7 +91,7 @@ static void setup_codec_clock(struct device *dev) struct soc_intel_fsp_baytrail_config *config; const char *freq_str; - config = dev->chip_info; + config = config_of(dev); switch (config->lpe_codec_clk_freq) { case 19: freq_str = "19.2"; @@ -150,7 +150,7 @@ static void lpe_stash_firmware_info(struct device *dev) static void lpe_init(struct device *dev) { - struct soc_intel_fsp_baytrail_config *config = dev->chip_info; + struct soc_intel_fsp_baytrail_config *config = config_of(dev); lpe_stash_firmware_info(dev); diff --git a/src/soc/intel/fsp_baytrail/lpss.c b/src/soc/intel/fsp_baytrail/lpss.c index d644138f4c..154a70ad19 100644 --- a/src/soc/intel/fsp_baytrail/lpss.c +++ b/src/soc/intel/fsp_baytrail/lpss.c @@ -147,7 +147,7 @@ static void i2c_disable_resets(struct device *dev) static void lpss_init(struct device *dev) { - struct soc_intel_fsp_baytrail_config *config = dev->chip_info; + struct soc_intel_fsp_baytrail_config *config = config_of(dev); int iosf_reg, nvs_index; dev_ctl_reg(dev, &iosf_reg, &nvs_index); diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index c73c12a430..52f16d3ade 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -1,44 +1,47 @@ ifeq ($(CONFIG_SOC_INTEL_FSP_BROADWELL_DE),y) +subdirs-y += fsp subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/x86/cache subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc -subdirs-y += ../../../cpu/x86/cache subdirs-y += ../../../lib/fsp -subdirs-y += fsp romstage-y += gpio.c -ramstage-y += cpu.c -ramstage-y += chip.c -ramstage-y += northcluster.c -ramstage-y += ramstage.c -ramstage-y += tsc_freq.c romstage-y += memmap.c -ramstage-y += memmap.c -ramstage-y += southcluster.c -ramstage-y += acpi.c -ramstage-y += smbus_common.c -ramstage-y += smbus.c romstage-y += tsc_freq.c + postcar-y += tsc_freq.c -ramstage-y += smi.c + +ramstage-y += acpi.c +ramstage-y += chip.c +ramstage-y += cpu.c ramstage-y += gpio.c ramstage-y += iou_complto.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c +ramstage-y += memmap.c +ramstage-y += northcluster.c +ramstage-y += ramstage.c +ramstage-y += smbus.c +ramstage-y += smbus_common.c +ramstage-y += smi.c +ramstage-y += southcluster.c +ramstage-y += tsc_freq.c ramstage-y += vtd.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c + smm-y += pmutil.c smm-y += smihandler.c smm-y += tsc_freq.c +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-56-*) + CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/include CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/fsp CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/ -cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-56-*) - endif # ifeq ($(CONFIG_SOC_INTEL_FSP_BROADWELL_DE),y) diff --git a/src/soc/intel/fsp_broadwell_de/iou_complto.c b/src/soc/intel/fsp_broadwell_de/iou_complto.c index dcc307174f..f998d97547 100644 --- a/src/soc/intel/fsp_broadwell_de/iou_complto.c +++ b/src/soc/intel/fsp_broadwell_de/iou_complto.c @@ -17,12 +17,14 @@ #include #include #include +#include #define DEVCTL2 0xb8 static void iou_init(struct device *dev) { - const config_t *config = dev->chip_info; + /* Use config from device always present in static devicetree. */ + const config_t *config = config_of_path(SOC_DEV_FUNC); u16 devctl2; /* pcie completion timeout diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index a2261a0457..7931018021 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -16,7 +16,6 @@ config CPU_SPECIFIC_OPTIONS select BOOT_DEVICE_SUPPORTS_WRITES select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COMMON_FADT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_M_XIP @@ -172,8 +171,7 @@ config CBFS_SIZE choice prompt "Cache-as-ram implementation" - default USE_ICELAKE_CAR_NEM_ENHANCED if MAINBOARD_HAS_CHROMEOS - default USE_ICELAKE_FSP_CAR + default USE_ICELAKE_CAR_NEM_ENHANCED help This option allows you to select how cache-as-ram (CAR) is set up. @@ -206,4 +204,15 @@ config FSP_FD_PATH depends on FSP_USE_REPO default "3rdparty/fsp/IceLakeFspBinPkg/Fsp.fd" +config ENABLE_DISPLAY_OVER_EXT_PCIE_GFX + bool "Enable display over external PCIE GFX card" + select ALWAYS_LOAD_OPROM + help + It's possible to bring display through external graphics card over PCIE + in coreboot. This option enables graphics initialization with external + graphics card. + + Selected by mainboard that runs OpRom to perform display + initialization over attached PCIe GFX card. + endif diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index cd029343bf..15f7030ba0 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -57,6 +57,7 @@ ramstage-y += sd.c smm-y += gpio.c smm-y += p2sb.c +smm-y += pmc.c smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index ae7b344df0..c61d877d1c 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -137,8 +137,9 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) ARRAY_SIZE(cstate_set_non_s0ix))]; int *set; int i; - struct device *dev = SA_DEV_ROOT; - config_t *config = dev->chip_info; + + config_t *config = config_of_path(SA_DEVFN_ROOT); + int is_s0ix_enable = config->s0ix_enable; if (is_s0ix_enable) { @@ -158,8 +159,8 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) void soc_power_states_generation(int core_id, int cores_per_package) { - struct device *dev = SA_DEV_ROOT; - config_t *config = dev->chip_info; + config_t *config = config_of_path(SA_DEVFN_ROOT); + if (config->eist_enable) /* Generate P-state tables */ generate_p_state_entries(core_id, cores_per_package); @@ -168,8 +169,8 @@ void soc_power_states_generation(int core_id, int cores_per_package) void soc_fill_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; - const struct device *dev = pcidev_on_root(0, 0); - const struct soc_intel_icelake_config *config = dev->chip_info; + + config_t *config = config_of_path(SA_DEVFN_ROOT); if (!config->PmTimerDisabled) { fadt->pm_tmr_blk = pmbase + PM1_TMR; @@ -193,8 +194,7 @@ uint32_t soc_read_sci_irq_select(void) void acpi_create_gnvs(struct global_nvs_t *gnvs) { - const struct device *dev = pcidev_on_root(0, 0); - const struct soc_intel_icelake_config *config = dev->chip_info; + config_t *config = config_of_path(SA_DEVFN_ROOT); /* Set unknown wake source */ gnvs->pm1i = -1; diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index ceef266c06..c4abb0c3f7 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -107,12 +107,7 @@ const char *soc_acpi_name(const struct device *dev) static void soc_fill_gpio_pm_configuration(void) { uint8_t value[TOTAL_GPIO_COMM]; - const struct device *dev; - dev = pcidev_on_root(SA_DEV_SLOT_ROOT, 0); - if (!dev || !dev->chip_info) - return; - - const config_t *config = dev->chip_info; + const config_t *config = config_of_path(SA_DEVFN_ROOT); if (config->gpio_override_pm) memcpy(value, config->gpio_pm, sizeof(uint8_t) * diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 67d41d79fd..cf92cd9c3f 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -40,8 +40,7 @@ static void soc_fsp_load(void) static void configure_isst(void) { - struct device *dev = SA_DEV_ROOT; - config_t *conf = dev->chip_info; + config_t *conf = config_of_path(SA_DEVFN_ROOT); msr_t msr; if (conf->speed_shift_enable) { @@ -66,10 +65,10 @@ static void configure_isst(void) static void configure_misc(void) { - struct device *dev = SA_DEV_ROOT; - config_t *conf = dev->chip_info; msr_t msr; + config_t *conf = config_of_path(SA_DEVFN_ROOT); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index a98821c903..efde625d60 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -48,7 +48,7 @@ const struct lpc_mmio_range *soc_get_fixed_mmio_ranges() void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) { - const config_t *config = dev->chip_info; + const config_t *config = config_of(dev); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index e035c958df..086787d9df 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -54,7 +55,6 @@ static void pch_handle_sideband(config_t *config) static void pch_finalize(void) { - struct device *dev; uint32_t reg32; uint8_t *pmcbase; config_t *config; @@ -63,6 +63,15 @@ static void pch_finalize(void) /* TCO Lock down */ tco_lockdown(); + /* + * Set low maximum temp threshold value used for dynamic thermal sensor + * shutdown consideration. + * + * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the + * thermal sensor when CPU is in a C-state and DTS Temp <= LTT. + */ + pch_thermal_configuration(); + /* * Disable ACPI PM timer based on dt policy * @@ -74,8 +83,7 @@ static void pch_finalize(void) * point and hence removed from the root bus. pcidev_path_on_root thus * returns NULL for PCH_DEV_PMC device. */ - dev = SA_DEV_ROOT; - config = dev->chip_info; + config = config_of_path(SA_DEVFN_ROOT); pmcbase = pmc_mmio_regs(); if (config->PmTimerDisabled) { reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 382b1843f4..e31e47bf57 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -29,13 +30,8 @@ static void parse_devicetree(FSP_S_CONFIG *params) { - struct device *dev = pcidev_on_root(0, 0); - if (!dev) { - printk(BIOS_ERR, "Could not find root device\n"); - return; - } - - const struct soc_intel_icelake_config *config = dev->chip_info; + const struct soc_intel_icelake_config *config; + config = config_of_path(SA_DEVFN_ROOT); for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; @@ -50,13 +46,30 @@ static void parse_devicetree(FSP_S_CONFIG *params) params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; } +static const pci_devfn_t serial_io_dev[] = { + PCH_DEVFN_I2C0, + PCH_DEVFN_I2C1, + PCH_DEVFN_I2C2, + PCH_DEVFN_I2C3, + PCH_DEVFN_I2C4, + PCH_DEVFN_I2C5, + PCH_DEVFN_GSPI0, + PCH_DEVFN_GSPI1, + PCH_DEVFN_GSPI2, + PCH_DEVFN_UART0, + PCH_DEVFN_UART1, + PCH_DEVFN_UART2 +}; + /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { int i; FSP_S_CONFIG *params = &supd->FspsConfig; - struct device *dev = SA_DEV_ROOT; - config_t *config = dev->chip_info; + + struct device *dev; + struct soc_intel_icelake_config *config; + config = config_of_path(SA_DEVFN_ROOT); /* Parse device tree and enable/disable devices */ parse_devicetree(params); @@ -232,3 +245,10 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } + +/* Return list of SOC LPSS controllers */ +const pci_devfn_t *soc_lpss_controllers_list(size_t *size) +{ + *size = ARRAY_SIZE(serial_io_dev); + return serial_io_dev; +} diff --git a/src/soc/intel/icelake/include/soc/pci_devs.h b/src/soc/intel/icelake/include/soc/pci_devs.h index 1348f23b78..e18fdaed99 100644 --- a/src/soc/intel/icelake/include/soc/pci_devs.h +++ b/src/soc/intel/icelake/include/soc/pci_devs.h @@ -18,31 +18,30 @@ #include -#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) #if !defined(__SIMPLE_DEVICE__) #include -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #else -#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) #endif /* System Agent Devices */ #define SA_DEV_SLOT_ROOT 0x00 -#define SA_DEVFN_ROOT _SA_DEVFN(ROOT) -#define SA_DEV_ROOT _SA_DEV(ROOT) +#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) +#if defined(__SIMPLE_DEVICE__) +#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) +#endif #define SA_DEV_SLOT_IGD 0x02 -#define SA_DEVFN_IGD _SA_DEVFN(IGD) -#define SA_DEV_IGD _SA_DEV(IGD) +#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) +#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) #define SA_DEV_SLOT_DSP 0x04 -#define SA_DEVFN_DSP _SA_DEVFN(DSP) -#define SA_DEV_DSP _SA_DEV(DSP) +#define SA_DEVFN_DSP PCI_DEVFN(SA_DEV_SLOT_DSP, 0) +#define SA_DEV_DSP PCI_DEV(0, SA_DEV_SLOT_DSP, 0) /* PCH Devices */ #define PCH_DEV_SLOT_THERMAL 0x12 diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h index 991c593f72..2d4adf7e8c 100644 --- a/src/soc/intel/icelake/include/soc/smm.h +++ b/src/soc/intel/icelake/include/soc/smm.h @@ -18,7 +18,7 @@ #include #include -#include +#include #include struct ied_header { @@ -28,10 +28,8 @@ struct ied_header { } __packed; struct smm_relocation_params { - u32 smram_base; - u32 smram_size; - u32 ied_base; - u32 ied_size; + uintptr_t ied_base; + size_t ied_size; msr_t smrr_base; msr_t smrr_mask; msr_t emrr_base; diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 67f71da28a..13eb947935 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -27,9 +27,9 @@ #include #include -void smm_region(void **start, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - *start = (void *)sa_get_tseg_base(); + *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } @@ -44,16 +44,14 @@ void smm_region(void **start, size_t *size) * | (TSEG) | * +-------------------------+ TSEG */ -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; size_t sub_size; - void *smm_base; const size_t ied_size = CONFIG_IED_REGION_SIZE; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - smm_region(&smm_base, &sub_size); - sub_base = (uintptr_t)smm_base; + smm_region(&sub_base, &sub_size); switch (sub) { case SMM_SUBREGION_HANDLER: @@ -72,12 +70,13 @@ int smm_subregion(int sub, void **start, size_t *size) sub_size = ied_size; break; default: + *start = 0; + *size = 0; return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; - return 0; } @@ -166,7 +165,7 @@ static size_t calculate_reserved_mem_size(uintptr_t dram_base, size_t reserve_mem_size; const struct soc_intel_icelake_config *config; - config = dev->chip_info; + config = config_of(dev); /* Get PRMRR size */ reserve_mem_base -= get_prmrr_size(reserve_mem_base, config); diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c index d98c83ecdb..1889c4b82a 100644 --- a/src/soc/intel/icelake/pmc.c +++ b/src/soc/intel/icelake/pmc.c @@ -29,37 +29,19 @@ * Set which power state system will be after reapplying * the power (from G3 State) */ -static void pmc_set_afterg3(int s5pwr) +void pmc_soc_set_afterg3_en(const bool on) { uint8_t reg8; - uint8_t *pmcbase = pmc_mmio_regs(); + uint8_t *const pmcbase = pmc_mmio_regs(); reg8 = read8(pmcbase + GEN_PMCON_A); - - switch (s5pwr) { - case MAINBOARD_POWER_STATE_OFF: - reg8 |= 1; - break; - case MAINBOARD_POWER_STATE_ON: - reg8 &= ~1; - break; - case MAINBOARD_POWER_STATE_PREVIOUS: - default: - break; - } - + if (on) + reg8 &= ~SLEEP_AFTER_POWER_FAIL; + else + reg8 |= SLEEP_AFTER_POWER_FAIL; write8(pmcbase + GEN_PMCON_A, reg8); } -/* - * Set PMC register to know which state system should be after - * power reapplied - */ -void pmc_soc_restore_power_failure(void) -{ - pmc_set_afterg3(CONFIG_MAINBOARD_POWER_FAILURE_STATE); -} - static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) { uint32_t reg; @@ -101,47 +83,14 @@ static void config_deep_sx(uint32_t deepsx_config) write32(pmcbase + DSX_CFG, reg); } -static void pch_power_options(void) -{ - const char *state; - - const int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; - - /* - * Which state do we want to goto after g3 (power restored)? - * 0 == S5 Soft Off - * 1 == S0 Full On - * 2 == Keep Previous State - */ - switch (pwr_on) { - case MAINBOARD_POWER_STATE_OFF: - state = "off"; - break; - case MAINBOARD_POWER_STATE_ON: - state = "on"; - break; - case MAINBOARD_POWER_STATE_PREVIOUS: - state = "state keep"; - break; - default: - state = "undefined"; - } - pmc_set_afterg3(pwr_on); - printk(BIOS_INFO, "Set power %s after power failure.\n", state); - - /* Set up GPE configuration. */ - pmc_gpe_init(); -} - static void pmc_init(void *unused) { - struct device *dev = SA_DEV_ROOT; - config_t *config = dev->chip_info; + const config_t *config = config_of_path(SA_DEVFN_ROOT); rtc_init(); - /* Initialize power management */ - pch_power_options(); + pmc_set_power_failure_state(true); + pmc_gpe_init(); pmc_set_acpi_mode(); diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 45f2a70d7c..a70840b527 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -174,13 +174,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_icelake_config *config; - /* Look up the device in devicetree */ - DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC); - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); - return; - } - config = dev->chip_info; + config = config_of_path(SA_DEVFN_ROOT); /* Assign to out variable */ *dw0 = config->gpe0_dw0; diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 89dc99a18a..a78c8a49cf 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -76,11 +76,11 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { - const struct device *dev = pcidev_on_root(0, 0); - assert(dev != NULL); - const struct soc_intel_icelake_config *config = dev->chip_info; + const struct soc_intel_icelake_config *config; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + config = config_of_path(SA_DEVFN_ROOT); + soc_memory_init_params(m_cfg, config); /* Enable SMBus controller based on config */ diff --git a/src/soc/intel/icelake/sd.c b/src/soc/intel/icelake/sd.c index 4d84bb43ff..f7c0eb3fa7 100644 --- a/src/soc/intel/icelake/sd.c +++ b/src/soc/intel/icelake/sd.c @@ -18,7 +18,7 @@ int sd_fill_soc_gpio_info(struct acpi_gpio *gpio, struct device *dev) { - config_t *config = dev->chip_info; + config_t *config = config_of(dev); if (!config->sdcard_cd_gpio) return -1; diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 3d41ee034d..8db2c3bbb4 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -75,15 +75,8 @@ static void pch_disable_heci(void) void smihandler_soc_at_finalize(void) { const struct soc_intel_icelake_config *config; - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_CSE); - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", - __func__); - return; - } - - config = dev->chip_info; + config = config_of_path(PCH_DEVFN_CSE); if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) pch_disable_heci(); diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 4e2d6840bb..edda5400c0 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -170,14 +170,9 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, write_smrr(relo_params); } -static void fill_in_relocation_params(struct device *dev, - struct smm_relocation_params *params) +static void fill_in_relocation_params(struct smm_relocation_params *params) { - void *handler_base; - size_t handler_size; - void *ied_base; - size_t ied_size; - void *tseg_base; + uintptr_t tseg_base; size_t tseg_size; u32 emrr_base; u32 emrr_size; @@ -192,20 +187,12 @@ static void fill_in_relocation_params(struct device *dev, phys_bits = cpu_phys_address_size(); smm_region(&tseg_base, &tseg_size); - smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); - smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size); - - params->smram_size = handler_size; - params->smram_base = (uintptr_t)handler_base; - - params->ied_base = (uintptr_t)ied_base; - params->ied_size = ied_size; + smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) - | MTRR_PHYS_MASK_VALID; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; params->smrr_mask.hi = 0; /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */ @@ -242,8 +229,8 @@ static void setup_ied_area(struct smm_relocation_params *params) ied_base = (void *)params->ied_base; - printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base); - printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size); + printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32)params->ied_base); + printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32)params->ied_size); /* Place IED header at IEDBASE. */ memcpy(ied_base, &ied, sizeof(ied)); @@ -255,17 +242,15 @@ static void setup_ied_area(struct smm_relocation_params *params) void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - struct device *dev = SA_DEV_ROOT; - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - fill_in_relocation_params(dev, &smm_reloc_params); + fill_in_relocation_params(&smm_reloc_params); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); if (smm_reloc_params.ied_size) setup_ied_area(&smm_reloc_params); - *perm_smbase = smm_reloc_params.smram_base; - *perm_smsize = smm_reloc_params.smram_size; *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); } @@ -300,11 +285,12 @@ void smm_relocate(void) void smm_lock(void) { + struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); /* * LOCK the SMM memory window and enable normal SMM. * After running this function, only a full reset can * make the SMM registers writable again. */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); + pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } diff --git a/src/soc/intel/icelake/uart.c b/src/soc/intel/icelake/uart.c index 7174a9a58f..ae19acc264 100644 --- a/src/soc/intel/icelake/uart.c +++ b/src/soc/intel/icelake/uart.c @@ -50,7 +50,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); -struct device *soc_uart_console_to_device(int uart_console) +DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) { /* * if index is valid, this function will return corresponding structure @@ -58,11 +58,11 @@ struct device *soc_uart_console_to_device(int uart_console) */ switch (uart_console) { case 0: - return (struct device *)PCH_DEV_UART0; + return pcidev_path_on_root(PCH_DEVFN_UART0); case 1: - return (struct device *)PCH_DEV_UART1; + return pcidev_path_on_root(PCH_DEVFN_UART1); case 2: - return (struct device *)PCH_DEV_UART2; + return pcidev_path_on_root(PCH_DEVFN_UART2); default: printk(BIOS_ERR, "Invalid UART console index\n"); return NULL; diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index a8bd26eceb..20f2ad776b 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -104,7 +104,6 @@ int fill_power_state(void) void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) { FSPM_ARCH_UPD *aupd; - const struct device *dev; const struct soc_intel_quark_config *config; void *rmu_data; size_t rmu_data_len; @@ -120,10 +119,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) "Microcode file (rmu.bin) not found."); /* Locate the configuration data from devicetree.cb */ - dev = pcidev_path_on_root(LPC_DEV_FUNC); - if (!dev) - die("ERROR - LPC device not found!"); - config = dev->chip_info; + config = config_of_path(LPC_DEV_FUNC); /* Update the architectural UPD values. */ aupd = &fspm_upd->FspmArchUpd; diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f36d5ca0f3..ca5968cf00 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -27,7 +27,6 @@ config CPU_SPECIFIC_OPTIONS select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COLLECT_TIMESTAMPS select COMMON_FADT select CPU_INTEL_COMMON @@ -118,10 +117,6 @@ config CBFS_SIZE hex default 0x200000 -config CPU_ADDR_BITS - int - default 36 - config DCACHE_RAM_BASE hex default 0xfef00000 diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 20fba29116..ef741f808b 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -64,16 +64,18 @@ ramstage-y += sd.c ramstage-y += smmrelocate.c ramstage-y += spi.c ramstage-y += systemagent.c -ramstage-y += thermal.c ramstage-y += uart.c ramstage-y += vr_config.c +ramstage-y += xhci.c smm-y += elog.c smm-y += gpio.c smm-y += p2sb.c +smm-y += pmc.c smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c +smm-y += xhci.c postcar-y += memmap.c postcar-y += gspi.c diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 910db970f6..869ca7f1ee 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -174,8 +174,7 @@ static int get_cores_per_package(void) static void acpi_create_gnvs(global_nvs_t *gnvs) { - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); - const struct soc_intel_skylake_config *config = dev->chip_info; + const struct soc_intel_skylake_config *config = config_of_path(PCH_DEVFN_LPC); /* Set unknown wake source */ gnvs->pm1i = -1; @@ -234,9 +233,8 @@ unsigned long acpi_fill_madt(unsigned long current) void acpi_fill_fadt(acpi_fadt_t *fadt) { - const struct device *dev = SA_DEV_ROOT; - const config_t *config = dev ? dev->chip_info : NULL; const uint16_t pmbase = ACPI_BASE_ADDRESS; + config_t *config = config_of_path(SA_DEVFN_ROOT); /* Use ACPI 3.0 revision */ fadt->header.revision = get_acpi_table_revision(FADT); @@ -284,7 +282,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - if (config && config->s0ix_enable) + if (config->s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; fadt->reset_reg.space_id = 1; @@ -506,8 +504,7 @@ void generate_cpu_entries(struct device *device) int totalcores = dev_count_cpu(); int cores_per_package = get_cores_per_package(); int numcpus = totalcores/cores_per_package; - struct device *dev = SA_DEV_ROOT; - config_t *config = dev->chip_info; + config_t *config = config_of_path(SA_DEVFN_ROOT); int is_s0ix_enable = config->s0ix_enable; int max_c_state; @@ -519,7 +516,7 @@ void generate_cpu_entries(struct device *device) printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package); - if (config && config->eist_enable && config->speed_shift_enable) { + if (config->eist_enable && config->speed_shift_enable) { struct cppc_config cppc_config; cpu_init_cppc_config(&cppc_config, 2 /* version 2 */); acpigen_write_CPPC_package(&cppc_config); @@ -619,11 +616,11 @@ unsigned long northbridge_write_acpi_tables(struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp) { - const struct soc_intel_skylake_config *const config = dev->chip_info; + const struct soc_intel_skylake_config *const config = config_of(dev); acpi_dmar_t *const dmar = (acpi_dmar_t *)current; /* Create DMAR table only if we have VT-d capability. */ - if ((config && config->ignore_vtd) || !soc_is_vtd_capable()) + if (config->ignore_vtd || !soc_is_vtd_capable()) return current; printk(BIOS_DEBUG, "ACPI: * DMAR\n"); @@ -695,8 +692,7 @@ void southbridge_inject_dsdt(struct device *device) /* Save wake source information for calculating ACPI _SWS values */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) { - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); - const struct soc_intel_skylake_config *config = dev->chip_info; + const struct soc_intel_skylake_config *config = config_of_path(PCH_DEVFN_LPC); struct chipset_power_state *ps; static uint32_t gpe0_sts[GPE0_REG_MAX]; uint32_t pm1_en; diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 6733f912dc..a643bbedf2 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -73,16 +73,17 @@ static struct { { PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE, "Skylake-U Base" }, { PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM, "Skylake-U Premium" }, { PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM, "Skylake-Y Premium" }, - { PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM, "Skylake PCH-H Premium" }, { PCI_DEVICE_ID_INTEL_SPT_H_H110, "Skylake PCH-H H110" }, { PCI_DEVICE_ID_INTEL_SPT_H_H170, "Skylake PCH-H H170" }, { PCI_DEVICE_ID_INTEL_SPT_H_Z170, "Skylake PCH-H Z170" }, { PCI_DEVICE_ID_INTEL_SPT_H_Q170, "Skylake PCH-H Q170" }, { PCI_DEVICE_ID_INTEL_SPT_H_Q150, "Skylake PCH-H Q150" }, { PCI_DEVICE_ID_INTEL_SPT_H_B150, "Skylake PCH-H B150" }, - { PCI_DEVICE_ID_INTEL_SPT_H_CM236, "Skylake PCH-H CM236" }, { PCI_DEVICE_ID_INTEL_SPT_H_C236, "Skylake PCH-H C236" }, + { PCI_DEVICE_ID_INTEL_SPT_H_C232, "Skylake PCH-H C232" }, { PCI_DEVICE_ID_INTEL_SPT_H_QM170, "Skylake PCH-H QM170" }, + { PCI_DEVICE_ID_INTEL_SPT_H_HM170, "Skylake PCH-H HM170" }, + { PCI_DEVICE_ID_INTEL_SPT_H_CM236, "Skylake PCH-H CM236" }, { PCI_DEVICE_ID_INTEL_SPT_H_HM175, "Skylake PCH-H HM175" }, { PCI_DEVICE_ID_INTEL_SPT_H_QM175, "Skylake PCH-H QM175" }, { PCI_DEVICE_ID_INTEL_SPT_H_CM238, "Skylake PCH-H CM238" }, diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 7fbe9e519c..a7d58720a5 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -93,7 +93,7 @@ struct chip_operations soc_intel_skylake_ops = { void soc_silicon_init_params(SILICON_INIT_UPD *params) { struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); - const struct soc_intel_skylake_config *config = dev->chip_info; + const struct soc_intel_skylake_config *config = config_of(dev); int i; memcpy(params->SerialIoDevMode, config->SerialIoDevMode, diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index da941dc643..6c105cea8c 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -585,9 +585,6 @@ struct soc_intel_skylake_config { */ u8 IslVrCmd; - /* PCH Trip Temperature */ - u8 pch_trip_temp; - /* Enable/Disable Sata power optimization */ u8 SataPwrOptEnable; }; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index a1fced293d..064f71e2f2 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -232,16 +232,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { FSP_S_CONFIG *params = &supd->FspsConfig; FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; - static struct soc_intel_skylake_config *config; + struct soc_intel_skylake_config *config; + struct device *dev; uintptr_t vbt_data = (uintptr_t)vbt_get(); int i; - struct device *dev = SA_DEV_ROOT; - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); - return; - } - config = dev->chip_info; + config = config_of_path(SA_DEVFN_ROOT); mainboard_silicon_init_params(params); /* Set PsysPmax if it is available from DT */ diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index df08959cc8..eecb0048b9 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -116,11 +116,11 @@ void set_power_limits(u8 power_limit_1_time) unsigned int power_unit; unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; u8 power_limit_1_val; - struct device *dev = SA_DEV_ROOT; - config_t *conf = dev->chip_info; - if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr)) - power_limit_1_time = 28; + config_t *conf = config_of_path(SA_DEVFN_ROOT); + + if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) + power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; if (!(msr.lo & PLATFORM_INFO_SET_TDP)) return; @@ -240,13 +240,13 @@ void set_power_limits(u8 power_limit_1_time) static void configure_thermal_target(void) { - struct device *dev = SA_DEV_ROOT; - config_t *conf = dev->chip_info; + config_t *conf = config_of_path(SA_DEVFN_ROOT); msr_t msr; + /* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & (1 << 30)) && conf && conf->tcc_offset) { + if ((msr.lo & (1 << 30)) && conf->tcc_offset) { msr = rdmsr(MSR_TEMPERATURE_TARGET); msr.lo &= ~(0xf << 24); /* Bits 27:24 */ msr.lo |= (conf->tcc_offset & 0xf) << 24; @@ -260,10 +260,10 @@ static void configure_thermal_target(void) static void configure_isst(void) { - struct device *dev = SA_DEV_ROOT; - config_t *conf = dev->chip_info; + config_t *conf = config_of_path(SA_DEVFN_ROOT); msr_t msr; + if (conf->speed_shift_enable) { /* * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP @@ -286,21 +286,19 @@ static void configure_isst(void) static void configure_misc(void) { - struct device *dev = SA_DEV_ROOT; - if (!dev) { - printk(BIOS_ERR, "SA_DEV_ROOT device not found!\n"); - return; - } - config_t *conf = dev->chip_info; + config_t *conf = config_of_path(SA_DEVFN_ROOT); msr_t msr; + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ + if (conf->eist_enable) msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ else msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */ + wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ @@ -315,6 +313,7 @@ static void configure_misc(void) msr = rdmsr(MSR_POWER_CTL); msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 18); /* Enable Energy/Performance Bias control */ msr.lo &= ~POWER_CTL_C1E_MASK; /* Disable C1E */ msr.lo |= (1 << 23); /* Lock it */ wrmsr(MSR_POWER_CTL, msr); @@ -477,6 +476,8 @@ static void fc_lock_configure(void *unused) static void post_mp_init(void) { + int ret = 0; + /* Set Max Ratio */ cpu_set_max_ratio(); @@ -490,11 +491,14 @@ static void post_mp_init(void) if (CONFIG(HAVE_SMI_HANDLER)) smm_lock(); - mp_run_on_all_cpus(vmx_configure, NULL, 2 * USECS_PER_MSEC); + ret |= mp_run_on_all_cpus(vmx_configure, NULL, 2 * USECS_PER_MSEC); - mp_run_on_all_cpus(sgx_configure, NULL, 14 * USECS_PER_MSEC); + ret |= mp_run_on_all_cpus(sgx_configure, NULL, 14 * USECS_PER_MSEC); - mp_run_on_all_cpus(fc_lock_configure, NULL, 2 * USECS_PER_MSEC); + ret |= mp_run_on_all_cpus(fc_lock_configure, NULL, 2 * USECS_PER_MSEC); + + if (ret) + printk(BIOS_CRIT, "CRITICAL ERROR: MP post init failed\n"); } static const struct mp_ops mp_ops = { @@ -558,19 +562,7 @@ void cpu_lock_sgx_memory(void) int soc_fill_sgx_param(struct sgx_param *sgx_param) { - struct device *dev = SA_DEV_ROOT; - config_t *conf; - - if (!dev) { - printk(BIOS_ERR, "Failed to get root dev for checking SGX param\n"); - return -1; - } - - conf = dev->chip_info; - if (!conf) { - printk(BIOS_ERR, "Failed to get chip_info for SGX param\n"); - return -1; - } + config_t *conf = config_of_path(SA_DEVFN_ROOT); sgx_param->enable = conf->sgx_enable; return 0; diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 359f3e612a..47d6137ec7 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -39,18 +39,6 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) } } -#define XHCI_USB2_PORT_STATUS_REG 0x480 -#define XHCI_USB3_PORT_STATUS_REG 0x540 -#define XHCI_USB2_PORT_NUM 10 -#define XHCI_USB3_PORT_NUM 6 - -static const struct xhci_usb_info usb_info = { - .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, - .num_usb2_ports = XHCI_USB2_PORT_NUM, - .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, - .num_usb3_ports = XHCI_USB3_PORT_NUM, -}; - struct pme_status_info { #ifdef __SIMPLE_DEVICE__ pci_devfn_t dev; @@ -76,7 +64,7 @@ static void pch_log_add_elog_event(const struct pme_status_info *info, * USB2/3 ports. */ if ((info->dev == PCH_DEV_XHCI) && - pch_xhci_update_wake_event(&usb_info)) + pch_xhci_update_wake_event(soc_get_xhci_usb_info())) return; elog_add_event_wake(info->elog_event, 0); @@ -124,7 +112,7 @@ static void pch_log_pme_internal_wake_source(void) * PME_STS_BIT in controller register. */ if (!dev_found) - dev_found = pch_xhci_update_wake_event(&usb_info); + dev_found = pch_xhci_update_wake_event(soc_get_xhci_usb_info()); if (!dev_found) elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 34738f28f1..8afaf4d344 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -35,7 +36,6 @@ #include #include #include -#include #include #include @@ -76,7 +76,7 @@ static void pch_finalize_script(struct device *dev) intel_me_status(); pmcbase = pmc_mmio_regs(); - config = dev->chip_info; + config = config_of(dev); /* * Set low maximum temp value used for dynamic thermal sensor @@ -117,7 +117,7 @@ static void soc_lockdown(struct device *dev) struct soc_intel_skylake_config *config; u8 reg8; - config = dev->chip_info; + config = config_of(dev); /* Global SMI Lock */ if (config->LockDownConfigGlobalSmi == 0) { @@ -134,7 +134,7 @@ static void soc_finalize(void *unused) dev = PCH_DEV_PMC; /* Check if PMC is enabled, else return */ - if (dev == NULL || dev->chip_info == NULL) + if (dev == NULL) return; printk(BIOS_DEBUG, "Finalizing chipset.\n"); diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index 7efc65a591..c06893edf6 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -36,7 +36,7 @@ uintptr_t fsp_soc_get_igd_bar(void) static void graphics_setup_panel(struct device *dev) { - struct soc_intel_skylake_config *conf = dev->chip_info; + struct soc_intel_skylake_config *conf = config_of(dev); struct resource *mmio_res; uint8_t *base; u32 reg32; diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 5acaaebc5a..0e8bb6841f 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -19,34 +19,28 @@ #include -#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) #if !defined(__SIMPLE_DEVICE__) #include -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #else -#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) #endif /* System Agent Devices */ #define SA_DEV_SLOT_ROOT 0x00 -#define SA_DEVFN_ROOT _SA_DEVFN(ROOT) -#define SA_DEV_ROOT _SA_DEV(ROOT) +#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) +#if defined(__SIMPLE_DEVICE__) +#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) +#endif #define SA_DEV_SLOT_PEG 0x01 -#define SA_DEVFN_PEG(func) PCI_DEVFN(SA_DEV_SLOT_PEG, func) -#define SA_DEV_PEG(func) pcidev_path_on_root(SA_DEVFN_PEG(func)) -#define SA_DEV_PEG0 SA_DEV_PEG(0) -#define SA_DEV_PEG1 SA_DEV_PEG(1) -#define SA_DEV_PEG2 SA_DEV_PEG(2) #define SA_DEV_SLOT_IGD 0x02 -#define SA_DEVFN_IGD _SA_DEVFN(IGD) -#define SA_DEV_IGD _SA_DEV(IGD) +#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) +#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) /* PCH Devices */ diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 0c5e9766c0..9c15db2915 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -19,7 +19,7 @@ #include #include -#include +#include #include #include @@ -30,10 +30,8 @@ struct ied_header { } __packed; struct smm_relocation_params { - u32 smram_base; - u32 smram_size; - u32 ied_base; - u32 ied_size; + uintptr_t ied_base; + size_t ied_size; msr_t smrr_base; msr_t smrr_mask; msr_t emrr_base; diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index 03cdb071ce..ddaffda796 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -224,7 +224,7 @@ void soc_irq_settings(FSP_SIL_UPD *params) uint32_t i, intdeventry; u8 irq_config[PCH_MAX_IRQ_CONFIG]; const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); - const struct soc_intel_skylake_config *config = dev->chip_info; + const struct soc_intel_skylake_config *config = config_of(dev); /* Get Device Int Count */ intdeventry = ARRAY_SIZE(devintconfig); @@ -295,7 +295,7 @@ void soc_irq_settings(FSP_SIL_UPD *params) void soc_pch_pirq_init(const struct device *dev) { - const config_t *config = dev->chip_info; + const config_t *config = config_of(dev); uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; struct device *irq_dev; diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index d8e5ccc6c0..71ffb9a23f 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -69,7 +69,7 @@ static void pch_enable_ioapic(struct device *dev) void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) { - const config_t *config = dev->chip_info; + const config_t *config = config_of(dev); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; @@ -98,7 +98,7 @@ static const struct reg_script pch_misc_init_script[] = { void lpc_soc_init(struct device *dev) { - const config_t *const config = dev->chip_info; + const config_t *const config = config_of(dev); /* Legacy initialization */ isa_dma_init(); diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index ff7edbc95a..963a5003e8 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -18,32 +18,22 @@ #include #include #include +#include #include #include -#include #include #include #include #include +#include #include #include #include "chip.h" -size_t mmap_region_granularity(void) +void smm_region(uintptr_t *start, size_t *size) { - if (CONFIG(HAVE_SMI_HANDLER)) - /* Align to TSEG size when SMM is in use */ - if (CONFIG_SMM_TSEG_SIZE != 0) - return CONFIG_SMM_TSEG_SIZE; - - /* Make it 8MiB by default. */ - return 8*MiB; -} - -void smm_region(void **start, size_t *size) -{ - *start = (void *)sa_get_tseg_base(); + *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } @@ -58,16 +48,14 @@ void smm_region(void **start, size_t *size) * | (TSEG) | * +-------------------------+ TSEG */ -int smm_subregion(int sub, void **start, size_t *size) +int smm_subregion(int sub, uintptr_t *start, size_t *size) { uintptr_t sub_base; size_t sub_size; - void *smm_base; const size_t ied_size = CONFIG_IED_REGION_SIZE; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - smm_region(&smm_base, &sub_size); - sub_base = (uintptr_t)smm_base; + smm_region(&sub_base, &sub_size); switch (sub) { case SMM_SUBREGION_HANDLER: @@ -86,12 +74,13 @@ int smm_subregion(int sub, void **start, size_t *size) sub_size = ied_size; break; default: + *start = 0; + *size = 0; return -1; } - *start = (void *)sub_base; + *start = sub_base; *size = sub_size; - return 0; } @@ -207,7 +196,7 @@ static size_t calculate_reserved_mem_size(uintptr_t dram_base) size_t reserve_mem_size; const struct soc_intel_skylake_config *config; - config = dev->chip_info; + config = config_of(dev); /* Get PRMRR size */ reserve_mem_base -= get_prmrr_size(reserve_mem_base, config); diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index 01def44b06..ffe060518e 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -47,6 +47,27 @@ void pmc_set_disb(void) pci_write_config32(dev, GEN_PMCON_A, disb_val); } +/* + * Set which power state system will be after reapplying + * the power (from G3 State) + */ +void pmc_soc_set_afterg3_en(const bool on) +{ + uint8_t reg8; +#if defined(__SIMPLE_DEVICE__) + const pci_devfn_t dev = PCH_DEV_PMC; +#else + const struct device *const dev = PCH_DEV_PMC; +#endif + + reg8 = pci_read_config8(dev, GEN_PMCON_B); + if (on) + reg8 &= ~SLEEP_AFTER_POWER_FAIL; + else + reg8 |= SLEEP_AFTER_POWER_FAIL; + pci_write_config8(dev, GEN_PMCON_B, reg8); +} + #if ENV_RAMSTAGE /* Fill up PMC resource structure */ int pmc_soc_get_resources(struct pmc_resource_config *cfg) @@ -81,63 +102,6 @@ static const struct reg_script pmc_write1_to_clear_script[] = { REG_SCRIPT_END }; -/* - * Set which power state system will be after reapplying - * the power (from G3 State) - */ -static void pmc_set_afterg3(struct device *dev, int s5pwr) -{ - uint8_t reg8; - - reg8 = pci_read_config8(dev, GEN_PMCON_B); - - switch (s5pwr) { - case MAINBOARD_POWER_STATE_OFF: - reg8 |= 1; - break; - case MAINBOARD_POWER_STATE_ON: - reg8 &= ~1; - break; - case MAINBOARD_POWER_STATE_PREVIOUS: - default: - break; - } - - pci_write_config8(dev, GEN_PMCON_B, reg8); -} - -static void pch_power_options(struct device *dev) -{ - const char *state; - - const int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; - - /* - * Which state do we want to goto after g3 (power restored)? - * 0 == S5 Soft Off - * 1 == S0 Full On - * 2 == Keep Previous State - */ - switch (pwr_on) { - case MAINBOARD_POWER_STATE_OFF: - state = "off"; - break; - case MAINBOARD_POWER_STATE_ON: - state = "on"; - break; - case MAINBOARD_POWER_STATE_PREVIOUS: - state = "state keep"; - break; - default: - state = "undefined"; - } - pmc_set_afterg3(dev, pwr_on); - printk(BIOS_INFO, "Set power %s after power failure.\n", state); - - /* Set up GPE configuration. */ - pmc_gpe_init(); -} - static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) { uint32_t reg; @@ -181,12 +145,12 @@ static void config_deep_sx(uint32_t deepsx_config) void pmc_soc_init(struct device *dev) { - const config_t *config = dev->chip_info; + const config_t *config = config_of(dev); rtc_init(); - /* Initialize power management */ - pch_power_options(dev); + pmc_set_power_failure_state(true); + pmc_gpe_init(); /* Note that certain bits may be cleared from running script as * certain bit fields are write 1 to clear. */ @@ -201,15 +165,6 @@ void pmc_soc_init(struct device *dev) reg_script_run_on_dev(dev, pmc_write1_to_clear_script); } -/* - * Set PMC register to know which state system should be after - * power reapplied - */ -void pmc_soc_restore_power_failure(void) -{ - pmc_set_afterg3(PCH_DEV_PMC, CONFIG_MAINBOARD_POWER_FAILURE_STATE); -} - static void pm1_enable_pwrbtn_smi(void *unused) { /* @@ -233,12 +188,7 @@ BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL); */ static void pm1_handle_wake_pin(void *unused) { - struct device *dev = SA_DEV_ROOT; - - if (!dev || !dev->chip_info) - return; - - const config_t *conf = dev->chip_info; + const config_t *conf = config_of_path(SA_DEVFN_ROOT); /* If WAKE# pin is enabled, bail out early. */ if (conf->deep_sx_config & DSX_EN_WAKE_PIN) diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 9732aa1617..90f1b038e0 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -177,13 +177,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_skylake_config *config; - /* Look up the device in devicetree */ - DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC); - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); - return; - } - config = dev->chip_info; + config = config_of_path(PCH_DEVFN_PMC); /* Assign to out variable */ *dw0 = config->gpe0_dw0; diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 2bbab475af..2d0de2f5e9 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -39,26 +39,26 @@ /* SOC initialization before RAM is enabled */ void soc_pre_ram_init(struct romstage_params *params) { + const struct soc_intel_skylake_config *config; + /* Program MCHBAR and DMIBAR */ systemagent_early_init(); - const struct device *const dev = pcidev_path_on_root(PCH_DEVFN_LPC); - const struct soc_intel_skylake_config *const config = - dev ? dev->chip_info : NULL; + config = config_of_path(PCH_DEVFN_LPC); + /* Force a full memory train if RMT is enabled */ - params->disable_saved_data = config && config->Rmt; + params->disable_saved_data = config->Rmt; } /* UPD parameters to be initialized before MemoryInit */ void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd) { - const struct device *dev; const struct soc_intel_skylake_config *config; /* Set the parameters for MemoryInit */ - dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0); - config = dev->chip_info; + + config = config_of_path(PCH_DEVFN_LPC); /* * Set IGD stolen size to 64MB. The FBC hardware for skylake does not diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 6884a324a8..221c6c41d5 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -18,11 +18,11 @@ #include #include #include +#include #include #include #include #include -#include #include #include #include @@ -173,9 +173,8 @@ asmlinkage void car_stage_entry(void) postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); if (CONFIG(HAVE_SMI_HANDLER)) { - void *smm_base; + uintptr_t smm_base; size_t smm_size; - uintptr_t tseg_base; /* * Cache the TSEG region at the top of ram. This region is @@ -185,8 +184,7 @@ asmlinkage void car_stage_entry(void) * region for other purposes. */ smm_region(&smm_base, &smm_size); - tseg_base = (uintptr_t)smm_base; - postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, + postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); } @@ -223,7 +221,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, * If PEG port is not defined in the device tree, it will be disabled * in FSP */ - dev = SA_DEV_PEG0; /* PEG 0:1:0 */ + dev = pcidev_on_root(SA_DEV_SLOT_PEG, 0); /* PEG 0:1:0 */ if (!dev || !dev->enabled) m_cfg->Peg0Enable = 0; else if (dev->enabled) { @@ -238,7 +236,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, m_t_cfg->Peg0Gen3EqPh3Method = 0; } - dev = SA_DEV_PEG1; /* PEG 0:1:1 */ + dev = pcidev_on_root(SA_DEV_SLOT_PEG, 1); /* PEG 0:1:1 */ if (!dev || !dev->enabled) m_cfg->Peg1Enable = 0; else if (dev->enabled) { @@ -250,7 +248,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, m_t_cfg->Peg1Gen3EqPh3Method = 0; } - dev = SA_DEV_PEG2; /* PEG 0:1:2 */ + dev = pcidev_on_root(SA_DEV_SLOT_PEG, 2); /* PEG 0:1:2 */ if (!dev || !dev->enabled) m_cfg->Peg2Enable = 0; else if (dev->enabled) { @@ -326,13 +324,11 @@ static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg, void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { - const struct device *dev; const struct soc_intel_skylake_config *config; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; - dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0); - config = dev->chip_info; + config = config_of_path(PCH_DEVFN_LPC); soc_memory_init_params(m_cfg, config); soc_peg_init_params(m_cfg, m_t_cfg, config); diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index 00f620ff14..9b7ea2470e 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -26,13 +26,11 @@ static void systemagent_vtd_init(void) { - const struct device *const root_dev = pcidev_path_on_root(SA_DEVFN_ROOT); const struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); const struct soc_intel_skylake_config *config = NULL; - if (root_dev) - config = root_dev->chip_info; - if (config && config->ignore_vtd) + config = config_of_path(SA_DEVFN_ROOT); + if (config->ignore_vtd) return; const bool vtd_capable = diff --git a/src/soc/intel/skylake/sd.c b/src/soc/intel/skylake/sd.c index 571d3e7b44..a24d03f98d 100644 --- a/src/soc/intel/skylake/sd.c +++ b/src/soc/intel/skylake/sd.c @@ -18,7 +18,7 @@ int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, struct device *dev) { - config_t *config = dev->chip_info; + config_t *config = config_of(dev); /* Nothing to write if GPIO is not set in devicetree */ if(!config->sdcard_cd_gpio_default && !config->sdcard_cd_gpio.pins[0]) diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 12ed26a56e..9bc599a3cd 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -180,14 +180,9 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, write_smrr(relo_params); } -static void fill_in_relocation_params(struct device *dev, - struct smm_relocation_params *params) +static void fill_in_relocation_params(struct smm_relocation_params *params) { - void *handler_base; - size_t handler_size; - void *ied_base; - size_t ied_size; - void *tseg_base; + uintptr_t tseg_base; size_t tseg_size; u32 emrr_base; u32 emrr_size; @@ -202,20 +197,12 @@ static void fill_in_relocation_params(struct device *dev, phys_bits = cpuid_eax(0x80000008) & 0xff; smm_region(&tseg_base, &tseg_size); - smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); - smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size); - - params->smram_size = handler_size; - params->smram_base = (uintptr_t)handler_base; - - params->ied_base = (uintptr_t)ied_base; - params->ied_size = ied_size; + smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) - | MTRR_PHYS_MASK_VALID; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; params->smrr_mask.hi = 0; /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */ @@ -252,8 +239,8 @@ static void setup_ied_area(struct smm_relocation_params *params) ied_base = (void *)params->ied_base; - printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base); - printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size); + printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32) params->ied_base); + printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32) params->ied_size); /* Place IED header at IEDBASE. */ memcpy(ied_base, &ied, sizeof(ied)); @@ -265,17 +252,15 @@ static void setup_ied_area(struct smm_relocation_params *params) void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - struct device *dev = SA_DEV_ROOT; - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - fill_in_relocation_params(dev, &smm_reloc_params); + fill_in_relocation_params(&smm_reloc_params); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); if (smm_reloc_params.ied_size) setup_ied_area(&smm_reloc_params); - *perm_smbase = smm_reloc_params.smram_base; - *perm_smsize = smm_reloc_params.smram_size; *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); } @@ -310,11 +295,12 @@ void smm_relocate(void) void smm_lock(void) { + struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); /* * LOCK the SMM memory window and enable normal SMM. * After running this function, only a full reset can * make the SMM registers writable again. */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); + pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index bfaadfd3a9..410265f68e 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -29,7 +29,7 @@ bool soc_is_vtd_capable(void) { - struct device *const root_dev = SA_DEV_ROOT; + struct device *const root_dev = pcidev_path_on_root(SA_DEVFN_ROOT); return root_dev && !(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE); } @@ -42,7 +42,8 @@ bool soc_is_vtd_capable(void) */ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { - struct device *const igd_dev = SA_DEV_IGD; + struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); + static const struct sa_mmio_descriptor soc_fixed_resources[] = { { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, "PCIEXBAR" }, @@ -52,12 +53,12 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { GDXCBAR, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE, "GDXCBAR" }, { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, }; - const struct soc_intel_skylake_config *const config = dev->chip_info; + const struct soc_intel_skylake_config *const config = config_of(dev); sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, ARRAY_SIZE(soc_fixed_resources)); - if (!(config && config->ignore_vtd) && soc_is_vtd_capable()) { + if (!config->ignore_vtd && soc_is_vtd_capable()) { if (igd_dev && igd_dev->enabled) sa_add_fixed_mmio_resources(dev, index, &soc_gfxvt_mmio_descriptor, 1); diff --git a/src/soc/intel/skylake/thermal.c b/src/soc/intel/skylake/thermal.c deleted file mode 100644 index 97cd1b7779..0000000000 --- a/src/soc/intel/skylake/thermal.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "chip.h" - -#define MAX_TRIP_TEMP 205 -#define DEFAULT_TRIP_TEMP 50 - -static void *pch_thermal_get_bar(struct device *dev) -{ - uintptr_t bar; - - bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); - /* - * Bits [31:12] are the base address as per EDS for Thermal Device, - * Don't care about [11:0] bits - */ - return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); -} - -static void pch_thermal_set_bar(struct device *dev, uintptr_t tempbar) -{ - uint8_t pcireg; - - /* Assign Resources to Thermal Device */ - /* Clear BIT 1-2 of Command Register */ - pcireg = pci_read_config8(dev, PCI_COMMAND); - pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config8(dev, PCI_COMMAND, pcireg); - - /* Program Temporary BAR for Thermal Device */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar); - pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); - - /* Enable Bus Master and MMIO Space */ - pcireg = pci_read_config8(dev, PCI_COMMAND); - pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config8(dev, PCI_COMMAND, pcireg); -} - -/* PCH Low Temp Threshold (LTT) */ -static uint16_t pch_get_ltt_value(struct device *dev) -{ - static struct soc_intel_skylake_config *config; - uint16_t ltt_value; - uint16_t trip_temp = DEFAULT_TRIP_TEMP; - - config = dev->chip_info; - - if (config->pch_trip_temp) - trip_temp = config->pch_trip_temp; - - if (trip_temp > MAX_TRIP_TEMP) - die("Input PCH temp trip is higher than allowed range!"); - - /* Trip Point Temp = (LTT / 2 - 50 degree C) */ - ltt_value = (trip_temp + 50) * 2; - - return ltt_value; -} - -/* Enable thermal sensor power management */ -void pch_thermal_configuration(void) -{ - uint16_t reg16; - struct device *dev = PCH_DEV_THERMAL; - if (!dev) { - printk(BIOS_ERR, "PCH_DEV_THERMAL device not found!\n"); - return; - } - void *thermalbar = pch_thermal_get_bar(dev); - - /* Use default pre-ram bar */ - if (!thermalbar) { - pch_thermal_set_bar(dev, THERMAL_BASE_ADDRESS); - thermalbar = (void *)THERMAL_BASE_ADDRESS; - } - - /* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */ - reg16 = read16(thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT); - reg16 &= ~0x1ff; - /* Low Temp Threshold (LTT) */ - reg16 |= pch_get_ltt_value(dev); - write16(thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT, reg16); -} diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c index 8b7c99eae5..18fcf1b194 100644 --- a/src/soc/intel/skylake/uart.c +++ b/src/soc/intel/skylake/uart.c @@ -51,7 +51,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); -struct device *soc_uart_console_to_device(int uart_console) +DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) { /* * if index is valid, this function will return corresponding structure @@ -59,11 +59,11 @@ struct device *soc_uart_console_to_device(int uart_console) */ switch (uart_console) { case 0: - return (struct device *)PCH_DEV_UART0; + return pcidev_path_on_root(PCH_DEVFN_UART0); case 1: - return (struct device *)PCH_DEV_UART1; + return pcidev_path_on_root(PCH_DEVFN_UART1); case 2: - return (struct device *)PCH_DEV_UART2; + return pcidev_path_on_root(PCH_DEVFN_UART2); default: printk(BIOS_ERR, "Invalid UART console index\n"); return NULL; diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 905154e8ac..c83e18dd1d 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -174,17 +174,19 @@ static uint16_t get_dev_id(struct device *dev) static int get_kbl_sku(void) { + struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); static int sku = -1; uint16_t id; if (sku != -1) return sku; - id = get_dev_id(SA_DEV_ROOT); + id = get_dev_id(sa_dev); if (id == PCI_DEVICE_ID_INTEL_KBL_U_R) sku = KBL_R_SKU; else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_Y) { - id = get_dev_id(SA_DEV_IGD); + struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); + id = get_dev_id(igd_dev); if (id == PCI_DEVICE_ID_INTEL_AML_GT2_ULX) sku = AML_Y_SKU; else diff --git a/src/soc/intel/skylake/xhci.c b/src/soc/intel/skylake/xhci.c new file mode 100644 index 0000000000..bca3b861ea --- /dev/null +++ b/src/soc/intel/skylake/xhci.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#define XHCI_USB3_PORT_STATUS_REG 0x540 +#define XHCI_USB2_PORT_NUM 10 +#define XHCI_USB3_PORT_NUM 6 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + +const struct xhci_usb_info *soc_get_xhci_usb_info(void) +{ + return &usb_info; +} diff --git a/src/soc/mediatek/common/ddp.c b/src/soc/mediatek/common/ddp.c new file mode 100644 index 0000000000..173fa90cd7 --- /dev/null +++ b/src/soc/mediatek/common/ddp.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) +#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) + +void ovl_set_roi(u32 idx, u32 width, u32 height, u32 color) +{ + write32(&disp_ovl[idx]->roi_size, height << 16 | width); + write32(&disp_ovl[idx]->roi_bgclr, color); +} + +void rdma_start(void) +{ + setbits_le32(&disp_rdma0->global_con, RDMA_ENGINE_EN); +} + +void rdma_config(u32 width, u32 height, u32 pixel_clk, u32 fifo_size) +{ + u32 threshold; + u32 reg; + + clrsetbits_le32(&disp_rdma0->size_con_0, 0x1FFF, width); + clrsetbits_le32(&disp_rdma0->size_con_1, 0xFFFFF, height); + + /* + * Enable FIFO underflow since DSI and DPI can't be blocked. Set the + * output threshold to 6 microseconds with 7/6 overhead to account for + * blanking, and with a pixel depth of 4 bytes: + */ + threshold = pixel_clk * 4 * 7 / 1000; + + if (threshold > fifo_size) + threshold = fifo_size; + + reg = RDMA_FIFO_UNDERFLOW_EN | RDMA_FIFO_PSEUDO_SIZE(fifo_size) | + RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); + + write32(&disp_rdma0->fifo_con, reg); +} + +void color_start(u32 width, u32 height) +{ + + write32(&disp_color0->width, width); + write32(&disp_color0->height, height); + write32(&disp_color0->cfg_main, COLOR_BYPASS_ALL | COLOR_SEQ_SEL); + write32(&disp_color0->start, BIT(0)); +} + +void ovl_layer_config(u32 fmt, u32 bpp, u32 width, u32 height) +{ + struct disp_ovl_regs *const ovl0 = disp_ovl[0]; + write32(&ovl0->layer[0].con, fmt << 12); + write32(&ovl0->layer[0].src_size, height << 16 | width); + write32(&ovl0->layer[0].pitch, (width * bpp) & 0xFFFF); + + /* Enable layer */ + write32(&ovl0->rdma[0].ctrl, BIT(0)); + write32(&ovl0->rdma[0].mem_gmc_setting, RDMA_MEM_GMC); + + setbits_le32(&ovl0->src_con, BIT(0)); +} diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c new file mode 100644 index 0000000000..e58bb9c4ea --- /dev/null +++ b/src/soc/mediatek/common/i2c.c @@ -0,0 +1,261 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static inline void i2c_dma_reset(struct mt_i2c_dma_regs *dma_regs) +{ + write32(&dma_regs->dma_rst, 0x1); + udelay(50); + write32(&dma_regs->dma_rst, 0x2); + udelay(50); + write32(&dma_regs->dma_rst, 0x0); + udelay(50); +} + +static inline void mtk_i2c_dump_info(struct mt_i2c_regs *regs) +{ + printk(BIOS_ERR, "I2C register:\nSLAVE_ADDR %x\nINTR_MASK %x\n" + "INTR_STAT %x\nCONTROL %x\nTRANSFER_LEN %x\nTRANSAC_LEN %x\n" + "DELAY_LEN %x\nTIMING %x\nSTART %x\nFIFO_STAT %x\nIO_CONFIG %x\n" + "HS %x\nDEBUGSTAT %x\nEXT_CONF %x\n", + read32(®s->slave_addr), + read32(®s->intr_mask), + read32(®s->intr_stat), + read32(®s->control), + read32(®s->transfer_len), + read32(®s->transac_len), + read32(®s->delay_len), + read32(®s->timing), + read32(®s->start), + read32(®s->fifo_stat), + read32(®s->io_config), + read32(®s->hs), + read32(®s->debug_stat), + read32(®s->ext_conf)); +} + +static uint32_t mtk_i2c_transfer(uint8_t bus, struct i2c_msg *seg, + enum i2c_modes mode) +{ + uint32_t ret_code = I2C_OK; + uint16_t status; + uint32_t time_out_val = 0; + uint8_t addr; + uint32_t write_len = 0; + uint32_t read_len = 0; + uint8_t *write_buffer = NULL; + uint8_t *read_buffer = NULL; + struct mt_i2c_regs *regs; + struct mt_i2c_dma_regs *dma_regs; + struct stopwatch sw; + + regs = mtk_i2c_bus_controller[bus].i2c_regs; + dma_regs = mtk_i2c_bus_controller[bus].i2c_dma_regs; + + addr = seg[0].slave; + + switch (mode) { + case I2C_WRITE_MODE: + assert(seg[0].len > 0 && seg[0].len <= 255); + write_len = seg[0].len; + write_buffer = seg[0].buf; + break; + + case I2C_READ_MODE: + assert(seg[0].len > 0 && seg[0].len <= 255); + read_len = seg[0].len; + read_buffer = seg[0].buf; + break; + + /* Must use special write-then-read mode for repeated starts. */ + case I2C_WRITE_READ_MODE: + assert(seg[0].len > 0 && seg[0].len <= 255); + assert(seg[1].len > 0 && seg[1].len <= 255); + write_len = seg[0].len; + read_len = seg[1].len; + write_buffer = seg[0].buf; + read_buffer = seg[1].buf; + break; + } + + /* Clear interrupt status */ + write32(®s->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR | + I2C_HS_NACKERR); + + write32(®s->fifo_addr_clr, 0x1); + + /* Enable interrupt */ + write32(®s->intr_mask, I2C_HS_NACKERR | I2C_ACKERR | + I2C_TRANSAC_COMP); + + switch (mode) { + case I2C_WRITE_MODE: + memcpy(_dma_coherent, write_buffer, write_len); + + /* control registers */ + write32(®s->control, ASYNC_MODE | DMAACK_EN | + ACK_ERR_DET_EN | DMA_EN | CLK_EXT | + REPEATED_START_FLAG); + + /* Set transfer and transaction len */ + write32(®s->transac_len, 1); + write32(®s->transfer_len, write_len); + + /* set i2c write slave address*/ + write32(®s->slave_addr, addr << 1); + + /* Prepare buffer data to start transfer */ + write32(&dma_regs->dma_con, I2C_DMA_CON_TX); + write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); + write32(&dma_regs->dma_tx_len, write_len); + break; + + case I2C_READ_MODE: + /* control registers */ + write32(®s->control, ASYNC_MODE | DMAACK_EN | + ACK_ERR_DET_EN | DMA_EN | CLK_EXT | + REPEATED_START_FLAG); + + /* Set transfer and transaction len */ + write32(®s->transac_len, 1); + write32(®s->transfer_len, read_len); + + /* set i2c read slave address*/ + write32(®s->slave_addr, (addr << 1 | 0x1)); + + /* Prepare buffer data to start transfer */ + write32(&dma_regs->dma_con, I2C_DMA_CON_RX); + write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); + write32(&dma_regs->dma_rx_len, read_len); + break; + + case I2C_WRITE_READ_MODE: + memcpy(_dma_coherent, write_buffer, write_len); + + /* control registers */ + write32(®s->control, ASYNC_MODE | DMAACK_EN | + DIR_CHG | ACK_ERR_DET_EN | DMA_EN | + CLK_EXT | REPEATED_START_FLAG); + + /* Set transfer and transaction len */ + write32(®s->transfer_len, write_len); + write32(®s->transfer_aux_len, read_len); + write32(®s->transac_len, 2); + + /* set i2c write slave address*/ + write32(®s->slave_addr, addr << 1); + + /* Prepare buffer data to start transfer */ + write32(&dma_regs->dma_con, I2C_DMA_CLR_FLAG); + write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); + write32(&dma_regs->dma_tx_len, write_len); + write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); + write32(&dma_regs->dma_rx_len, read_len); + break; + } + + write32(&dma_regs->dma_int_flag, I2C_DMA_CLR_FLAG); + write32(&dma_regs->dma_en, I2C_DMA_START_EN); + + /* start transfer transaction */ + write32(®s->start, 0x1); + + stopwatch_init_msecs_expire(&sw, 100); + + /* polling mode : see if transaction complete */ + while (1) { + status = read32(®s->intr_stat); + if (status & I2C_HS_NACKERR) { + ret_code = I2C_TRANSFER_FAIL_HS_NACKERR; + printk(BIOS_ERR, "[i2c%d] transfer NACK error\n", bus); + mtk_i2c_dump_info(regs); + break; + } else if (status & I2C_ACKERR) { + ret_code = I2C_TRANSFER_FAIL_ACKERR; + printk(BIOS_ERR, "[i2c%d] transfer ACK error\n", bus); + mtk_i2c_dump_info(regs); + break; + } else if (status & I2C_TRANSAC_COMP) { + ret_code = I2C_OK; + memcpy(read_buffer, _dma_coherent, read_len); + break; + } + + if (stopwatch_expired(&sw)) { + ret_code = I2C_TRANSFER_FAIL_TIMEOUT; + printk(BIOS_ERR, "[i2c%d] transfer timeout:%d\n", bus, + time_out_val); + mtk_i2c_dump_info(regs); + break; + } + } + + write32(®s->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR | + I2C_HS_NACKERR); + + /* clear bit mask */ + write32(®s->intr_mask, I2C_HS_NACKERR | I2C_ACKERR | + I2C_TRANSAC_COMP); + + /* reset the i2c controller for next i2c transfer. */ + write32(®s->softreset, 0x1); + + i2c_dma_reset(dma_regs); + + return ret_code; +} + +static bool mtk_i2c_should_combine(struct i2c_msg *seg, int left_count) +{ + return (left_count >= 2 && + !(seg[0].flags & I2C_M_RD) && + (seg[1].flags & I2C_M_RD) && + seg[0].slave == seg[1].slave); +} + +int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, + int seg_count) +{ + int ret = 0; + int i; + int mode; + + for (i = 0; i < seg_count; i++) { + if (mtk_i2c_should_combine(&segments[i], seg_count - i)) { + mode = I2C_WRITE_READ_MODE; + } else { + mode = (segments[i].flags & I2C_M_RD) ? + I2C_READ_MODE : I2C_WRITE_MODE; + } + + ret = mtk_i2c_transfer(bus, &segments[i], mode); + + if (ret) + break; + + if (mode == I2C_WRITE_READ_MODE) + i++; + } + + return ret; +} diff --git a/src/soc/mediatek/common/include/soc/ddp_common.h b/src/soc/mediatek/common/include/soc/ddp_common.h new file mode 100644 index 0000000000..6d00ea3c75 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/ddp_common.h @@ -0,0 +1,157 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DDP_COMMON_H_ +#define _DDP_COMMON_H_ + +#include +#include + + +struct disp_ovl_regs { + u32 sta; + u32 inten; + u32 intsta; + u32 en; + u32 trig; + u32 rst; + u8 reserved0[8]; + u32 roi_size; + u32 datapath_con; + u32 roi_bgclr; + u32 src_con; + struct { + u32 con; + u32 srckey; + u32 src_size; + u32 offset; + u32 reserved0; + u32 pitch; + u32 reserved1[2]; + } layer[4]; + u8 reserved8[16]; + struct { + u32 ctrl; + u32 mem_start_trig; + u32 mem_gmc_setting; + u32 mem_slow_con; + u32 fifo_ctrl; + u8 reserved[12]; + } rdma[4]; + u8 reserved12[148]; + u32 debug_mon_sel; + u8 reserved13[8]; + u32 rdma_mem_gmc_setting2[4]; + u8 reserved14[16]; + u32 dummy; + u8 reserved15[60]; + u32 flow_ctrl_dbg; + u32 addcon_dbg; + u32 outmux_dbg; + u32 rdma_dbg[4]; + u8 reserved16[3300]; + u32 l0_addr; + u8 reserved17[28]; + u32 l1_addr; + u8 reserved18[28]; + u32 l2_addr; + u8 reserved19[28]; + u32 l3_addr; +}; + +check_member(disp_ovl_regs, l3_addr, 0xFA0); +static struct disp_ovl_regs *const disp_ovl[2] = { + (void *)DISP_OVL0_BASE, (void *)DISP_OVL1_BASE +}; + +struct disp_rdma_regs { + u32 int_enable; + u32 int_status; + u8 reserved0[8]; + u32 global_con; + u32 size_con_0; + u32 size_con_1; + u32 target_line; + u8 reserved1[4]; + u32 mem_con; + u32 mem_start_addr; + u32 mem_src_pitch; + u32 mem_gmc_setting_0; + u32 mem_slow_con; + u32 mem_gmc_setting_1; + u8 reserved2[4]; + u32 fifo_con; + u8 reserved3[16]; + u32 cf[3][3]; + u32 cf_pre_add[3]; + u32 cf_post_add[3]; + u32 dummy; + u32 debug_out_sel; +}; + +enum { + RDMA_ENGINE_EN = BIT(0), + RDMA_FIFO_UNDERFLOW_EN = BIT(31), + RDMA_MEM_GMC = 0x40402020, +}; + +check_member(disp_rdma_regs, debug_out_sel, 0x94); +static struct disp_rdma_regs *const disp_rdma0 = (void *)DISP_RDMA0_BASE; + +struct disp_color_regs { + u8 reserved0[1024]; + u32 cfg_main; + u8 reserved1[2044]; + u32 start; + u8 reserved2[76]; + u32 width; + u32 height; +}; + +check_member(disp_color_regs, cfg_main, 0x400); +check_member(disp_color_regs, start, 0xC00); +check_member(disp_color_regs, width, 0xC50); +check_member(disp_color_regs, height, 0xC54); +static struct disp_color_regs *const disp_color0 = (void *)DISP_COLOR0_BASE; + + +enum { + COLOR_BYPASS_ALL = BIT(7), + COLOR_SEQ_SEL = BIT(13), +}; + +enum OVL_INPUT_FORMAT { + OVL_INFMT_RGB565 = 0, + OVL_INFMT_RGB888 = 1, + OVL_INFMT_RGBA8888 = 2, + OVL_INFMT_ARGB8888 = 3, + OVL_INFMT_UYVY = 4, + OVL_INFMT_YUYV = 5, + OVL_INFMT_UNKNOWN = 16, + + OVL_COLOR_BASE = 30, + OVL_INFMT_BGR565 = OVL_INFMT_RGB565 + OVL_COLOR_BASE, + OVL_INFMT_BGR888 = OVL_INFMT_RGB888 + OVL_COLOR_BASE, + OVL_INFMT_BGRA8888 = OVL_INFMT_RGBA8888 + OVL_COLOR_BASE, + OVL_INFMT_ABGR8888 = OVL_INFMT_ARGB8888 + OVL_COLOR_BASE, +}; + +void ovl_set_roi(u32 idx, u32 width, u32 height, u32 color); +void rdma_start(void); +void rdma_config(u32 width, u32 height, u32 pixel_clk, u32 fifo_size); +void color_start(u32 width, u32 height); +void ovl_layer_config(u32 fmt, u32 bpp, u32 width, u32 height); + +#endif diff --git a/src/soc/mediatek/common/include/soc/i2c_common.h b/src/soc/mediatek/common/include/soc/i2c_common.h new file mode 100644 index 0000000000..c9dade4d82 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/i2c_common.h @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MTK_COMMON_I2C_H +#define MTK_COMMON_I2C_H + +/* I2C DMA Registers */ +struct mt_i2c_dma_regs { + uint32_t dma_int_flag; + uint32_t dma_int_en; + uint32_t dma_en; + uint32_t dma_rst; + uint32_t reserved1; + uint32_t dma_flush; + uint32_t dma_con; + uint32_t dma_tx_mem_addr; + uint32_t dma_rx_mem_addr; + uint32_t dma_tx_len; + uint32_t dma_rx_len; +}; + +check_member(mt_i2c_dma_regs, dma_tx_len, 0x24); + +/* I2C Configuration */ +enum { + I2C_HS_DEFAULT_VALUE = 0x0102, +}; + +enum i2c_modes { + I2C_WRITE_MODE = 0, + I2C_READ_MODE = 1, + I2C_WRITE_READ_MODE = 2, +}; + +enum { + I2C_DMA_CON_TX = 0x0, + I2C_DMA_CON_RX = 0x1, + I2C_DMA_START_EN = 0x1, + I2C_DMA_INT_FLAG_NONE = 0x0, + I2C_DMA_CLR_FLAG = 0x0, + I2C_DMA_FLUSH_FLAG = 0x1, +}; + +enum { + I2C_TRANS_LEN_MASK = (0xff), + I2C_TRANS_AUX_LEN_MASK = (0x1f << 8), + I2C_CONTROL_MASK = (0x3f << 1) +}; + +/* Register mask */ +enum { + I2C_HS_NACKERR = (1 << 2), + I2C_ACKERR = (1 << 1), + I2C_TRANSAC_COMP = (1 << 0), +}; + +/* i2c control bits */ +enum { + ASYNC_MODE = (1 << 9), + DMAACK_EN = (1 << 8), + ACK_ERR_DET_EN = (1 << 5), + DIR_CHG = (1 << 4), + CLK_EXT = (1 << 3), + DMA_EN = (1 << 2), + REPEATED_START_FLAG = (1 << 1), + STOP_FLAG = (0 << 1) +}; + +/* I2C Status Code */ + +enum { + I2C_OK = 0x0000, + I2C_SET_SPEED_FAIL_OVER_SPEED = 0xA001, + I2C_TRANSFER_INVALID_LENGTH = 0xA002, + I2C_TRANSFER_FAIL_HS_NACKERR = 0xA003, + I2C_TRANSFER_FAIL_ACKERR = 0xA004, + I2C_TRANSFER_FAIL_TIMEOUT = 0xA005, + I2C_TRANSFER_INVALID_ARGUMENT = 0xA006 +}; + +struct mtk_i2c { + struct mt_i2c_regs *i2c_regs; + struct mt_i2c_dma_regs *i2c_dma_regs; +}; + +extern struct mtk_i2c mtk_i2c_bus_controller[]; +#endif diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c index 1af6f105c3..40ab9b7002 100644 --- a/src/soc/mediatek/common/spi.c +++ b/src/soc/mediatek/common/spi.c @@ -17,10 +17,10 @@ #include #include #include -#include #include #include #include +#include #define MTK_SPI_DEBUG 0 diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 0ffa1965a9..510fbf0cc5 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -17,7 +17,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8173),y) bootblock-y += bootblock.c bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c -bootblock-y += i2c.c +bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/pll.c pll.c bootblock-y += ../common/spi.c spi.c bootblock-y += ../common/timer.c @@ -32,7 +32,7 @@ bootblock-y += ../common/mmu_operations.c mmu_operations.c ################################################################################ -verstage-y += i2c.c +verstage-y += ../common/i2c.c i2c.c verstage-y += ../common/spi.c spi.c verstage-y += ../common/uart.c @@ -49,7 +49,7 @@ romstage-$(CONFIG_SPI_FLASH) += flash_controller.c romstage-y += ../common/pll.c pll.c romstage-y += ../common/timer.c romstage-y += timer.c -romstage-y += i2c.c +romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/uart.c romstage-y += ../common/cbmem.c @@ -71,7 +71,8 @@ ramstage-y += soc.c ../common/mtcmos.c ramstage-y += ../common/timer.c ramstage-y += timer.c ramstage-y += ../common/uart.c -ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c i2c.c +ramstage-y += ../common/i2c.c i2c.c +ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c ramstage-y += mt6311.c ramstage-y += da9212.c ramstage-y += ../common/gpio.c gpio.c @@ -81,7 +82,7 @@ ramstage-y += ../common/rtc.c rtc.c ramstage-y += ../common/usb.c usb.c -ramstage-y += ddp.c +ramstage-y += ../common/ddp.c ddp.c ramstage-y += dsi.c ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c diff --git a/src/soc/mediatek/mt8173/ddp.c b/src/soc/mediatek/mt8173/ddp.c index f8896d391a..9f201fd0d4 100644 --- a/src/soc/mediatek/mt8173/ddp.c +++ b/src/soc/mediatek/mt8173/ddp.c @@ -21,25 +21,13 @@ #include #include -#define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) -#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) - -static void disp_config_main_path_connection(bool dual_dsi_mode) +static void disp_config_main_path_connection(void) { write32(&mmsys_cfg->disp_ovl0_mout_en, OVL0_MOUT_EN_COLOR0); - write32(&mmsys_cfg->disp_color0_sel_in, COLOR0_SEL_IN_OVL0); - write32(&mmsys_cfg->disp_od_mout_en, OD_MOUT_EN_RDMA0); - - if (dual_dsi_mode) { - write32(&mmsys_cfg->disp_ufoe_mout_en, UFOE_MOUT_EN_SPLIT1); - write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_SPLIT1); - write32(&mmsys_cfg->dsi1_sel_in, DSI1_SEL_IN_SPLIT1); - } else { - write32(&mmsys_cfg->disp_ufoe_mout_en, UFOE_MOUT_EN_DSI0); - write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_UFOE); - } + write32(&mmsys_cfg->disp_ufoe_mout_en, UFOE_MOUT_EN_DSI0); + write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_UFOE); } static void disp_config_main_path_mutex(void) @@ -51,52 +39,6 @@ static void disp_config_main_path_mutex(void) write32(&disp_mutex->mutex[0].en, BIT(0)); } -static void ovl_set_roi(u32 width, u32 height, u32 color) -{ - write32(&disp_ovl[0]->roi_size, height << 16 | width); - write32(&disp_ovl[0]->roi_bgclr, color); -} - -static void ovl_layer_enable(void) -{ - write32(&disp_ovl[0]->rdma[0].ctrl, BIT(0)); - write32(&disp_ovl[0]->rdma[0].mem_gmc_setting, RDMA_MEM_GMC); - - setbits_le32(&disp_ovl[0]->src_con, BIT(0)); -} - -static void rdma_start(void) -{ - setbits_le32(&disp_rdma[0]->global_con, RDMA_ENGINE_EN); -} - -static void rdma_config(u32 width, u32 height, u32 pixel_clk) -{ - u32 threshold; - u32 reg; - - /* Config width */ - clrsetbits_le32(&disp_rdma[0]->size_con_0, 0x1FFF, width); - - /* Config height */ - clrsetbits_le32(&disp_rdma[0]->size_con_1, 0xFFFFF, height); - - /* - * Enable FIFO underflow since DSI and DPI can't be blocked. Keep the - * FIFO pseudo size reset default of 8 KiB. Set the output threshold to - * 6 microseconds with 7/6 overhead to account for blanking, and with a - * pixel depth of 4 bytes: - */ - - threshold = pixel_clk * 4 * 7 / 1000; - - reg = RDMA_FIFO_UNDERFLOW_EN | - RDMA_FIFO_PSEUDO_SIZE(8 * KiB) | - RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); - - write32(&disp_rdma[0]->fifo_con, reg); -} - static void od_start(u32 width, u32 height) { write32(&disp_od->size, width << 16 | height); @@ -105,80 +47,19 @@ static void od_start(u32 width, u32 height) write32(&disp_od->en, 1); } -static void ufoe_start(u32 width, u32 height, bool dual_dsi_mode) +static void main_disp_path_setup(u32 width, u32 height, u32 pixel_clk) { - if (dual_dsi_mode) { - write32(&disp_ufoe->frame_width, width); - write32(&disp_ufoe->frame_height, height); - write32(&disp_ufoe->start, UFO_LR); - } else { - write32(&disp_ufoe->start, UFO_BYPASS); - } -} - -static void color_start(u32 width, u32 height) -{ - write32(&disp_color[0]->width, width); - write32(&disp_color[0]->height, height); - write32(&disp_color[0]->cfg_main, COLOR_BYPASS_ALL | COLOR_SEQ_SEL); - write32(&disp_color[0]->start, BIT(0)); -} - -static void split_start(void) -{ - write32(&disp_split->start, 1); -} - -static void ovl_layer_config(u32 fmt, u32 bpp, u32 width, u32 height) -{ - write32(&disp_ovl[0]->layer[0].con, fmt << 12); - write32(&disp_ovl[0]->layer[0].src_size, height << 16 | width); - write32(&disp_ovl[0]->layer[0].pitch, (width * bpp) & 0xFFFF); - - ovl_layer_enable(); -} - -static void main_disp_path_setup(u32 width, u32 height, u32 pixel_clk, - bool dual_dsi_mode) -{ - /* Setup OVL */ - ovl_set_roi(width, height, 0); - - /* Setup RDMA0 */ - rdma_config(width, height, pixel_clk); - - /* Setup OD */ + ovl_set_roi(0, width, height, 0); + rdma_config(width, height, pixel_clk, 8 * KiB); od_start(width, height); - - /* Setup UFOE */ - ufoe_start(width, height, dual_dsi_mode); - - if (dual_dsi_mode) - split_start(); - - /* Setup Color */ + write32(&disp_ufoe->start, UFO_BYPASS); color_start(width, height); - - /* Setup main path connection */ - disp_config_main_path_connection(dual_dsi_mode); - - /* Setup main path mutex */ + disp_config_main_path_connection(); disp_config_main_path_mutex(); } -static void disp_clock_on(bool dual_dsi_mode) +static void disp_clock_on(void) { - u32 dual_dsi_cg_con0; - u32 dual_dsi_cg_con1; - - if (dual_dsi_mode) { - dual_dsi_cg_con0 = CG_CON0_DISP_SPLIT1; - dual_dsi_cg_con1 = CG_CON1_DSI1_ENGINE | CG_CON1_DSI1_DIGITAL; - } else { - dual_dsi_cg_con0 = 0; - dual_dsi_cg_con1 = 0; - } - clrbits_le32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_SMI_COMMON | CG_CON0_SMI_LARB0 | CG_CON0_MUTEX_32K | @@ -186,28 +67,25 @@ static void disp_clock_on(bool dual_dsi_mode) CG_CON0_DISP_RDMA0 | CG_CON0_DISP_COLOR0 | CG_CON0_DISP_UFOE | - dual_dsi_cg_con0 | CG_CON0_DISP_OD); clrbits_le32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DSI0_ENGINE | - CG_CON1_DSI0_DIGITAL | - dual_dsi_cg_con1); + CG_CON1_DSI0_DIGITAL); } -void mtk_ddp_init(bool dual_dsi_mode) +void mtk_ddp_init(void) { - disp_clock_on(dual_dsi_mode); + disp_clock_on(); } -void mtk_ddp_mode_set(const struct edid *edid, bool dual_dsi_mode) +void mtk_ddp_mode_set(const struct edid *edid) { u32 fmt = OVL_INFMT_RGBA8888; u32 bpp = edid->framebuffer_bits_per_pixel / 8; main_disp_path_setup(edid->mode.ha, edid->mode.va, - edid->mode.pixel_clock, dual_dsi_mode); + edid->mode.pixel_clock); rdma_start(); - ovl_layer_config(fmt, bpp, edid->mode.ha, edid->mode.va); } diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c index b2279ea9bf..5b96a582b7 100644 --- a/src/soc/mediatek/mt8173/dsi.c +++ b/src/soc/mediatek/mt8173/dsi.c @@ -17,78 +17,9 @@ #include #include #include -#include -#include #include -#include #include -static bool dual_dsi_mode; - -static void mipi_write32(void *a, uint32_t v) -{ - void *a1 = a + (MIPI_TX1_BASE - MIPI_TX0_BASE); - write32(a, v); - if (dual_dsi_mode) - write32(a1, v); -} - -static void mipi_clrsetbits_le32(void *a, uint32_t m, uint32_t v) -{ - void *a1 = a + (MIPI_TX1_BASE - MIPI_TX0_BASE); - clrsetbits_le32(a, m, v); - if (dual_dsi_mode) - clrsetbits_le32(a1, m, v); -} - -static void mipi_clrbits_le32(void *a, uint32_t m) -{ - void *a1 = a + (MIPI_TX1_BASE - MIPI_TX0_BASE); - clrbits_le32(a, m); - if (dual_dsi_mode) - clrbits_le32(a1, m); -} - -static void mipi_setbits_le32(void *a, uint32_t m) -{ - void *a1 = a + (MIPI_TX1_BASE - MIPI_TX0_BASE); - setbits_le32(a, m); - if (dual_dsi_mode) - setbits_le32(a1, m); -} - -static void dsi_write32(void *a, uint32_t v) -{ - void *a1 = a + (DSI1_BASE - DSI0_BASE); - write32(a, v); - if (dual_dsi_mode) - write32(a1, v); -} - -static void dsi_clrsetbits_le32(void *a, uint32_t m, uint32_t v) -{ - void *a1 = a + (DSI1_BASE - DSI0_BASE); - clrsetbits_le32(a, m, v); - if (dual_dsi_mode) - clrsetbits_le32(a1, m, v); -} - -static void dsi_clrbits_le32(void *a, uint32_t m) -{ - void *a1 = a + (DSI1_BASE - DSI0_BASE); - clrbits_le32(a, m); - if (dual_dsi_mode) - clrbits_le32(a1, m); -} - -static void dsi_setbits_le32(void *a, uint32_t m) -{ - void *a1 = a + (DSI1_BASE - DSI0_BASE); - setbits_le32(a, m); - if (dual_dsi_mode) - setbits_le32(a1, m); -} - static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes, const struct edid *edid) { @@ -108,19 +39,19 @@ static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes, reg = (reg & (~RG_DSI_V12_SEL)) | (4 << 5); reg |= RG_DSI_BG_CKEN; reg |= RG_DSI_BG_CORE_EN; - mipi_write32(&mipi_tx0->dsi_bg_con, reg); + write32(&mipi_tx0->dsi_bg_con, reg); udelay(30); - mipi_clrsetbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE, + clrsetbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE, 8 << 4 | RG_DSI_LNT_HS_BIAS_EN); - mipi_setbits_le32(&mipi_tx0->dsi_con, + setbits_le32(&mipi_tx0->dsi_con, RG_DSI0_CKG_LDOOUT_EN | RG_DSI0_LDOCORE_EN); - mipi_clrsetbits_le32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN, + clrsetbits_le32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN, RG_DSI_MPPLL_SDM_PWR_ON); - mipi_clrbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); + clrbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); switch (format) { case MIPI_DSI_FMT_RGB565: @@ -146,8 +77,6 @@ static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes, data_rate = edid->mode.pixel_clock * 102 * bit_per_pixel / (lanes * 1000 * 100); mipi_tx_rate = data_rate; - if (dual_dsi_mode) - data_rate /= 2; if (data_rate > 500) { txdiv0 = 0; @@ -171,7 +100,7 @@ static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes, return -1; } - mipi_clrsetbits_le32(&mipi_tx0->dsi_pll_con0, + clrsetbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_TXDIV1 | RG_DSI0_MPPLL_TXDIV0 | RG_DSI0_MPPLL_PREDIV, txdiv1 << 5 | txdiv0 << 3); @@ -185,21 +114,21 @@ static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes, */ pcw = (u64)(data_rate * (1 << txdiv0) * (1 << txdiv1)) << 24; pcw /= 13; - mipi_write32(&mipi_tx0->dsi_pll_con2, pcw); + write32(&mipi_tx0->dsi_pll_con2, pcw); - mipi_setbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN); + setbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN); - mipi_setbits_le32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN); + setbits_le32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN); for (i = 0; i < lanes; i++) - mipi_setbits_le32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN); + setbits_le32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN); - mipi_setbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); + setbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); udelay(40); - mipi_clrbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN); - mipi_clrbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN); + clrbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN); + clrbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN); return mipi_tx_rate; } @@ -222,26 +151,26 @@ static void mtk_dsi_phy_timconfig(u32 data_rate) DIV_ROUND_UP(80 + 52 * ui, cycle_time) << 8 | DIV_ROUND_UP(0x40, cycle_time); - dsi_write32(&dsi0->dsi_phy_timecon0, timcon0); - dsi_write32(&dsi0->dsi_phy_timecon1, timcon1); - dsi_write32(&dsi0->dsi_phy_timecon2, timcon2); - dsi_write32(&dsi0->dsi_phy_timecon3, timcon3); + write32(&dsi0->dsi_phy_timecon0, timcon0); + write32(&dsi0->dsi_phy_timecon1, timcon1); + write32(&dsi0->dsi_phy_timecon2, timcon2); + write32(&dsi0->dsi_phy_timecon3, timcon3); } static void mtk_dsi_reset(void) { - dsi_setbits_le32(&dsi0->dsi_con_ctrl, 3); - dsi_clrbits_le32(&dsi0->dsi_con_ctrl, 1); + setbits_le32(&dsi0->dsi_con_ctrl, 3); + clrbits_le32(&dsi0->dsi_con_ctrl, 1); } static void mtk_dsi_clk_hs_mode_enable(void) { - dsi_setbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); + setbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); } static void mtk_dsi_clk_hs_mode_disable(void) { - dsi_clrbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); + clrbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); } static void mtk_dsi_set_mode(u32 mode_flags) @@ -258,7 +187,7 @@ static void mtk_dsi_set_mode(u32 mode_flags) tmp_reg1 = SYNC_PULSE_MODE; } - dsi_write32(&dsi0->dsi_mode_ctrl, tmp_reg1); + write32(&dsi0->dsi_mode_ctrl, tmp_reg1); } static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes) @@ -284,7 +213,7 @@ static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes) tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; - dsi_write32(&dsi0->dsi_txrx_ctrl, tmp_reg); + write32(&dsi0->dsi_txrx_ctrl, tmp_reg); } static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, @@ -308,10 +237,10 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, edid->mode.vborder; vfp_byte = edid->mode.vso - edid->mode.vborder; - dsi_write32(&dsi0->dsi_vsa_nl, edid->mode.vspw); - dsi_write32(&dsi0->dsi_vbp_nl, vbp_byte); - dsi_write32(&dsi0->dsi_vfp_nl, vfp_byte); - dsi_write32(&dsi0->dsi_vact_nl, edid->mode.va); + write32(&dsi0->dsi_vsa_nl, edid->mode.vspw); + write32(&dsi0->dsi_vbp_nl, vbp_byte); + write32(&dsi0->dsi_vfp_nl, vfp_byte); + write32(&dsi0->dsi_vact_nl, edid->mode.va); if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) hbp_byte = (edid->mode.hbl - edid->mode.hso - edid->mode.hspw - @@ -323,9 +252,9 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, hsync_active_byte = edid->mode.hspw * bpp - 10; hfp_byte = (edid->mode.hso - edid->mode.hborder) * bpp - 12; - dsi_write32(&dsi0->dsi_hsa_wc, hsync_active_byte); - dsi_write32(&dsi0->dsi_hbp_wc, hbp_byte); - dsi_write32(&dsi0->dsi_hfp_wc, hfp_byte); + write32(&dsi0->dsi_hsa_wc, hsync_active_byte); + write32(&dsi0->dsi_hbp_wc, hbp_byte); + write32(&dsi0->dsi_hfp_wc, hfp_byte); switch (format) { case MIPI_DSI_FMT_RGB888: @@ -346,60 +275,22 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, } hactive = edid->mode.ha; - if (dual_dsi_mode) - hactive /= 2; packet_fmt |= (hactive * bpp) & DSI_PS_WC; - dsi_write32(&dsi0->dsi_psctrl, packet_fmt); + write32(&dsi0->dsi_psctrl, packet_fmt); } static void mtk_dsi_start(void) { - dsi_write32(&dsi0->dsi_start, 0); + write32(&dsi0->dsi_start, 0); /* Only start master DSI */ write32(&dsi0->dsi_start, 1); } -static void mtk_dsi_tx_cmd_type0(u8 cmd) -{ - struct stopwatch sw; - u32 cmdq0; - u32 intsta_0, intsta_1; - - cmdq0 = (MIPI_DSI_DCS_SHORT_WRITE << 8) | SHORT_PACKET | (cmd << 16); - - dsi_write32(&dsi0->dsi_cmdq0, cmdq0); - dsi_clrsetbits_le32(&dsi0->dsi_cmdq_size, CMDQ_SIZE, 1); - dsi_write32(&dsi0->dsi_intsta, 0); - - dsi_write32(&dsi0->dsi_start, 1); - - stopwatch_init_usecs_expire(&sw, 400); - do { - intsta_0 = read32(&dsi0->dsi_intsta); - intsta_1 = read32(&dsi1->dsi_intsta); - if ((intsta_0 & CMD_DONE_INT_FLAG) && - (intsta_1 & CMD_DONE_INT_FLAG)) - break; - udelay(4); - } while (!stopwatch_expired(&sw)); - - if (!(intsta_0 & CMD_DONE_INT_FLAG)) - printk(BIOS_ERR, "DSI0 DONE INT Timeout\n"); - - if (!(intsta_1 & CMD_DONE_INT_FLAG)) - printk(BIOS_ERR, "DSI1 DONE INT Timeout\n"); - - dsi_write32(&dsi0->dsi_start, 0); -} - -int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual, - const struct edid *edid) +int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid) { int data_rate; - dual_dsi_mode = dual; - data_rate = mtk_dsi_phy_clk_setting(format, lanes, edid); if (data_rate < 0) @@ -413,21 +304,6 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual, mtk_dsi_set_mode(mode_flags); mtk_dsi_clk_hs_mode_enable(); - if (dual_dsi_mode) { - dsi_write32(&dsi0->dsi_start, 0); - /* Disable dual_dsi when in CMD_MODE */ - dsi_write32(&dsi0->dsi_con_ctrl, DSI_EN); - - dsi_write32(&dsi0->dsi_mode_ctrl, CMD_MODE); - - mtk_dsi_tx_cmd_type0(MIPI_DCS_EXIT_SLEEP_MODE); - mtk_dsi_tx_cmd_type0(MIPI_DCS_SET_DISPLAY_ON); - - dsi_write32(&dsi0->dsi_con_ctrl, DSI_EN | DSI_DUAL); - - dsi_write32(&dsi0->dsi_mode_ctrl, BURST_MODE); - } - mtk_dsi_start(); return 0; @@ -438,7 +314,7 @@ void mtk_dsi_pin_drv_ctrl(void) struct stopwatch sw; uint32_t pwr_ack; - mipi_setbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDSTX_PWR_ON); + setbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDSTX_PWR_ON); stopwatch_init_usecs_expire(&sw, 1000); @@ -448,10 +324,7 @@ void mtk_dsi_pin_drv_ctrl(void) return; } pwr_ack = read32(&lvds_tx1->vopll_ctl3) & RG_AD_LVDSTX_PWR_ACK; - if (dual_dsi_mode) - pwr_ack &= read32(&lvds_tx2->vopll_ctl3) & - RG_AD_LVDSTX_PWR_ACK; } while (pwr_ack == 0); - mipi_clrbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDS_ISO_EN); + clrbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDS_ISO_EN); } diff --git a/src/soc/mediatek/mt8173/flash_controller.c b/src/soc/mediatek/mt8173/flash_controller.c index bca2ecf98d..b491a41efd 100644 --- a/src/soc/mediatek/mt8173/flash_controller.c +++ b/src/soc/mediatek/mt8173/flash_controller.c @@ -21,12 +21,12 @@ #include #include #include -#include #include #include #include #include #include +#include #define get_nth_byte(d, n) ((d >> (8 * n)) & 0xff) diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index 3395539bf1..67de335ebf 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -23,11 +23,13 @@ #include #include #include +#include #include +#include #define I2C_CLK_HZ (AXI_HZ / 16) -static struct mtk_i2c i2c[7] = { +struct mtk_i2c mtk_i2c_bus_controller[7] = { /* i2c0 setting */ { .i2c_regs = (void *)I2C_BASE, @@ -79,267 +81,21 @@ static struct mtk_i2c i2c[7] = { #define I2CERR(fmt, arg...) printk(BIOS_ERR, I2CTAG fmt, ##arg) -static inline void i2c_dma_reset(struct mt8173_i2c_dma_regs *dma_regs) -{ - write32(&dma_regs->dma_rst, 0x1); - udelay(50); - write32(&dma_regs->dma_rst, 0x2); - udelay(50); - write32(&dma_regs->dma_rst, 0x0); - udelay(50); -} - void mtk_i2c_bus_init(uint8_t bus) { - uint8_t sample_div; uint8_t step_div; uint32_t i2c_freq; + const uint8_t sample_div = 1; - assert(bus < ARRAY_SIZE(i2c)); + assert(bus < ARRAY_SIZE(mtk_i2c_bus_controller)); /* Calculate i2c frequency */ - sample_div = 1; step_div = DIV_ROUND_UP(I2C_CLK_HZ, (400 * KHz * sample_div * 2)); i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2); assert(sample_div < 8 && step_div < 64 && i2c_freq < 400 * KHz && i2c_freq >= 380 * KHz); /* Init i2c bus Timing register */ - write32(&i2c[bus].i2c_regs->timing, (sample_div - 1) << 8 | - (step_div - 1)); -} - -static inline void mtk_i2c_dump_info(uint8_t bus) -{ - struct mt8173_i2c_regs *regs; - - regs = i2c[bus].i2c_regs; - - I2CLOG("I2C register:\nSLAVE_ADDR %x\nINTR_MASK %x\nINTR_STAT %x\n" - "CONTROL %x\nTRANSFER_LEN %x\nTRANSAC_LEN %x\nDELAY_LEN %x\n" - "TIMING %x\nSTART %x\nFIFO_STAT %x\nIO_CONFIG %x\nHS %x\n" - "DEBUGSTAT %x\nEXT_CONF %x\n", - (read32(®s->salve_addr)), - (read32(®s->intr_mask)), - (read32(®s->intr_stat)), - (read32(®s->control)), - (read32(®s->transfer_len)), - (read32(®s->transac_len)), - (read32(®s->delay_len)), - (read32(®s->timing)), - (read32(®s->start)), - (read32(®s->fifo_stat)), - (read32(®s->io_config)), - (read32(®s->hs)), - (read32(®s->debug_stat)), - (read32(®s->ext_conf))); - - I2CLOG("addr address %x\n", (uint32_t)regs); -} - -static uint32_t mtk_i2c_transfer(uint8_t bus, struct i2c_msg *seg, - enum i2c_modes read) -{ - uint32_t ret_code = I2C_OK; - uint16_t status; - uint32_t time_out_val = 0; - uint8_t addr; - uint32_t write_len = 0; - uint32_t read_len = 0; - uint8_t *write_buffer = NULL; - uint8_t *read_buffer = NULL; - struct mt8173_i2c_regs *regs; - struct mt8173_i2c_dma_regs *dma_regs; - struct stopwatch sw; - - regs = i2c[bus].i2c_regs; - dma_regs = i2c[bus].i2c_dma_regs; - - addr = seg[0].slave; - - switch (read) { - case I2C_WRITE_MODE: - assert(seg[0].len > 0 && seg[0].len <= 255); - write_len = seg[0].len; - write_buffer = seg[0].buf; - break; - - case I2C_READ_MODE: - assert(seg[0].len > 0 && seg[0].len <= 255); - read_len = seg[0].len; - read_buffer = seg[0].buf; - break; - - /* Must use special write-then-read mode for repeated starts. */ - case I2C_WRITE_READ_MODE: - assert(seg[0].len > 0 && seg[0].len <= 255); - assert(seg[1].len > 0 && seg[1].len <= 255); - write_len = seg[0].len; - read_len = seg[1].len; - write_buffer = seg[0].buf; - read_buffer = seg[1].buf; - break; - } - - /* Clear interrupt status */ - write32(®s->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR | - I2C_HS_NACKERR); - - write32(®s->fifo_addr_clr, 0x1); - - /* Enable interrupt */ - write32(®s->intr_mask, I2C_HS_NACKERR | I2C_ACKERR | - I2C_TRANSAC_COMP); - - switch (read) { - case I2C_WRITE_MODE: - memcpy(_dma_coherent, write_buffer, write_len); - - /* control registers */ - write32(®s->control, ACK_ERR_DET_EN | DMA_EN | CLK_EXT | - REPEATED_START_FLAG); - - /* Set transfer and transaction len */ - write32(®s->transac_len, 1); - write32(®s->transfer_len, write_len); - - /* set i2c write slave address*/ - write32(®s->slave_addr, addr << 1); - - /* Prepare buffer data to start transfer */ - write32(&dma_regs->dma_con, I2C_DMA_CON_TX); - write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); - write32(&dma_regs->dma_tx_len, write_len); - break; - - case I2C_READ_MODE: - /* control registers */ - write32(®s->control, ACK_ERR_DET_EN | DMA_EN | CLK_EXT | - REPEATED_START_FLAG); - - /* Set transfer and transaction len */ - write32(®s->transac_len, 1); - write32(®s->transfer_len, read_len); - - /* set i2c read slave address*/ - write32(®s->slave_addr, (addr << 1 | 0x1)); - - /* Prepare buffer data to start transfer */ - write32(&dma_regs->dma_con, I2C_DMA_CON_RX); - write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); - write32(&dma_regs->dma_rx_len, read_len); - break; - - case I2C_WRITE_READ_MODE: - memcpy(_dma_coherent, write_buffer, write_len); - - /* control registers */ - write32(®s->control, DIR_CHG | ACK_ERR_DET_EN | DMA_EN | - CLK_EXT | REPEATED_START_FLAG); - - /* Set transfer and transaction len */ - write32(®s->transfer_len, write_len); - write32(®s->transfer_aux_len, read_len); - write32(®s->transac_len, 2); - - /* set i2c write slave address*/ - write32(®s->slave_addr, addr << 1); - - /* Prepare buffer data to start transfer */ - write32(&dma_regs->dma_con, I2C_DMA_CLR_FLAG); - write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); - write32(&dma_regs->dma_tx_len, write_len); - write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); - write32(&dma_regs->dma_rx_len, read_len); - break; - } - - write32(&dma_regs->dma_int_flag, I2C_DMA_CLR_FLAG); - write32(&dma_regs->dma_en, I2C_DMA_START_EN); - - /* start transfer transaction */ - write32(®s->start, 0x1); - - stopwatch_init_msecs_expire(&sw, 100); - - /* polling mode : see if transaction complete */ - while (1) { - status = read32(®s->intr_stat); - if (status & I2C_HS_NACKERR) { - ret_code = I2C_TRANSFER_FAIL_HS_NACKERR; - I2CERR("[i2c%d transfer] transaction NACK error\n", - bus); - mtk_i2c_dump_info(bus); - break; - } else if (status & I2C_ACKERR) { - ret_code = I2C_TRANSFER_FAIL_ACKERR; - I2CERR("[i2c%d transfer] transaction ACK error\n", bus); - mtk_i2c_dump_info(bus); - break; - } else if (status & I2C_TRANSAC_COMP) { - ret_code = I2C_OK; - memcpy(read_buffer, _dma_coherent, read_len); - break; - } - - if (stopwatch_expired(&sw)) { - ret_code = I2C_TRANSFER_FAIL_TIMEOUT; - I2CERR("[i2c%d transfer] transaction timeout:%d\n", bus, - time_out_val); - mtk_i2c_dump_info(bus); - break; - } - } - - write32(®s->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR | - I2C_HS_NACKERR); - - /* clear bit mask */ - write32(®s->intr_mask, I2C_HS_NACKERR | I2C_ACKERR | - I2C_TRANSAC_COMP); - - /* reset the i2c controller for next i2c transfer. */ - write32(®s->softreset, 0x1); - - i2c_dma_reset(dma_regs); - - return ret_code; -} - -static uint8_t mtk_i2c_should_combine(struct i2c_msg *seg, int left_count) -{ - if (left_count >= 2 && - !(seg[0].flags & I2C_M_RD) && - (seg[1].flags & I2C_M_RD) && - seg[0].slave == seg[1].slave) - return 1; - else - return 0; -} - -int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments, - int seg_count) -{ - int ret = 0; - int i; - int read; - - for (i = 0; i < seg_count; i++) { - if (mtk_i2c_should_combine(&segments[i], seg_count - i)) { - read = I2C_WRITE_READ_MODE; - } else { - read = (segments[i].flags & I2C_M_RD) ? - I2C_READ_MODE : I2C_WRITE_MODE; - } - - ret = mtk_i2c_transfer(bus, &segments[i], read); - - if (ret) - break; - - if (read == I2C_WRITE_READ_MODE) - i++; - } - - return ret; + write32(&mtk_i2c_bus_controller[bus].i2c_regs->timing, + (sample_div - 1) << 8 | (step_div - 1)); } diff --git a/src/soc/mediatek/mt8173/include/soc/addressmap.h b/src/soc/mediatek/mt8173/include/soc/addressmap.h index 0ebe3d1c6d..90834a3ca9 100644 --- a/src/soc/mediatek/mt8173/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8173/include/soc/addressmap.h @@ -56,8 +56,8 @@ enum { SSUSB_IPPC_BASE = IO_PHYS + 0x1280700, SSUSB_SIF_BASE = IO_PHYS + 0x1290800, MMSYS_BASE = IO_PHYS + 0x4000000, - DIS_OVL0_BASE = IO_PHYS + 0x400C000, - DIS_OVL1_BASE = IO_PHYS + 0x400D000, + DISP_OVL0_BASE = IO_PHYS + 0x400C000, + DISP_OVL1_BASE = IO_PHYS + 0x400D000, DISP_RDMA0_BASE = IO_PHYS + 0x400E000, DISP_RDMA1_BASE = IO_PHYS + 0x400F000, DISP_RDMA2_BASE = IO_PHYS + 0x4010000, diff --git a/src/soc/mediatek/mt8173/include/soc/ddp.h b/src/soc/mediatek/mt8173/include/soc/ddp.h index 0bd832e90f..dbac5f7fb9 100644 --- a/src/soc/mediatek/mt8173/include/soc/ddp.h +++ b/src/soc/mediatek/mt8173/include/soc/ddp.h @@ -13,10 +13,11 @@ * GNU General Public License for more details. */ -#ifndef _DDP_REG_H_ -#define _DDP_REG_H_ +#ifndef _MT8173_SOC_DDP_H_ +#define _MT8173_SOC_DDP_H_ #include +#include #include struct mmsys_cfg_regs { @@ -254,100 +255,6 @@ enum { MUTEX_MOD_DISP_UFOE | MUTEX_MOD_DISP_OD, }; -struct disp_ovl_regs { - u32 sta; - u32 inten; - u32 intsta; - u32 en; - u32 trig; - u32 rst; - u8 reserved0[8]; - u32 roi_size; - u32 datapath_con; - u32 roi_bgclr; - u32 src_con; - struct { - u32 con; - u32 srckey; - u32 src_size; - u32 offset; - u32 reserved0; - u32 pitch; - u32 reserved1[2]; - } layer[4]; - u8 reserved8[16]; - struct { - u32 ctrl; - u32 mem_start_trig; - u32 mem_gmc_setting; - u32 mem_slow_con; - u32 fifo_ctrl; - u8 reserved[12]; - } rdma[4]; - u8 reserved12[148]; - u32 debug_mon_sel; - u8 reserved13[8]; - u32 rdma_mem_gmc_setting2[4]; - u8 reserved14[16]; - u32 dummy; - u8 reserved15[60]; - u32 flow_ctrl_dbg; - u32 addcon_dbg; - u32 outmux_dbg; - u32 rdma_dbg[4]; - u8 reserved16[3300]; - u32 l0_addr; - u8 reserved17[28]; - u32 l1_addr; - u8 reserved18[28]; - u32 l2_addr; - u8 reserved19[28]; - u32 l3_addr; -}; - -check_member(disp_ovl_regs, l3_addr, 0xFA0); -static struct disp_ovl_regs *const disp_ovl[2] = { - (void *)DIS_OVL0_BASE, (void *)DIS_OVL1_BASE -}; - -struct disp_rdma_regs { - u32 int_enable; - u32 int_status; - u8 reserved0[8]; - u32 global_con; - u32 size_con_0; - u32 size_con_1; - u32 target_line; - u8 reserved1[4]; - u32 mem_con; - u32 mem_start_addr; - u32 mem_src_pitch; - u32 mem_gmc_setting_0; - u32 mem_slow_con; - u32 mem_gmc_setting_1; - u8 reserved2[4]; - u32 fifo_con; - u8 reserved3[16]; - u32 cf[3][3]; - u32 cf_pre_add[3]; - u32 cf_post_add[3]; - u32 dummy; - u32 debug_out_sel; -}; - -enum { - RDMA_ENGINE_EN = BIT(0), - RDMA_FIFO_UNDERFLOW_EN = BIT(31), - RDMA_MEM_GMC = 0x40402020, -}; - -check_member(disp_rdma_regs, debug_out_sel, 0x94); -static struct disp_rdma_regs *const disp_rdma[3] = { - (void *)DISP_RDMA0_BASE, - (void *)DISP_RDMA1_BASE, - (void *)DISP_RDMA2_BASE -}; - struct disp_od_regs { u32 en; u32 reset; @@ -407,52 +314,7 @@ enum { UFO_LR = BIT(3) | BIT(0), }; -struct disp_split_regs { - u32 start; -}; - -static struct disp_split_regs *const disp_split = (void *)DISP_SPLIT1_BASE; - -struct disp_color_regs { - u8 reserved0[1024]; - u32 cfg_main; - u8 reserved1[2044]; - u32 start; - u8 reserved2[76]; - u32 width; - u32 height; -}; - -check_member(disp_color_regs, cfg_main, 0x400); -check_member(disp_color_regs, start, 0xC00); -check_member(disp_color_regs, width, 0xC50); -check_member(disp_color_regs, height, 0xC54); -static struct disp_color_regs *const disp_color[2] = { - (void *)DISP_COLOR0_BASE, (void *)DISP_COLOR1_BASE -}; - -enum { - COLOR_BYPASS_ALL = BIT(7), - COLOR_SEQ_SEL = BIT(13), -}; - -enum OVL_INPUT_FORMAT { - OVL_INFMT_RGB565 = 0, - OVL_INFMT_RGB888 = 1, - OVL_INFMT_RGBA8888 = 2, - OVL_INFMT_ARGB8888 = 3, - OVL_INFMT_UYVY = 4, - OVL_INFMT_YUYV = 5, - OVL_INFMT_UNKNOWN = 16, - - OVL_COLOR_BASE = 30, - OVL_INFMT_BGR565 = OVL_INFMT_RGB565 + OVL_COLOR_BASE, - OVL_INFMT_BGR888 = OVL_INFMT_RGB888 + OVL_COLOR_BASE, - OVL_INFMT_BGRA8888 = OVL_INFMT_RGBA8888 + OVL_COLOR_BASE, - OVL_INFMT_ABGR8888 = OVL_INFMT_ARGB8888 + OVL_COLOR_BASE, -}; - -void mtk_ddp_init(bool dual_dsi_mode); -void mtk_ddp_mode_set(const struct edid *edid, bool dual_dsi_mode); +void mtk_ddp_init(void); +void mtk_ddp_mode_set(const struct edid *edid); #endif diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h index ca35bd1759..967ed4d27e 100644 --- a/src/soc/mediatek/mt8173/include/soc/dsi.h +++ b/src/soc/mediatek/mt8173/include/soc/dsi.h @@ -443,7 +443,7 @@ enum { }; int mtk_dsi_init(u32 mode_flags, enum mipi_dsi_pixel_format format, u32 lanes, - bool dual_dsi_mode, const struct edid *edid); + const struct edid *edid); void mtk_dsi_pin_drv_ctrl(void); #endif diff --git a/src/soc/mediatek/mt8173/include/soc/i2c.h b/src/soc/mediatek/mt8173/include/soc/i2c.h index 5f46e9cad5..619893489a 100644 --- a/src/soc/mediatek/mt8173/include/soc/i2c.h +++ b/src/soc/mediatek/mt8173/include/soc/i2c.h @@ -16,47 +16,10 @@ #ifndef SOC_MEDIATEK_MT8173_I2C_H #define SOC_MEDIATEK_MT8173_I2C_H -#include - -/* I2C Configuration */ -enum { - I2C_HS_DEFAULT_VALUE = 0x0102, -}; - -enum i2c_modes { - I2C_WRITE_MODE = 0, - I2C_READ_MODE = 1, - I2C_WRITE_READ_MODE = 2, -}; - -enum { - I2C_DMA_CON_TX = 0x0, - I2C_DMA_CON_RX = 0x1, - I2C_DMA_START_EN = 0x1, - I2C_DMA_INT_FLAG_NONE = 0x0, - I2C_DMA_CLR_FLAG = 0x0, - I2C_DMA_FLUSH_FLAG = 0x1, -}; - -/* I2C DMA Registers */ -struct mt8173_i2c_dma_regs { - uint32_t dma_int_flag; - uint32_t dma_int_en; - uint32_t dma_en; - uint32_t dma_rst; - uint32_t reserved1; - uint32_t dma_flush; - uint32_t dma_con; - uint32_t dma_tx_mem_addr; - uint32_t dma_rx_mem_addr; - uint32_t dma_tx_len; - uint32_t dma_rx_len; -}; - -check_member(mt8173_i2c_dma_regs, dma_tx_len, 0x24); +#include /* I2C Register */ -struct mt8173_i2c_regs { +struct mt_i2c_regs { uint32_t data_port; uint32_t slave_addr; uint32_t intr_mask; @@ -85,47 +48,7 @@ struct mt8173_i2c_regs { uint32_t transfer_aux_len; }; -check_member(mt8173_i2c_regs, debug_stat, 0x64); - -struct mtk_i2c { - struct mt8173_i2c_regs *i2c_regs; - struct mt8173_i2c_dma_regs *i2c_dma_regs; -}; - -enum { - I2C_TRANS_LEN_MASK = (0xff), - I2C_TRANS_AUX_LEN_MASK = (0x1f << 8), - I2C_CONTROL_MASK = (0x3f << 1) -}; - -/* Register mask */ -enum { - I2C_HS_NACKERR = (1 << 2), - I2C_ACKERR = (1 << 1), - I2C_TRANSAC_COMP = (1 << 0), -}; - -/* i2c control bits */ -enum { - ACK_ERR_DET_EN = (1 << 5), - DIR_CHG = (1 << 4), - CLK_EXT = (1 << 3), - DMA_EN = (1 << 2), - REPEATED_START_FLAG = (1 << 1), - STOP_FLAG = (0 << 1) -}; - -/* I2C Status Code */ - -enum { - I2C_OK = 0x0000, - I2C_SET_SPEED_FAIL_OVER_SPEED = 0xA001, - I2C_TRANSFER_INVALID_LENGTH = 0xA002, - I2C_TRANSFER_FAIL_HS_NACKERR = 0xA003, - I2C_TRANSFER_FAIL_ACKERR = 0xA004, - I2C_TRANSFER_FAIL_TIMEOUT = 0xA005, - I2C_TRANSFER_INVALID_ARGUMENT = 0xA006 -}; +check_member(mt_i2c_regs, debug_stat, 0x64); void mtk_i2c_bus_init(uint8_t bus); diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index d35a07ed59..45276835af 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -6,6 +6,7 @@ bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += mt8183.c +bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/timer.c bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c @@ -18,6 +19,7 @@ verstage-y += auxadc.c verstage-y += ../common/gpio.c gpio.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += mt8183.c +verstage-y += ../common/i2c.c i2c.c verstage-y += ../common/timer.c verstage-y += ../common/uart.c verstage-y += ../common/wdt.c @@ -36,23 +38,33 @@ romstage-y += ../common/pll.c pll.c romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c romstage-y += ../common/rtc.c rtc.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/timer.c romstage-y += ../common/uart.c romstage-y += ../common/wdt.c ramstage-y += auxadc.c ramstage-y += ../common/cbmem.c emi.c +ramstage-y += ../common/ddp.c ddp.c ramstage-y += ../common/gpio.c gpio.c +ramstage-y += ../common/i2c.c i2c.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += ../common/pmic_wrap.c ramstage-y += ../common/rtc.c rtc.c ramstage-y += soc.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +ramstage-y += sspm.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c ramstage-y += ../common/wdt.c +ramstage-y += md_ctrl.c + +cbfs-files-y += sspm.bin +sspm.bin-file := 3rdparty/blobs/soc/mediatek/mt8183/sspm.bin +sspm.bin-type := raw +sspm.bin-compression := $(CBFS_COMPRESS_FLAG) CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c new file mode 100644 index 0000000000..0ae0be1815 --- /dev/null +++ b/src/soc/mediatek/mt8183/ddp.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +static void disp_config_main_path_connection(void) +{ + write32(&mmsys_cfg->disp_ovl0_mout_en, OVL0_MOUT_EN_OVL0_2L); + write32(&mmsys_cfg->disp_ovl0_2l_mout_en, OVL0_2L_MOUT_EN_DISP_PATH0); + write32(&mmsys_cfg->disp_path0_sel_in, DISP_PATH0_SEL_IN_OVL0_2L); + write32(&mmsys_cfg->disp_rdma0_sout_sel_in, RDMA0_SOUT_SEL_IN_COLOR); + write32(&mmsys_cfg->disp_dither0_mout_en, DITHER0_MOUT_EN_DISP_DSI0); + write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_DITHER0_MOUT); +} + +static void disp_config_main_path_mutex(void) +{ + write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH); + + /* Clock source from DSI0 */ + write32(&disp_mutex->mutex[0].ctl, + MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 6)); + write32(&disp_mutex->mutex[0].en, BIT(0)); +} + +static void ovl_bgclr_in_sel(u32 idx) +{ + setbits_le32(&disp_ovl[idx]->datapath_con, BIT(2)); +} + +static void enable_pq(struct disp_pq_regs *const regs, u32 width, u32 height, + int enable_relay) +{ + write32(®s->size, height << 16 | width); + if (enable_relay) + write32(®s->cfg, PQ_RELAY_MODE); + write32(®s->en, PQ_EN); +} + +static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh) +{ + u32 idx = 0; + u32 pixel_clk = width * height * vrefresh; + + for (idx = 0; idx < MAIN_PATH_OVL_NR; idx++) + ovl_set_roi(idx, width, height, idx ? 0 : 0xff0000ff); + + rdma_config(width, height, pixel_clk, 5 * KiB); + color_start(width, height); + enable_pq(disp_ccorr, width, height, 1); + enable_pq(disp_aal, width, height, 0); + enable_pq(disp_gamma, width, height, 0); + enable_pq(disp_dither, width, height, 1); + disp_config_main_path_connection(); + disp_config_main_path_mutex(); +} + +static void disp_clock_on(void) +{ + clrbits_le32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL); + + clrbits_le32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_DSI0 | + CG_CON1_DISP_DSI0_INTERFACE); +} + +void mtk_ddp_init(void) +{ + disp_clock_on(); + /* Turn off M4U port. */ + write32((void *)(SMI_LARB0 + SMI_LARB_NON_SEC_CON), 0); +} + +void mtk_ddp_mode_set(const struct edid *edid) +{ + u32 fmt = OVL_INFMT_RGBA8888; + u32 bpp = edid->framebuffer_bits_per_pixel / 8; + u32 width = edid->mode.ha; + u32 height = edid->mode.va; + u32 vrefresh = edid->mode.refresh; + + main_disp_path_setup(width, height, vrefresh); + rdma_start(); + ovl_layer_config(fmt, bpp, width, height); + ovl_bgclr_in_sel(1); +} diff --git a/src/soc/mediatek/mt8183/i2c.c b/src/soc/mediatek/mt8183/i2c.c new file mode 100644 index 0000000000..a70c5e175d --- /dev/null +++ b/src/soc/mediatek/mt8183/i2c.c @@ -0,0 +1,150 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#define I2C_CLK_HZ (UNIVPLL_HZ / 20) + +struct mtk_i2c mtk_i2c_bus_controller[] = { + /* i2c0 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x2000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE), + }, + + /* i2c1 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0xc000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x400), + }, + + /* i2c2 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x4000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x200), + }, + + /* i2c3 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0xa000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x380), + }, + + /* i2c4 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x3000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x80), + }, + + /* i2c5 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x11000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x480), + }, + + /* i2c6 setting */ + { + .i2c_regs = (void *)(I2C_BASE), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x580), + }, +}; + +#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller) + +struct pad_func { + gpio_t gpio; + u8 func; +}; + +#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} + +static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = { + { + PAD_FUNC(SDA0, SDA0), + PAD_FUNC(SCL0, SCL0), + }, + { + PAD_FUNC(SDA1, SDA1), + PAD_FUNC(SCL1, SCL1), + }, + { + PAD_FUNC(SDA2, SDA2), + PAD_FUNC(SCL2, SCL2), + }, + { + PAD_FUNC(SDA3, SDA3), + PAD_FUNC(SCL3, SCL3), + }, + { + PAD_FUNC(SDA4, SDA4), + PAD_FUNC(SCL4, SCL4), + }, + { + PAD_FUNC(SDA5, SDA5), + PAD_FUNC(SCL5, SCL5), + }, + { + PAD_FUNC(SDA6, SDA6), + PAD_FUNC(SCL6, SCL6), + }, +}; + +static void mtk_i2c_set_gpio_pinmux(uint8_t bus) +{ + assert(bus < I2C_BUS_NUMBER); + + const struct pad_func *ptr = i2c_funcs[bus]; + for (size_t i = 0; i < 2; i++) { + gpio_set_mode(ptr[i].gpio, ptr[i].func); + gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); + } +} + +static void mtk_i2c_speed_init(uint8_t bus) +{ + uint8_t step_div; + const uint8_t clock_div = 5; + const uint8_t sample_div = 1; + uint32_t i2c_freq; + + assert(bus < ARRAY_SIZE(mtk_i2c_bus_controller)); + + /* Calculate i2c frequency */ + step_div = DIV_ROUND_UP(I2C_CLK_HZ, + (400 * KHz * sample_div * 2) * clock_div); + i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2 * clock_div); + assert(sample_div < 8 && step_div < 64 && i2c_freq <= 400 * KHz && + i2c_freq >= 380 * KHz); + + /* Init i2c bus Timing register */ + write32(&mtk_i2c_bus_controller[bus].i2c_regs->timing, + (sample_div - 1) << 8 | (step_div - 1)); + write32(&mtk_i2c_bus_controller[bus].i2c_regs->ltiming, + (sample_div - 1) << 6 | (step_div - 1)); + + /* Init i2c bus clock_div register */ + write32(&mtk_i2c_bus_controller[bus].i2c_regs->clock_div, + clock_div - 1); +} + +void mtk_i2c_bus_init(uint8_t bus) +{ + mtk_i2c_speed_init(bus); + mtk_i2c_set_gpio_pinmux(bus); +} diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index e9f80d1607..bb44f9bb45 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -34,8 +34,12 @@ enum { EMI_BASE = IO_PHYS + 0x00219000, EMI_MPU_BASE = IO_PHYS + 0x00226000, DRAMC_CH_BASE = IO_PHYS + 0x00228000, + SSPM_SRAM_BASE = IO_PHYS + 0x00400000, + SSPM_CFG_BASE = IO_PHYS + 0x00440000, + I2C_DMA_BASE = IO_PHYS + 0x01000080, AUXADC_BASE = IO_PHYS + 0x01001000, UART0_BASE = IO_PHYS + 0x01002000, + I2C_BASE = IO_PHYS + 0x01005000, SPI0_BASE = IO_PHYS + 0x0100A000, SPI1_BASE = IO_PHYS + 0x01010000, SPI2_BASE = IO_PHYS + 0x01012000, @@ -54,6 +58,19 @@ enum { IOCFG_LT_BASE = IO_PHYS + 0x01F20000, IOCFG_TL_BASE = IO_PHYS + 0x01F30000, SSUSB_SIF_BASE = IO_PHYS + 0x01F40300, + MMSYS_BASE = IO_PHYS + 0x04000000, + DISP_OVL0_BASE = IO_PHYS + 0x04008000, + DISP_OVL1_BASE = IO_PHYS + 0x04009000, + DISP_OVL1_2L_BASE = IO_PHYS + 0x0400A000, + DISP_RDMA0_BASE = IO_PHYS + 0x0400B000, + DISP_RDMA1_BASE = IO_PHYS + 0x0400C000, + DISP_COLOR0_BASE = IO_PHYS + 0x0400E000, + DISP_CCORR0_BASE = IO_PHYS + 0x0400F000, + DISP_AAL0_BASE = IO_PHYS + 0x04010000, + DISP_GAMMA0_BASE = IO_PHYS + 0x04011000, + DISP_DITHER0_BASE = IO_PHYS + 0x04012000, + DISP_MUTEX_BASE = IO_PHYS + 0x04016000, + SMI_LARB0 = IO_PHYS + 0x04017000, SMI_BASE = IO_PHYS + 0x04019000, }; diff --git a/src/soc/mediatek/mt8183/include/soc/ddp.h b/src/soc/mediatek/mt8183/include/soc/ddp.h new file mode 100644 index 0000000000..479417c77e --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/ddp.h @@ -0,0 +1,197 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MT8183_SOC_DDP_H_ +#define _MT8183_SOC_DDP_H_ + +#include +#include +#include + +#define MAIN_PATH_OVL_NR 2 + +struct mmsys_cfg_regs { + u32 reserved_0x000[64]; /* 0x000 */ + u32 mmsys_cg_con0; /* 0x100 */ + u32 mmsys_cg_set0; /* 0x104 */ + u32 mmsys_cg_clr0; /* 0x108 */ + u32 reserved_0x10C; /* 0x10C */ + u32 mmsys_cg_con1; /* 0x110 */ + u32 mmsys_cg_set1; /* 0x114 */ + u32 mmsys_cg_clr1; /* 0x118 */ + u32 reserved_0x11C[889]; /* 0x11C */ + u32 disp_ovl0_mout_en; /* 0xF00 */ + u32 disp_ovl0_2l_mout_en; /* 0xF04 */ + u32 disp_ovl1_2l_mout_en; /* 0xF08 */ + u32 disp_dither0_mout_en; /* 0xF0C */ + u32 reserved_0xF10[5]; /* 0xF10 - 0xF20 */ + u32 disp_path0_sel_in; /* 0xF24 */ + u32 reserved_0xF28; /* 0xF28 */ + u32 dsi0_sel_in; /* 0xF2C */ + u32 dpi0_sel_in; /* 0xF30 */ + u32 reserved_0xF34; /* 0xF34 */ + u32 disp_ovl0_2l_sel_in; /* 0xF38 */ + u32 reserved_0xF3C[5]; /* 0xF3C - 0xF4C */ + u32 disp_rdma0_sout_sel_in; /* 0xF50 */ + u32 disp_rdma1_sout_sel_in; /* 0xF54 */ + u32 reserved_0xF58[3]; /* 0xF58 - 0xF60 */ + u32 dpi0_sel_sout_sel_in; /* 0xF64 */ +}; + +check_member(mmsys_cfg_regs, mmsys_cg_con0, 0x100); +check_member(mmsys_cfg_regs, dpi0_sel_sout_sel_in, 0xF64); +static struct mmsys_cfg_regs *const mmsys_cfg = + (void *)MMSYS_BASE; + + +/* DISP_REG_CONFIG_MMSYS_CG_CON0 + Configures free-run clock gating 0 + 0: Enable clock + 1: Clock gating */ +enum { + CG_CON0_SMI_COMMON = BIT(0), + CG_CON0_SMI_LARB0 = BIT(1), + CG_CON0_GALS_COMMON0 = BIT(3), + CG_CON0_GALS_COMMON1 = BIT(4), + CG_CON0_DISP_OVL0 = BIT(20), + CG_CON0_DISP_OVL0_2L = BIT(21), + CG_CON0_DISP_OVL1_2L = BIT(22), + CG_CON0_DISP_RDMA0 = BIT(23), + CG_CON0_DISP_RDMA1 = BIT(24), + CG_CON0_DISP_WDMA0 = BIT(25), + CG_CON0_DISP_COLOR0 = BIT(26), + CG_CON0_DISP_CCORR0 = BIT(27), + CG_CON0_DISP_AAL0 = BIT(28), + CG_CON0_DISP_GAMMA0 = BIT(29), + CG_CON0_DISP_DITHER0 = BIT(30), + CG_CON0_DISP_ALL = CG_CON0_SMI_COMMON | + CG_CON0_SMI_LARB0 | + CG_CON0_GALS_COMMON0 | + CG_CON0_GALS_COMMON1 | + CG_CON0_DISP_OVL0 | + CG_CON0_DISP_OVL0_2L | + CG_CON0_DISP_RDMA0 | + CG_CON0_DISP_COLOR0 | + CG_CON0_DISP_CCORR0 | + CG_CON0_DISP_AAL0 | + CG_CON0_DISP_DITHER0 | + CG_CON0_DISP_GAMMA0, + CG_CON0_ALL = 0xffffffff +}; + +/* DISP_REG_CONFIG_MMSYS_CG_CON1 + Configures free-run clock gating 1 + 0: Enable clock + 1: Clock gating */ +enum { + CG_CON1_DISP_DSI0 = BIT(0), + CG_CON1_DISP_DSI0_INTERFACE = BIT(1), + CG_CON1_DISP_26M = BIT(7), + + CG_CON1_ALL = 0xffffffff +}; + +enum { + OVL0_MOUT_EN_RDMA0 = BIT(0), + OVL0_MOUT_EN_OVL0_2L = BIT(4), + OVL0_2L_MOUT_EN_DISP_PATH0 = BIT(0), + OVL1_2L_MOUT_EN_DISP_RDMA1 = BIT(4), + DITHER0_MOUT_EN_DISP_DSI0 = BIT(0), +}; + +enum { + DISP_PATH0_SEL_IN_OVL0 = 0, + DISP_PATH0_SEL_IN_OVL0_2L = 1, + DSI0_SEL_IN_DITHER0_MOUT = 0, + DSI0_SEL_IN_RDMA0 = 1, + RDMA0_SOUT_SEL_IN_DSI0 = 0, + RDMA0_SOUT_SEL_IN_COLOR = 1, +}; + +struct disp_mutex_regs { + u32 inten; + u32 intsta; + u32 reserved0[6]; + struct { + u32 en; + u32 dummy; + u32 rst; + u32 ctl; + u32 mod; + u32 reserved[3]; + } mutex[12]; +}; + +static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE; + +enum { + MUTEX_MOD_DISP_RDMA0 = BIT(0), + MUTEX_MOD_DISP_RDMA1 = BIT(1), + MUTEX_MOD_DISP_OVL0 = BIT(9), + MUTEX_MOD_DISP_OVL0_2L = BIT(10), + MUTEX_MOD_DISP_OVL1_2L = BIT(11), + MUTEX_MOD_DISP_WDMA0 = BIT(12), + MUTEX_MOD_DISP_COLOR0 = BIT(13), + MUTEX_MOD_DISP_CCORR0 = BIT(14), + MUTEX_MOD_DISP_AAL0 = BIT(15), + MUTEX_MOD_DISP_GAMMA0 = BIT(16), + MUTEX_MOD_DISP_DITHER0 = BIT(17), + MUTEX_MOD_DISP_PWM0 = BIT(28), + MUTEX_MOD_MAIN_PATH = MUTEX_MOD_DISP_OVL0 | MUTEX_MOD_DISP_OVL0_2L | + MUTEX_MOD_DISP_RDMA0 | MUTEX_MOD_DISP_COLOR0 | + MUTEX_MOD_DISP_CCORR0 | MUTEX_MOD_DISP_AAL0 | + MUTEX_MOD_DISP_GAMMA0 | + MUTEX_MOD_DISP_DITHER0, +}; + +enum { + MUTEX_SOF_SINGLE_MODE = 0, + MUTEX_SOF_DSI0 = 1, + MUTEX_SOF_DPI0 = 2, +}; + +struct disp_pq_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; +}; + +enum { + PQ_EN = BIT(0), + PQ_RELAY_MODE = BIT(0), +}; + +static struct disp_pq_regs *const disp_ccorr = (void *)DISP_CCORR0_BASE; + +static struct disp_pq_regs *const disp_aal = (void *)DISP_AAL0_BASE; + +static struct disp_pq_regs *const disp_gamma = (void *)DISP_GAMMA0_BASE; + +static struct disp_pq_regs *const disp_dither = (void *)DISP_DITHER0_BASE; + +enum { + SMI_LARB_NON_SEC_CON = 0x380, +}; + +void mtk_ddp_init(void); +void mtk_ddp_mode_set(const struct edid *edid); + +#endif diff --git a/src/soc/mediatek/mt8183/include/soc/i2c.h b/src/soc/mediatek/mt8183/include/soc/i2c.h new file mode 100644 index 0000000000..a75b6f002e --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/i2c.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_I2C_H +#define SOC_MEDIATEK_MT8183_I2C_H + +#include + +/* I2C Register */ +struct mt_i2c_regs { + uint32_t data_port; + uint32_t slave_addr; + uint32_t intr_mask; + uint32_t intr_stat; + uint32_t control; + uint32_t transfer_len; + uint32_t transac_len; + uint32_t delay_len; + uint32_t timing; + uint32_t start; + uint32_t ext_conf; + uint32_t ltiming; + uint32_t hs; + uint32_t io_config; + uint32_t fifo_addr_clr; + uint32_t reserved0[2]; + uint32_t transfer_aux_len; + uint32_t clock_div; + uint32_t time_out; + uint32_t softreset; + uint32_t reserved1[36]; + uint32_t debug_stat; + uint32_t debug_ctrl; + uint32_t reserved2[2]; + uint32_t fifo_stat; + uint32_t fifo_thresh; + uint32_t reserved3[932]; + uint32_t multi_dma; + uint32_t reserved4[2]; + uint32_t rollback; +}; + +check_member(mt_i2c_regs, multi_dma, 0xf8c); + +void mtk_i2c_bus_init(uint8_t bus); + +#endif /* SOC_MEDIATEK_MT8183_I2C_H */ diff --git a/src/soc/mediatek/mt8183/include/soc/md_ctrl.h b/src/soc/mediatek/mt8183/include/soc/md_ctrl.h new file mode 100644 index 0000000000..059bf9be2e --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/md_ctrl.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MEDIATEK_MD_CTRL_H__ +#define __SOC_MEDIATEK_MD_CTRL_H__ + +void mtk_md_early_init(void); + +#endif diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h index 1f6f06a568..5a61208eee 100644 --- a/src/soc/mediatek/mt8183/include/soc/rtc.h +++ b/src/soc/mediatek/mt8183/include/soc/rtc.h @@ -128,6 +128,9 @@ enum { /* PMIC TOP Register Definition */ enum { + PMIC_RG_TOP_CKPDN_CON0 = 0x010C, + PMIC_RG_TOP_CKPDN_CON0_SET = 0x010E, + PMIC_RG_TOP_CKPDN_CON0_CLR = 0x0110, PMIC_RG_TOP_CKPDN_CON1 = 0x0112, PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114, PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116, @@ -136,6 +139,11 @@ enum { PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C }; +enum { + PMIC_RG_FQMTR_32K_CK_PDN_SHIFT = 10, + PMIC_RG_FQMTR_CK_PDN_SHIFT = 11 +}; + /* PMIC DCXO Register Definition */ enum { PMIC_RG_DCXO_CW00 = 0x0788, @@ -155,6 +163,56 @@ enum { PMIC_RG_TOP_TMA_KEY = 0x03A8 }; +/* PMIC Frequency Meter Definition */ +enum { + PMIC_RG_FQMTR_CKSEL = 0x0118, + PMIC_RG_FQMTR_RST = 0x013E, + PMIC_RG_FQMTR_CON0 = 0x0514, + PMIC_RG_FQMTR_WINSET = 0x0516, + PMIC_RG_FQMTR_DATA = 0x0518, + + FQMTR_TIMEOUT_US = 8000 +}; + +enum { + PMIC_FQMTR_FIX_CLK_26M = 0U << 0, + PMIC_FQMTR_FIX_CLK_XOSC_32K_DET = 1U << 0, + PMIC_FQMTR_FIX_CLK_EOSC_32K = 2U << 0, + PMIC_FQMTR_FIX_CLK_RTC_32K = 3U << 0, + PMIC_FQMTR_FIX_CLK_SMPS_CK = 4U << 0, + PMIC_FQMTR_FIX_CLK_TCK_SEC = 5U << 0, + PMIC_FQMTR_FIX_CLK_PMU_75K = 6U << 0, + PMIC_FQMTR_CKSEL_MASK = 7U << 0 +}; + +enum { + PMIC_FQMTR_RST_SHIFT = 8 +}; + +enum { + PMIC_FQMTR_CON0_XOSC32_CK = 0U << 0, + PMIC_FQMTR_CON0_DCXO_F32K_CK = 1U << 0, + PMIC_FQMTR_CON0_EOSC32_CK = 2U << 0, + PMIC_FQMTR_CON0_XOSC32_CK_DETECTON = 3U << 0, + PMIC_FQMTR_CON0_FQM26M_CK = 4U << 0, + PMIC_FQMTR_CON0_FQM32k_CK = 5U << 0, + PMIC_FQMTR_CON0_TEST_CK = 6U << 0, + PMIC_FQMTR_CON0_TCKSEL_MASK = 7U << 0, + PMIC_FQMTR_CON0_BUSY = 1U << 3, + PMIC_FQMTR_CON0_DCXO26M_EN = 1U << 4, + PMIC_FQMTR_CON0_FQMTR_EN = 1U << 15 +}; + +enum { + RTC_FQMTR_LOW_BASE = 794 - 2, + RTC_FQMTR_HIGH_BASE = 794 + 2 +}; + +enum { + RTC_XOSCCALI_START = 0x00, + RTC_XOSCCALI_END = 0x1f +}; + /* external API */ void rtc_bbpu_power_on(void); void rtc_osc_init(void); diff --git a/src/soc/mediatek/mt8183/include/soc/sspm.h b/src/soc/mediatek/mt8183/include/soc/sspm.h new file mode 100644 index 0000000000..627088fdc7 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/sspm.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_SSPM_H +#define SOC_MEDIATEK_MT8183_SSPM_H + +#include +#include + +struct mt8183_sspm_regs { + u32 sw_rstn; +}; +static struct mt8183_sspm_regs *const mt8183_sspm = (void *)SSPM_CFG_BASE; +void sspm_init(void); +#endif /* SOC_MEDIATEK_MT8183_SSPM_H */ diff --git a/src/soc/mediatek/mt8183/md_ctrl.c b/src/soc/mediatek/mt8183/md_ctrl.c new file mode 100644 index 0000000000..aa97756db2 --- /dev/null +++ b/src/soc/mediatek/mt8183/md_ctrl.c @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#define TOPCKGEN_CLK_MODE_MD_32K (1 << 8) +#define TOPCKGEN_CLK_MODE_MD_26M (1 << 9) +#define INFRA_MISC2_SRCCLKENA_RELEASE (0xFF) + +static void internal_md_power_down(void) +{ + /* Gating MD clock */ + setbits_le32(&mtk_topckgen->clk_mode, + TOPCKGEN_CLK_MODE_MD_32K | TOPCKGEN_CLK_MODE_MD_26M); + /* Release SRCCLKENA */ + clrbits_le32(&mt8183_infracfg->infra_misc2, + INFRA_MISC2_SRCCLKENA_RELEASE); +} + +void mtk_md_early_init(void) +{ + internal_md_power_down(); +} diff --git a/src/soc/mediatek/mt8183/mt8183.c b/src/soc/mediatek/mt8183/mt8183.c index c4419803da..32da3e0ea5 100644 --- a/src/soc/mediatek/mt8183/mt8183.c +++ b/src/soc/mediatek/mt8183/mt8183.c @@ -15,8 +15,10 @@ #include #include +#include void mt8183_early_init(void) { mtk_wdt_init(); + gpio_set_i2c_eh_rsel(); } diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 3bd3ab4921..af30d1f90b 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -19,6 +19,7 @@ #include #include #include +#include #define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) @@ -79,11 +80,145 @@ static int rtc_gpio_init(void) return rtc_write_trigger(); } -/* set xosc mode */ +static u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size) +{ + u16 bbpu, osc32con; + u16 fqmtr_busy, fqmtr_data, fqmtr_rst, fqmtr_tcksel; + struct stopwatch sw; + + if (val) { + rtc_read(RTC_BBPU, &bbpu); + rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + rtc_write_trigger(); + rtc_read(RTC_OSC32CON, &osc32con); + rtc_xosc_write((osc32con & ~RTC_XOSCCALI_MASK) | + (val & RTC_XOSCCALI_MASK)); + } + + /* enable FQMTR clock */ + pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1, + PMIC_RG_FQMTR_32K_CK_PDN_SHIFT); + pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1, + PMIC_RG_FQMTR_CK_PDN_SHIFT); + + /* FQMTR reset */ + pwrap_write_field(PMIC_RG_FQMTR_RST, 1, 1, PMIC_FQMTR_RST_SHIFT); + do { + rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data); + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy); + } while (fqmtr_data && (fqmtr_busy & PMIC_FQMTR_CON0_BUSY)); + rtc_read(PMIC_RG_FQMTR_RST, &fqmtr_rst); + /* FQMTR normal */ + pwrap_write_field(PMIC_RG_FQMTR_RST, 0, 1, PMIC_FQMTR_RST_SHIFT); + + /* set frequency meter window value (0=1X32K(fixed clock)) */ + rtc_write(PMIC_RG_FQMTR_WINSET, window_size); + /* enable 26M and set test clock source */ + rtc_write(PMIC_RG_FQMTR_CON0, PMIC_FQMTR_CON0_DCXO26M_EN | measure_src); + /* enable 26M -> delay 100us -> enable FQMTR */ + udelay(100); + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); + /* enable FQMTR */ + rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel | PMIC_FQMTR_CON0_FQMTR_EN); + udelay(100); + + stopwatch_init_usecs_expire(&sw, FQMTR_TIMEOUT_US); + /* FQMTR read until ready */ + do { + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy); + if (stopwatch_expired(&sw)) { + rtc_info("get frequency time out !!\n"); + return 0; + } + } while (fqmtr_busy & PMIC_FQMTR_CON0_BUSY); + + /* read data should be closed to 26M/32k = 794 */ + rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data); + + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); + /* disable FQMTR */ + rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel & ~PMIC_FQMTR_CON0_FQMTR_EN); + /* disable FQMTR -> delay 100us -> disable 26M */ + udelay(100); + /* disable 26M */ + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); + rtc_write(PMIC_RG_FQMTR_CON0, + fqmtr_tcksel & ~PMIC_FQMTR_CON0_DCXO26M_EN); + rtc_info("input=0x%x, output=%d\n", val, fqmtr_data); + + /* disable FQMTR clock */ + pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1, + PMIC_RG_FQMTR_32K_CK_PDN_SHIFT); + pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1, + PMIC_RG_FQMTR_CK_PDN_SHIFT); + + return fqmtr_data; +} + +/* 32k clock calibration */ +static u16 rtc_eosc_cali(void) +{ + u16 middle, diff1, diff2, cksel; + u16 val = 0; + u16 left = RTC_XOSCCALI_START, right = RTC_XOSCCALI_END; + + rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel); + cksel &= ~PMIC_FQMTR_CKSEL_MASK; + /* select EOSC_32 as fixed clock */ + rtc_write(PMIC_RG_FQMTR_CKSEL, cksel | PMIC_FQMTR_FIX_CLK_EOSC_32K); + rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel); + rtc_info("PMIC_RG_FQMTR_CKSEL=0x%x\n", cksel); + + while (left <= right) { + middle = (right + left) / 2; + if (middle == left) + break; + + /* select 26M as target clock */ + val = rtc_get_frequency_meter(middle, PMIC_FQMTR_CON0_FQM26M_CK, 0); + + if ((val >= RTC_FQMTR_LOW_BASE) && (val <= RTC_FQMTR_HIGH_BASE)) + break; + if (val > RTC_FQMTR_HIGH_BASE) + right = middle; + else + left = middle; + } + + if ((val >= RTC_FQMTR_LOW_BASE) && (val <= RTC_FQMTR_HIGH_BASE)) + return middle; + + val = rtc_get_frequency_meter(left, PMIC_FQMTR_CON0_FQM26M_CK, 0); + if (val > RTC_FQMTR_LOW_BASE) + diff1 = val - RTC_FQMTR_LOW_BASE; + else + diff1 = RTC_FQMTR_LOW_BASE - val; + + val = rtc_get_frequency_meter(right, PMIC_FQMTR_CON0_FQM26M_CK, 0); + if (val > RTC_FQMTR_LOW_BASE) + diff2 = val - RTC_FQMTR_LOW_BASE; + else + diff2 = RTC_FQMTR_LOW_BASE - val; + + if (diff1 < diff2) + return left; + else + return right; +} + void rtc_osc_init(void) { + u16 osc32con; + /* enable 32K export */ rtc_gpio_init(); + + /* Calibrate eosc32 for powerdown clock */ + rtc_read(RTC_OSC32CON, &osc32con); + osc32con &= ~RTC_XOSCCALI_MASK; + osc32con |= rtc_eosc_cali() & RTC_XOSCCALI_MASK; + rtc_xosc_write(osc32con); + rtc_info("EOSC32 cali val = 0x%x\n", osc32con); } /* enable lpd subroutine */ @@ -196,6 +331,8 @@ int rtc_init(u8 recover) goto err; } + rtc_osc_init(); + if (recover) mdelay(20); diff --git a/src/soc/mediatek/mt8183/soc.c b/src/soc/mediatek/mt8183/soc.c index b51e7d4653..c9c2147cc8 100644 --- a/src/soc/mediatek/mt8183/soc.c +++ b/src/soc/mediatek/mt8183/soc.c @@ -15,10 +15,11 @@ #include #include +#include #include +#include #include - static void soc_read_resources(struct device *dev) { ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB); @@ -27,6 +28,8 @@ static void soc_read_resources(struct device *dev) static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); + mtk_md_early_init(); + sspm_init(); } static struct device_operations soc_ops = { diff --git a/src/soc/mediatek/mt8183/sspm.c b/src/soc/mediatek/mt8183/sspm.c new file mode 100644 index 0000000000..559034eacb --- /dev/null +++ b/src/soc/mediatek/mt8183/sspm.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#define BUF_SIZE (64 * KiB) +static uint8_t sspm_bin[BUF_SIZE] __aligned(8); + +void sspm_init(void) +{ + const char *file_name = "sspm.bin"; + size_t fw_size = cbfs_boot_load_file(file_name, + sspm_bin, + sizeof(sspm_bin), + CBFS_TYPE_RAW); + + if (fw_size == 0) + die("SSPM file :sspm.bin not found."); + + memcpy((void *)SSPM_SRAM_BASE, sspm_bin, fw_size); + /* Memory barrier to ensure that all fw code is loaded + before we release the reset pin. */ + mb(); + write32(&mt8183_sspm->sw_rstn, 0x1); +} diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c index 9dbfde8352..c28cd0b1de 100644 --- a/src/soc/nvidia/tegra/i2c.c +++ b/src/soc/nvidia/tegra/i2c.c @@ -17,9 +17,10 @@ #include #include #include -#include #include #include +#include + #include "i2c.h" static void do_bus_clear(int bus) diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index c7503041b4..1793aaf3de 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -26,6 +26,9 @@ #include #include +/* called from assembly in bootblock_asm.S */ +void tegra124_main(void); + static void run_next_stage(void *entry) { ASSERT(entry); @@ -41,7 +44,7 @@ static void run_next_stage(void *entry) clock_halt_avp(); } -void main(void) +void tegra124_main(void) { // enable pinmux clamp inputs clamp_tristate_inputs(); diff --git a/src/soc/nvidia/tegra124/bootblock_asm.S b/src/soc/nvidia/tegra124/bootblock_asm.S index 0391ebf1ac..dca5314dc9 100644 --- a/src/soc/nvidia/tegra124/bootblock_asm.S +++ b/src/soc/nvidia/tegra124/bootblock_asm.S @@ -66,5 +66,5 @@ call_bootblock: * Thumb. However, "b" will not and GCC may attempt to create a * wrapper which is currently broken. */ - bl main + bl tegra124_main ENDPROC(_start) diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index 6877c04b98..bb0343d432 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -13,6 +13,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#include #include #include #include @@ -377,6 +378,7 @@ clock_display(u32 frequency) printk(BIOS_WARNING, "%s: Failed to match output frequency %u, " "best difference is %u.\n", __func__, frequency, best_diff); + assert(plld.m != 0); rounded_rate = (ref / plld.m * plld.n) >> plld.p; } diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c index b9fa0eae8c..d8a4f22272 100644 --- a/src/soc/nvidia/tegra124/dp.c +++ b/src/soc/nvidia/tegra124/dp.c @@ -27,8 +27,8 @@ #include #include #include -#include #include +#include #include "chip.h" diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c index 3bc50e813e..1c151f50df 100644 --- a/src/soc/nvidia/tegra124/sor.c +++ b/src/soc/nvidia/tegra124/sor.c @@ -237,6 +237,7 @@ static int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor, /* fall through */ case 2: reg_val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO; + /* fall through */ case 1: reg_val |= NV_SOR_DP_PADCTL_PD_TXD_0_NO; break; @@ -347,10 +348,10 @@ static void tegra_dc_sor_io_set_dpd(struct tegra_dc_sor_data *sor, int up) } reg_val = READL(pmc_base + APBDEV_PMC_IO_DPD2_REQ); - reg_val &= ~(APBDEV_PMC_IO_DPD2_REQ_LVDS_ON || + reg_val &= ~(APBDEV_PMC_IO_DPD2_REQ_LVDS_ON | APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK); - reg_val = up ? APBDEV_PMC_IO_DPD2_REQ_LVDS_ON | + reg_val |= up ? APBDEV_PMC_IO_DPD2_REQ_LVDS_ON | APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF : APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF | APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON; diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 45159c2fee..4bd0ab7d1a 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -26,10 +26,9 @@ #include #include #include -#include -#include #include #include +#include #if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI # define DEBUG_SPI(x,...) printk(BIOS_DEBUG, "TEGRA_SPI: " x) diff --git a/src/soc/nvidia/tegra210/addressmap.c b/src/soc/nvidia/tegra210/addressmap.c index 4f11d4ec1c..716c900fec 100644 --- a/src/soc/nvidia/tegra210/addressmap.c +++ b/src/soc/nvidia/tegra210/addressmap.c @@ -21,9 +21,9 @@ #include #include #include -#include #include #include +#include static uintptr_t tz_base_mib; static const size_t tz_size_mib = CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB; diff --git a/src/soc/nvidia/tegra210/arm_tf.c b/src/soc/nvidia/tegra210/arm_tf.c index bd34185494..38bb8bfc9e 100644 --- a/src/soc/nvidia/tegra210/arm_tf.c +++ b/src/soc/nvidia/tegra210/arm_tf.c @@ -18,8 +18,8 @@ #include #include #include -#include #include +#include typedef struct bl31_plat_params { /* TZ memory size */ diff --git a/src/soc/nvidia/tegra210/bootblock.c b/src/soc/nvidia/tegra210/bootblock.c index 96fb9b22d5..383e578eeb 100644 --- a/src/soc/nvidia/tegra210/bootblock.c +++ b/src/soc/nvidia/tegra210/bootblock.c @@ -31,6 +31,9 @@ #define ODMDATA_OFFSET_IN_BCT 0x508 #define TEGRA_SRAM_MAX (TEGRA_SRAM_BASE + TEGRA_SRAM_SIZE) +/* called from assembly in bootblock_asm.S */ +void tegra210_main(void); + static void save_odmdata(void) { struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE; @@ -155,7 +158,7 @@ static void mbist_workaround(void) } } -void main(void) +void tegra210_main(void) { // enable JTAG at the earliest stage enable_jtag(); diff --git a/src/soc/nvidia/tegra210/bootblock_asm.S b/src/soc/nvidia/tegra210/bootblock_asm.S index 62554422db..6ea154abab 100644 --- a/src/soc/nvidia/tegra210/bootblock_asm.S +++ b/src/soc/nvidia/tegra210/bootblock_asm.S @@ -37,5 +37,5 @@ ENTRY(_start) */ msr cpsr_cxf, #0xdf - stack_init stack_top=_estack stack_bottom=_stack seed=1 func=main + stack_init stack_top=_estack stack_bottom=_stack seed=1 func=tegra210_main ENDPROC(_start) diff --git a/src/soc/nvidia/tegra210/dc.c b/src/soc/nvidia/tegra210/dc.c index ceffb41dd8..46443cfe72 100644 --- a/src/soc/nvidia/tegra210/dc.c +++ b/src/soc/nvidia/tegra210/dc.c @@ -12,16 +12,17 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + #include #include #include -#include #include #include #include -#include "chip.h" #include +#include "chip.h" + int dump = 0; unsigned long READL(void *p) { diff --git a/src/soc/nvidia/tegra210/dp.c b/src/soc/nvidia/tegra210/dp.c index b0c0846928..42845505d2 100644 --- a/src/soc/nvidia/tegra210/dp.c +++ b/src/soc/nvidia/tegra210/dp.c @@ -16,11 +16,11 @@ * GNU General Public License for more details. * */ + #include #include #include #include -#include #include #include #include @@ -32,6 +32,8 @@ #include #include #include +#include + #include "chip.h" #define DO_FAST_LINK_TRAINING 0 diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c index ae20d44d16..7d54c9e8ac 100644 --- a/src/soc/nvidia/tegra210/dsi.c +++ b/src/soc/nvidia/tegra210/dsi.c @@ -380,8 +380,8 @@ static int tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe, } tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1); - tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3); - tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5); + tegra_dsi_writel(dsi, (u32)bytes << 16, DSI_PKT_LEN_2_3); + tegra_dsi_writel(dsi, (u32)bytes << 16, DSI_PKT_LEN_4_5); tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7); value = MIPI_DCS_WRITE_MEMORY_START << 8 | @@ -769,7 +769,7 @@ static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host, tegra_dsi_writel(dsi, value, DSI_WR_DATA); /* write payload (if any) */ - if (msg->tx_len > 2) { + if (tx && msg->tx_len > 2) { for (j = 2; j < msg->tx_len; j += 4) { value = 0; diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld index 5d7481b7bb..6d74ab928f 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -29,17 +29,17 @@ SECTIONS { SRAM_START(0x40000000) PRERAM_CBMEM_CONSOLE(0x40000000, 2K) - PRERAM_CBFS_CACHE(0x40000800, 32K) - VBOOT2_WORK(0x40008800, 12K) - VBOOT2_TPM_LOG(0x4000B800, 2K) + PRERAM_CBFS_CACHE(0x40000800, 30K) + VBOOT2_WORK(0x40008000, 12K) + VBOOT2_TPM_LOG(0x4000B000, 2K) #if ENV_ARM64 - STACK(0x4000C000, 3K) + STACK(0x4000B800, 3K) #else /* AVP gets a separate stack to avoid any chance of handoff races. */ - STACK(0x4000CC00, 3K) + STACK(0x4000C400, 3K) #endif - TIMESTAMP(0x4000D800, 2K) - BOOTBLOCK(0x4000E000, 30K) - VERSTAGE(0x40015800, 66K) + TIMESTAMP(0x4000D000, 2K) + BOOTBLOCK(0x4000D800, 30K) + VERSTAGE(0x40015000, 68k) ROMSTAGE(0x40026000, 104K) SRAM_END(0x40040000) diff --git a/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c b/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c index a9101b80fb..f95a819448 100644 --- a/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c +++ b/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c @@ -12,18 +12,19 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + #include #include -#include #include #include #include #include #include -#include "../chip.h" #include #include #include + +#include "../chip.h" #include "panel-jdi-lpm102a188a.h" struct panel_jdi jdi_data[NUM_DSI]; diff --git a/src/soc/nvidia/tegra210/mipi.c b/src/soc/nvidia/tegra210/mipi.c index f863496ac0..e222048ba9 100644 --- a/src/soc/nvidia/tegra210/mipi.c +++ b/src/soc/nvidia/tegra210/mipi.c @@ -16,8 +16,6 @@ #include #include #include -#include -#include #include #include #include @@ -26,6 +24,7 @@ #include #include #include + #include "jdi_25x18_display/panel-jdi-lpm102a188a.h" static unsigned long dsi_pads[] = { diff --git a/src/soc/nvidia/tegra210/mipi_dsi.c b/src/soc/nvidia/tegra210/mipi_dsi.c index 23d92743ce..24a61f18d1 100644 --- a/src/soc/nvidia/tegra210/mipi_dsi.c +++ b/src/soc/nvidia/tegra210/mipi_dsi.c @@ -40,8 +40,6 @@ */ #include -#include -#include #include #include #include @@ -51,6 +49,7 @@ #include #include #include +#include struct mipi_dsi_device mipi_dsi_device_data[NUM_DSI] = { { diff --git a/src/soc/nvidia/tegra210/mmu_operations.c b/src/soc/nvidia/tegra210/mmu_operations.c index 86328a32b2..73538b1570 100644 --- a/src/soc/nvidia/tegra210/mmu_operations.c +++ b/src/soc/nvidia/tegra210/mmu_operations.c @@ -17,9 +17,8 @@ #include #include #include -#include -#include #include +#include static void tegra210_mmu_config(void) { diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index 9310e0cc09..6ec8b641ab 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -286,25 +286,27 @@ static void dump_spi_regs(struct tegra_spi_channel *spi) static void dump_dma_regs(struct apb_dma_channel *dma) { - printk(BIOS_INFO, "DMA regs:\n" - "\tahb_ptr: 0x%08x\n" - "\tapb_ptr: 0x%08x\n" - "\tahb_seq: 0x%08x\n" - "\tapb_seq: 0x%08x\n" - "\tcsr: 0x%08x\n" - "\tcsre: 0x%08x\n" - "\twcount: 0x%08x\n" - "\tdma_byte_sta: 0x%08x\n" - "\tword_transfer: 0x%08x\n", - read32(&dma->regs->ahb_ptr), - read32(&dma->regs->apb_ptr), - read32(&dma->regs->ahb_seq), - read32(&dma->regs->apb_seq), - read32(&dma->regs->csr), - read32(&dma->regs->csre), - read32(&dma->regs->wcount), - read32(&dma->regs->dma_byte_sta), - read32(&dma->regs->word_transfer)); + if (dma) { + printk(BIOS_INFO, "DMA regs:\n" + "\tahb_ptr: 0x%08x\n" + "\tapb_ptr: 0x%08x\n" + "\tahb_seq: 0x%08x\n" + "\tapb_seq: 0x%08x\n" + "\tcsr: 0x%08x\n" + "\tcsre: 0x%08x\n" + "\twcount: 0x%08x\n" + "\tdma_byte_sta: 0x%08x\n" + "\tword_transfer: 0x%08x\n", + read32(&dma->regs->ahb_ptr), + read32(&dma->regs->apb_ptr), + read32(&dma->regs->ahb_seq), + read32(&dma->regs->apb_seq), + read32(&dma->regs->csr), + read32(&dma->regs->csre), + read32(&dma->regs->wcount), + read32(&dma->regs->dma_byte_sta), + read32(&dma->regs->word_transfer)); + } } static inline unsigned int spi_byte_count(struct tegra_spi_channel *spi) @@ -574,9 +576,9 @@ static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE; - todo = read32(&spi->dma_in->regs->wcount); - if (spi->dma_in) { + todo = read32(&spi->dma_in->regs->wcount); + while ((read32(&spi->dma_in->regs->dma_byte_sta) < todo) || dma_busy(spi->dma_in)) ; @@ -589,6 +591,8 @@ static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) } if (spi->dma_out) { + todo = read32(&spi->dma_out->regs->wcount); + while ((read32(&spi->dma_out->regs->dma_byte_sta) < todo) || dma_busy(spi->dma_out)) ; diff --git a/src/soc/qualcomm/ipq806x/lcc.c b/src/soc/qualcomm/ipq806x/lcc.c index 68b878ceab..8f862b4d49 100644 --- a/src/soc/qualcomm/ipq806x/lcc.c +++ b/src/soc/qualcomm/ipq806x/lcc.c @@ -287,29 +287,21 @@ static int lcc_enable_mi2s(Ipq806xLccClocks *bus) int audio_clock_config(unsigned frequency) { - Ipq806xLccClocks *bus = malloc(sizeof(*bus)); + Ipq806xLccClocks bus = { + .gcc_apcs_regs = (void *)(MSM_GCC_BASE + GCC_PLL_APCS_REG), + .lcc_pll0_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_PLL0_MODE_REG), + .lcc_ahbix_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_AHBIX_NS_REG), + .lcc_mi2s_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_MI2S_NS_REG), + .lcc_pll_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_PLL_PCLK_REG), + }; - if (!bus) { - printk(BIOS_ERR, "%s: failed to allocate bus structure\n", - __func__); + if (lcc_init_enable_pll0(&bus)) return 1; - } - - bus->gcc_apcs_regs = (void *)(MSM_GCC_BASE + GCC_PLL_APCS_REG); - bus->lcc_pll0_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_PLL0_MODE_REG); - bus->lcc_ahbix_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_AHBIX_NS_REG); - bus->lcc_mi2s_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_MI2S_NS_REG); - bus->lcc_pll_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_PLL_PCLK_REG); - - - if (lcc_init_enable_pll0(bus)) + if (lcc_init_enable_ahbix(&bus)) return 1; - if (lcc_init_enable_ahbix(bus)) + if (lcc_init_mi2s(&bus, frequency)) return 1; - if (lcc_init_mi2s(bus, frequency)) - return 1; - - if (lcc_enable_mi2s(bus)) + if (lcc_enable_mi2s(&bus)) return 1; return 0; diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index 2657b9c574..64a98d5123 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #define SUCCESS 0 diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index de42147432..b7dd51b2a6 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -235,12 +235,16 @@ void clock_configure_spi(int blsp, int qup, uint32_t hz) spi_clk = (struct qcs405_clock *) &gcc->blsp1_qup4_spi_clk; break; + default: + printk(BIOS_ERR, "Invalid QUP %d\n", qup); + return; } - } else if (blsp == 2) + } else if (blsp == 2) { spi_clk = (struct qcs405_clock *)&gcc->blsp2_qup0_spi_clk; - - else - printk(BIOS_ERR, "BLSP%d not supported\n", blsp); + } else { + printk(BIOS_ERR, "BLSP %d not supported\n", blsp); + return; + } clock_configure(spi_clk, spi_cfg, hz, ARRAY_SIZE(spi_cfg)); } diff --git a/src/soc/rockchip/common/edp.c b/src/soc/rockchip/common/edp.c index 91e2de9ff4..ea0930a058 100644 --- a/src/soc/rockchip/common/edp.c +++ b/src/soc/rockchip/common/edp.c @@ -18,13 +18,12 @@ #include #include #include -#include -#include #include #include #include #include #include +#include #define edp_debug(x...) do {if (0) printk(BIOS_DEBUG, x); } while (0) diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c index e929419a14..7bde4333ea 100644 --- a/src/soc/rockchip/common/spi.c +++ b/src/soc/rockchip/common/spi.c @@ -23,8 +23,8 @@ #include #include #include -#include #include +#include struct rockchip_spi_slave { struct rockchip_spi *regs; diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index 808ff963a8..74038b078e 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -751,10 +751,8 @@ static void move_to_config_state(struct rk3288_ddr_publ_regs *ddr_publ_regs, while ((read32(&ddr_publ_regs->pgsr) & PGSR_DLDONE) != PGSR_DLDONE) ; - /* if at low power state,need wakeup first, - * and then enter the config - * so here no break. - */ + /* if at low power state, need wakeup first, then enter the config */ + /* fall through */ case ACCESS: case INIT_MEM: write32(&ddr_pctl_regs->sctl, CFG_STATE); @@ -908,6 +906,7 @@ static void move_to_access_state(u32 chnum) while ((read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK) != CONF) ; + /* fall through - enter config next to get to access state */ case CONF: write32(&ddr_pctl_regs->sctl, GO_STATE); while ((read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK) diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c index 1f3f02cbee..8b80bd724b 100644 --- a/src/soc/rockchip/rk3399/mipi.c +++ b/src/soc/rockchip/rk3399/mipi.c @@ -305,7 +305,7 @@ static int rk_mipi_dsi_get_lane_bps(struct rk_mipi_dsi *dsi, dsi->format); return bpp; } - pclk = edid->mode.pixel_clock * MSECS_PER_SEC; + pclk = (u64)edid->mode.pixel_clock * MSECS_PER_SEC; /* take 1 / 0.8, since mbps must bigger than bandwidth of RGB */ target_bps = pclk / panel_data->lanes * bpp / 8 * 10; diff --git a/src/soc/samsung/exynos5420/fimd.c b/src/soc/samsung/exynos5420/fimd.c index 756d2fba54..2b3552abdd 100644 --- a/src/soc/samsung/exynos5420/fimd.c +++ b/src/soc/samsung/exynos5420/fimd.c @@ -317,9 +317,10 @@ static void exynos5_set_system_display(void) void exynos_fimd_lcd_init(vidinfo_t *vid) { unsigned int cfg = 0, rgb_mode; - unsigned int offset; + struct exynos_fb *fimd; + + fimd = (void *)(FIMD_CTRL_ADDR + EXYNOS5_LCD_IF_BASE_OFFSET); - offset = exynos_fimd_get_base_offset(); printk(BIOS_SPEW, "%s\n", __func__); exynos5_set_system_display(); @@ -349,19 +350,19 @@ void exynos_fimd_lcd_init(vidinfo_t *vid) if (!vid->vl_dp) cfg |= EXYNOS_VIDCON1_IVDEN_INVERT; - lwritel(cfg, &FIMD_CTRL->vidcon1 + offset); + lwritel(cfg, &fimd->vidcon1); /* set timing */ cfg = EXYNOS_VIDTCON0_VFPD(vid->vl_vfpd - 1); cfg |= EXYNOS_VIDTCON0_VBPD(vid->vl_vbpd - 1); cfg |= EXYNOS_VIDTCON0_VSPW(vid->vl_vspw - 1); - lwritel(cfg, &FIMD_CTRL->vidtcon0 + offset); + lwritel(cfg, &fimd->vidtcon0); cfg = EXYNOS_VIDTCON1_HFPD(vid->vl_hfpd - 1); cfg |= EXYNOS_VIDTCON1_HBPD(vid->vl_hbpd - 1); cfg |= EXYNOS_VIDTCON1_HSPW(vid->vl_hspw - 1); - lwritel(cfg, &FIMD_CTRL->vidtcon1 + offset); + lwritel(cfg, &fimd->vidtcon1); /* set lcd size */ cfg = EXYNOS_VIDTCON2_HOZVAL(vid->vl_col - 1) | @@ -369,7 +370,7 @@ void exynos_fimd_lcd_init(vidinfo_t *vid) EXYNOS_VIDTCON2_HOZVAL_E(vid->vl_col - 1) | EXYNOS_VIDTCON2_LINEVAL_E(vid->vl_row - 1); - lwritel(cfg, &FIMD_CTRL->vidtcon2 + offset); + lwritel(cfg, &fimd->vidtcon2); } /* set display mode */ diff --git a/src/soc/samsung/exynos5420/include/soc/dp.h b/src/soc/samsung/exynos5420/include/soc/dp.h index 28db73a019..6b33a76294 100644 --- a/src/soc/samsung/exynos5420/include/soc/dp.h +++ b/src/soc/samsung/exynos5420/include/soc/dp.h @@ -884,11 +884,6 @@ struct exynos_fb { /* LCD IF register offset */ #define EXYNOS5_LCD_IF_BASE_OFFSET 0x20000 -static inline u32 exynos_fimd_get_base_offset(void) -{ - return EXYNOS5_LCD_IF_BASE_OFFSET/4; -} - /* * Register offsets */ diff --git a/src/soc/samsung/exynos5420/include/soc/fimd.h b/src/soc/samsung/exynos5420/include/soc/fimd.h index d9d86cbfae..3e9d6a44f5 100644 --- a/src/soc/samsung/exynos5420/include/soc/fimd.h +++ b/src/soc/samsung/exynos5420/include/soc/fimd.h @@ -136,7 +136,8 @@ check_member(exynos5_disp_ctrl, trigcon, 0x1a4); #define OSD_RIGHTBOTX_F_OFFSET 11 #define OSD_RIGHTBOTY_F_OFFSET 0 -#define FIMD_CTRL ((struct exynos_fb *)0x14400000) +#define FIMD_CTRL_ADDR 0x14400000 +#define FIMD_CTRL ((struct exynos_fb *)FIMD_CTRL_ADDR) /* from u-boot fb.h. It needs to be merged with these dp structs maybe. */ enum { diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index 82b42e5559..97c67bf946 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -24,6 +24,7 @@ config SOC_SIFIVE_FU540 select DRIVERS_UART_SIFIVE select RISCV_USE_ARCH_TIMER select UART_OVERRIDE_REFCLK + select RISCV_HAS_OPENSBI if SOC_SIFIVE_FU540 @@ -47,4 +48,11 @@ config RISCV_WORKING_HARTID int default 0 +config OPENSBI_PLATFORM + string + default "sifive/fu540" + +config OPENSBI_TEXT_START + hex + default 0x80000000 endif diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld index b9b9c479d6..1d11aa0452 100644 --- a/src/soc/sifive/fu540/include/soc/memlayout.ld +++ b/src/soc/sifive/fu540/include/soc/memlayout.ld @@ -31,6 +31,7 @@ SECTIONS L2LIM_END(FU540_L2LIM + 2M) DRAM_START(FU540_DRAM) - RAMSTAGE(FU540_DRAM, 256K) - MEM_STACK(FU540_DRAM + 256K, 20K) + REGION(opensbi, FU540_DRAM, 128K, 4K) + RAMSTAGE(FU540_DRAM + 128K, 256K) + MEM_STACK(FU540_DRAM + 448K, 20K) } diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c index 2ee400ab8b..542e08d05e 100644 --- a/src/soc/ucb/riscv/cbmem.c +++ b/src/soc/ucb/riscv/cbmem.c @@ -12,16 +12,10 @@ */ #include +#include +#include void *cbmem_top(void) { - uintptr_t base; - size_t size; - - /* Use dummy values until we can query the memory size again */ - //query_mem(configstring(), &base, &size); - base = 0x80000000; - size = 128 * MiB; - - return (void *)(base + size); + return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index 25997d2e9d..4c06e87281 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -117,21 +117,24 @@ void hudson_enable(struct device *dev) case PCI_DEVFN(0x12, 0): if (dev->enabled == 0) hudson_disable_usb(USB_EN_DEVFN_12_0); - case PCI_DEVFN(0x12, 2): /* Fall through */ + /* fall through */ + case PCI_DEVFN(0x12, 2): if (dev->enabled == 0) hudson_disable_usb(USB_EN_DEVFN_12_2); break; case PCI_DEVFN(0x13, 0): if (dev->enabled == 0) hudson_disable_usb(USB_EN_DEVFN_13_0); - case PCI_DEVFN(0x13, 2): /* Fall through */ + /* fall through */ + case PCI_DEVFN(0x13, 2): if (dev->enabled == 0) hudson_disable_usb(USB_EN_DEVFN_13_2); break; case PCI_DEVFN(0x16, 0): if (dev->enabled == 0) hudson_disable_usb(USB_EN_DEVFN_16_0); - case PCI_DEVFN(0x16, 2): /* Fall through */ + /* fall through */ + case PCI_DEVFN(0x16, 2): if (dev->enabled == 0) hudson_disable_usb(USB_EN_DEVFN_16_2); break; diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index a88d6d34e9..79f402993f 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -170,11 +170,13 @@ void lpc_enable_childrens_resources(struct device *dev) pci_write_config32(dev, 0x48, reg_x); /* Set WideIO for as many IOs found (fall through is on purpose) */ switch (var_num) { - case 2: + case 3: pci_write_config16(dev, 0x90, reg_var[2]); - case 1: + /* fall through */ + case 2: pci_write_config16(dev, 0x66, reg_var[1]); - case 0: + /* fall through */ + case 1: //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata break; } diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c index b04ecfa123..8e7c1cc67f 100644 --- a/src/southbridge/amd/cimx/sb900/lpc.c +++ b/src/southbridge/amd/cimx/sb900/lpc.c @@ -168,11 +168,13 @@ void lpc_enable_childrens_resources(struct device *dev) pci_write_config32(dev, 0x48, reg_x); /* Set WideIO for as many IOs found (fall through is on purpose) */ switch (var_num) { - case 2: + case 3: pci_write_config16(dev, 0x90, reg_var[2]); - case 1: + /* fall through */ + case 2: pci_write_config16(dev, 0x66, reg_var[1]); - case 0: + /* fall through */ + case 1: //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata break; } diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 6f3be03c30..eb171e605a 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -228,11 +228,13 @@ static void sb700_lpc_enable_childrens_resources(struct device *dev) pci_write_config32(dev, 0x48, reg_x); /* Set WideIO for as many IOs found (fall through is on purpose) */ switch (var_num) { - case 2: + case 3: pci_write_config16(dev, 0x90, reg_var[2]); - case 1: + /* fall through */ + case 2: pci_write_config16(dev, 0x66, reg_var[1]); - case 0: + /* fall through */ + case 1: pci_write_config16(dev, 0x64, reg_var[0]); break; } diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 649add5515..580138a470 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -220,11 +220,13 @@ static void sb800_lpc_enable_childrens_resources(struct device *dev) pci_write_config32(dev, 0x48, reg_x); /* Set WideIO for as many IOs found (fall through is on purpose) */ switch (var_num) { - case 2: + case 3: pci_write_config16(dev, 0x90, reg_var[2]); - case 1: + /* fall through */ + case 2: pci_write_config16(dev, 0x66, reg_var[1]); - case 0: + /* fall through */ + case 1: pci_write_config16(dev, 0x64, reg_var[0]); break; } diff --git a/src/southbridge/amd/sb800/usb.c b/src/southbridge/amd/sb800/usb.c index bc8c1c664e..063750dc46 100644 --- a/src/southbridge/amd/sb800/usb.c +++ b/src/southbridge/amd/sb800/usb.c @@ -42,7 +42,6 @@ static void usb_init(struct device *dev) /* RPR 7.4 Enable the USB controller to get reset by any software that generate a PCIRst# condition */ byte = pm_ioread(0xF0); byte |= (1 << 2); - byte |= 3 << 8; /* rpr 7.5 */ pm_iowrite(0xF0, byte); /* RPR 7.9 Disable OHCI MSI Capability. */ diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index 6c42fdde4d..5c3aee7995 100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -360,41 +360,53 @@ const u8 pGpp111111[] = {0x0E, 0x0E, 0x0E, 0x0E, 0, 0x0E, 0x0E}; static void gpp3a_cpl_buf_alloc(struct device *nb_dev, struct device *dev) { u8 dev_index; - u8 *slave_cpl; u8 value; struct southbridge_amd_sr5650_config *cfg = (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; dev_index = dev->path.pci.devfn >> 3; - if (dev_index < 4 || dev_index > 0xa) { + + if (dev_index < 4) return; - } + + dev_index -= 4; switch (cfg->gpp3a_configuration) { case 0x1: /* 4:2:0:0:0:0 */ - slave_cpl = (u8 *)&pGpp420000; + if (dev_index >= ARRAY_SIZE(pGpp420000)) + return; + value = pGpp420000[dev_index]; break; case 0x2: /* 4:1:1:0:0:0 */ - slave_cpl = (u8 *)&pGpp411000; + if (dev_index >= ARRAY_SIZE(pGpp411000)) + return; + value = pGpp411000[dev_index]; break; case 0xC: /* 2:2:2:0:0:0 */ - slave_cpl = (u8 *)&pGpp222000; + if (dev_index >= ARRAY_SIZE(pGpp222000)) + return; + value = pGpp222000[dev_index]; break; case 0xA: /* 2:2:1:1:0:0 */ - slave_cpl = (u8 *)&pGpp221100; + if (dev_index >= ARRAY_SIZE(pGpp221100)) + return; + value = pGpp221100[dev_index]; break; case 0x4: /* 2:1:1:1:1:0 */ - slave_cpl = (u8 *)&pGpp211110; + if (dev_index >= ARRAY_SIZE(pGpp211110)) + return; + value = pGpp211110[dev_index]; break; case 0xB: /* 1:1:1:1:1:1 */ - slave_cpl = (u8 *)&pGpp111111; + if (dev_index >= ARRAY_SIZE(pGpp111111)) + return; + value = pGpp111111[dev_index]; break; default: /* shouldn't be here. */ printk(BIOS_WARNING, "buggy gpp3a_configuration\n"); return; } - value = slave_cpl[dev_index - 4]; if (value != 0) { set_pcie_enable_bits(dev, 0x10, 0x3f << 8, value << 8); set_pcie_enable_bits(dev, 0x20, 1 << 11, 1 << 11); diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 8d424b8ba6..e3379d6af0 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -242,11 +242,11 @@ static void azalia_init(struct device *dev) base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); - if (RCBA32(0x2030) & (1 << 31)) { + if (RCBA32(CIR31) & (1 << 31)) { reg32 = pci_read_config32(dev, 0x120); reg32 &= 0xf8ffff01; reg32 |= (1 << 24); // 2 << 24 for server - reg32 |= RCBA32(0x2030) & 0xfe; + reg32 |= RCBA32(CIR31) & 0xfe; pci_write_config32(dev, 0x120, reg32); reg16 = pci_read_config16(dev, 0x78); diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 29f6881fc2..4be91522d2 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -82,7 +82,6 @@ struct southbridge_intel_bd82x6x_config { uint8_t pcie_aspm_f6; uint8_t pcie_aspm_f7; - int p_cnt_throttling_supported; int c2_latency; int docking_supported; diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index c1631f4229..73fce3bf9f 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -72,24 +72,24 @@ write_iobp(u32 address, u32 val) void early_pch_init_native_dmi_pre(void) { /* Link Capabilities Register */ - RCBA32(0x21a4) = (RCBA32(0x21a4) & ~0x3fc00) | + RCBA32(LCAP) = (RCBA32(LCAP) & ~0x3fc00) | (3 << 10) | // L0s and L1 entry supported (2 << 12) | // L0s 128 ns to less than 256 ns (2 << 15); // L1 2 us to less than 4 us RCBA32(0x2340) = (RCBA32(0x2340) & ~0xff0000) | (0x3a << 16); - RCBA8(0x21b0) = (RCBA8(0x21b0) & ~0xf) | 2; + RCBA8(DLCTL2) = (RCBA8(DLCTL2) & ~0xf) | 2; } void early_pch_init_native_dmi_post(void) { - RCBA32(0x0050); // !!! = 0x01200654 - RCBA32(0x0050) = 0x01200654; - RCBA32(0x0050); // !!! = 0x01200654 - RCBA32(0x0050) = 0x012a0654; - RCBA32(0x0050); // !!! = 0x012a0654 - RCBA8(0x1114); // !!! = 0x00 - RCBA8(0x1114) = 0x05; + RCBA32(CIR0); // !!! = 0x01200654 + RCBA32(CIR0) = 0x01200654; + RCBA32(CIR0); // !!! = 0x01200654 + RCBA32(CIR0) = 0x012a0654; + RCBA32(CIR0); // !!! = 0x012a0654 + RCBA8(UPDCR); // !!! = 0x00 + RCBA8(UPDCR) = 0x05; /* * Virtual Channel resources must match settings in DMIBAR! @@ -106,42 +106,42 @@ void early_pch_init_native_dmi_post(void) * Map TC0 and TC3 and TC4 to VC0. */ - RCBA32(0x2014) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; + RCBA32(V0CTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; /* Virtual Channel 1 Resource Control Register. * Enable channel. * Set Virtual Channel Identifier. * Map TC1 and TC5 to VC1. */ - RCBA32(0x2020) = (1 << 31) | (1 << 24) | (0x11 << 1); + RCBA32(V1CTL) = (1 << 31) | (1 << 24) | (0x11 << 1); /* Read back register */ - RCBA32(0x2020); + RCBA32(V1CTL); /* Virtual Channel private Resource Control Register. * Enable channel. * Set Virtual Channel Identifier. * Map TC2 and TC6 to VCp. */ - RCBA32(0x2030) = (1 << 31) | (2 << 24) | (0x22 << 1); + RCBA32(CIR31) = (1 << 31) | (2 << 24) | (0x22 << 1); /* Read back register */ - RCBA32(0x2030); + RCBA32(CIR31); /* Virtual Channel ME Resource Control Register. * Enable channel. * Set Virtual Channel Identifier. * Map TC7 to VCm. */ - RCBA32(0x2040) = (1 << 31) | (7 << 24) | (0x40 << 1); + RCBA32(CIR32) = (1 << 31) | (7 << 24) | (0x40 << 1); /* Lock Virtual Channel Resource control register. */ - RCBA32(0x0050) |= 0x80000000; + RCBA32(CIR0) |= TCLOCKDN; /* Read back register */ - RCBA32(0x0050); + RCBA32(CIR0); /* Wait for virtual channels negotiation pending */ - while (RCBA16(0x201a) & VCNEGPND) + while (RCBA16(V0STS) & VCNEGPND) ; - while (RCBA16(0x2026) & VCNEGPND) + while (RCBA16(V1STS) & VCNEGPND) ; while (RCBA16(0x2036) & VCNEGPND) ; @@ -155,17 +155,17 @@ early_pch_init_native (void) pci_write_config8 (SOUTHBRIDGE, 0xa6, pci_read_config8 (SOUTHBRIDGE, 0xa6) | 2); - RCBA32(0x2088) = 0x00109000; - RCBA32(0x20ac); // !!! = 0x00000000 - RCBA32(0x20ac) = 0x40000000; + RCBA32(CIR1) = 0x00109000; + RCBA32(REC); // !!! = 0x00000000 + RCBA32(REC) = 0x40000000; RCBA32(0x100c) = 0x01110000; RCBA8(0x2340) = 0x1b; - RCBA32(0x2314); // !!! = 0x0a080000 - RCBA32(0x2314) = 0x0a280000; + RCBA32(CIR6); // !!! = 0x0a080000 + RCBA32(CIR6) = 0x0a280000; RCBA32(0x2310); // !!! = 0xc809605b RCBA32(0x2310) = 0xa809605b; - RCBA32(0x2324) = 0x00854c74; - RCBA8(0x0400); // !!! = 0x00 + RCBA32(DMC2) = 0x00854c74; + RCBA8(RPC); // !!! = 0x00 RCBA32(0x2310); // !!! = 0xa809605b RCBA32(0x2310) = 0xa809605b; RCBA32(0x2310); // !!! = 0xa809605b diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index e5d5625cab..e735e21656 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -39,7 +39,7 @@ void early_usb_init(const struct southbridge_usb_port *portmap) write_pmbase16(UPRWC, read_pmbase16(UPRWC) | UPRWC_WR_EN); for (i = 0; i < 14; i++) - RCBA32(0x3500 + 4 * i) = currents[portmap[i].current]; + RCBA32(USBIR0 + 4 * i) = currents[portmap[i].current]; for (i = 0; i < 10; i++) RCBA32(0x3538 + 4 * i) = 0; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 661c1d483d..bd3c993912 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -269,9 +269,9 @@ static void pch_power_options(struct device *dev) outl(reg32, pmbase + 0x04); /* Clear magic status bits to prevent unexpected wake */ - reg32 = RCBA32(0x3310); + reg32 = RCBA32(PRSTS); reg32 |= (1 << 4)|(1 << 5)|(1 << 0); - RCBA32(0x3310) = reg32; + RCBA32(PRSTS) = reg32; reg32 = RCBA32(0x3f02); reg32 &= ~0xf; @@ -283,40 +283,40 @@ static void cpt_pm_init(struct device *dev) { printk(BIOS_DEBUG, "CougarPoint PM init\n"); pci_write_config8(dev, 0xa9, 0x47); - RCBA32_AND_OR(0x2238, ~0UL, (1 << 6)|(1 << 0)); - RCBA32_AND_OR(0x228c, ~0UL, (1 << 0)); - RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14)); - RCBA16_AND_OR(0x0900, ~0UL, (1 << 14)); - RCBA32(0x2304) = 0xc0388400; - RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18)); - RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1)); - RCBA32_AND_OR(0x3314, ~0x1f, 0xf); - RCBA32(0x3318) = 0x050f0000; - RCBA32(0x3324) = 0x04000000; - RCBA32_AND_OR(0x3340, ~0UL, 0xfffff); - RCBA32_AND_OR(0x3344, ~0UL, (1 << 1)); - RCBA32(0x3360) = 0x0001c000; - RCBA32(0x3368) = 0x00061100; - RCBA32(0x3378) = 0x7f8fdfff; - RCBA32(0x337c) = 0x000003fc; - RCBA32(0x3388) = 0x00001000; - RCBA32(0x3390) = 0x0001c000; - RCBA32(0x33a0) = 0x00000800; - RCBA32(0x33b0) = 0x00001000; - RCBA32(0x33c0) = 0x00093900; - RCBA32(0x33cc) = 0x24653002; - RCBA32(0x33d0) = 0x062108fe; - RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060); - RCBA32(0x3a28) = 0x01010000; - RCBA32(0x3a2c) = 0x01010404; - RCBA32(0x3a80) = 0x01041041; - RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001); - RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */ - RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0)); /* SATA 4/5 disabled */ - RCBA32(0x3a6c) = 0x00000001; + RCBA32_AND_OR(CIR30, ~0UL, (1 << 6)|(1 << 0)); + RCBA32_AND_OR(CIR5, ~0UL, (1 << 0)); + RCBA16_AND_OR(CIR3, ~0UL, (1 << 13)|(1 << 14)); + RCBA16_AND_OR(CIR2, ~0UL, (1 << 14)); + RCBA32(DMC) = 0xc0388400; + RCBA32_AND_OR(CIR6, ~0UL, (1 << 5)|(1 << 18)); + RCBA32_AND_OR(CIR9, ~0UL, (1 << 15)|(1 << 1)); + RCBA32_AND_OR(CIR7, ~0x1f, 0xf); + RCBA32(PM_CFG) = 0x050f0000; + RCBA32(CIR8) = 0x04000000; + RCBA32_AND_OR(CIR10, ~0UL, 0xfffff); + RCBA32_AND_OR(CIR11, ~0UL, (1 << 1)); + RCBA32(CIR12) = 0x0001c000; + RCBA32(CIR14) = 0x00061100; + RCBA32(CIR15) = 0x7f8fdfff; + RCBA32(CIR13) = 0x000003fc; + RCBA32(CIR16) = 0x00001000; + RCBA32(CIR18) = 0x0001c000; + RCBA32(CIR17) = 0x00000800; + RCBA32(CIR23) = 0x00001000; + RCBA32(CIR19) = 0x00093900; + RCBA32(CIR20) = 0x24653002; + RCBA32(CIR21) = 0x062108fe; + RCBA32_AND_OR(CIR22, 0xf000f000, 0x00670060); + RCBA32(CIR24) = 0x01010000; + RCBA32(CIR25) = 0x01010404; + RCBA32(CIR27) = 0x01041041; + RCBA32_AND_OR(CIR28, ~0x0000ffff, 0x00001001); + RCBA32_AND_OR(CIR28, ~0UL, (1 << 24)); /* SATA 2/3 disabled */ + RCBA32_AND_OR(CIR29, ~0UL, (1 << 0)); /* SATA 4/5 disabled */ + RCBA32(CIR26) = 0x00000001; RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c); RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20); - RCBA32(0x33c8) = 0; + RCBA32(PMSYNC_CFG) = 0; RCBA32_AND_OR(0x21b0, ~0UL, 0xf); } @@ -325,41 +325,41 @@ static void ppt_pm_init(struct device *dev) { printk(BIOS_DEBUG, "PantherPoint PM init\n"); pci_write_config8(dev, 0xa9, 0x47); - RCBA32_AND_OR(0x2238, ~0UL, (1 << 0)); - RCBA32_AND_OR(0x228c, ~0UL, (1 << 0)); - RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14)); - RCBA16_AND_OR(0x0900, ~0UL, (1 << 14)); - RCBA32(0x2304) = 0xc03b8400; - RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18)); - RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1)); - RCBA32_AND_OR(0x3314, ~0x1f, 0xf); - RCBA32(0x3318) = 0x054f0000; - RCBA32(0x3324) = 0x04000000; - RCBA32_AND_OR(0x3340, ~0UL, 0xfffff); - RCBA32_AND_OR(0x3344, ~0UL, (1 << 1)|(1 << 0)); - RCBA32(0x3360) = 0x0001c000; - RCBA32(0x3368) = 0x00061100; - RCBA32(0x3378) = 0x7f8fdfff; - RCBA32(0x337c) = 0x000003fd; - RCBA32(0x3388) = 0x00001000; - RCBA32(0x3390) = 0x0001c000; - RCBA32(0x33a0) = 0x00000800; - RCBA32(0x33b0) = 0x00001000; - RCBA32(0x33c0) = 0x00093900; - RCBA32(0x33cc) = 0x24653002; - RCBA32(0x33d0) = 0x067388fe; - RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060); - RCBA32(0x3a28) = 0x01010000; - RCBA32(0x3a2c) = 0x01010404; - RCBA32(0x3a80) = 0x01040000; - RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001); - RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */ - RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0)); /* SATA 4/5 disabled */ - RCBA32(0x3a6c) = 0x00000001; + RCBA32_AND_OR(CIR30, ~0UL, (1 << 0)); + RCBA32_AND_OR(CIR5, ~0UL, (1 << 0)); + RCBA16_AND_OR(CIR3, ~0UL, (1 << 13)|(1 << 14)); + RCBA16_AND_OR(CIR2, ~0UL, (1 << 14)); + RCBA32(DMC) = 0xc03b8400; + RCBA32_AND_OR(CIR6, ~0UL, (1 << 5)|(1 << 18)); + RCBA32_AND_OR(CIR9, ~0UL, (1 << 15)|(1 << 1)); + RCBA32_AND_OR(CIR7, ~0x1f, 0xf); + RCBA32(PM_CFG) = 0x054f0000; + RCBA32(CIR8) = 0x04000000; + RCBA32_AND_OR(CIR10, ~0UL, 0xfffff); + RCBA32_AND_OR(CIR11, ~0UL, (1 << 1)|(1 << 0)); + RCBA32(CIR12) = 0x0001c000; + RCBA32(CIR14) = 0x00061100; + RCBA32(CIR15) = 0x7f8fdfff; + RCBA32(CIR13) = 0x000003fd; + RCBA32(CIR16) = 0x00001000; + RCBA32(CIR18) = 0x0001c000; + RCBA32(CIR17) = 0x00000800; + RCBA32(CIR23) = 0x00001000; + RCBA32(CIR19) = 0x00093900; + RCBA32(CIR20) = 0x24653002; + RCBA32(CIR21) = 0x067388fe; + RCBA32_AND_OR(CIR22, 0xf000f000, 0x00670060); + RCBA32(CIR24) = 0x01010000; + RCBA32(CIR25) = 0x01010404; + RCBA32(CIR27) = 0x01040000; + RCBA32_AND_OR(CIR28, ~0x0000ffff, 0x00001001); + RCBA32_AND_OR(CIR28, ~0UL, (1 << 24)); /* SATA 2/3 disabled */ + RCBA32_AND_OR(CIR29, ~0UL, (1 << 0)); /* SATA 4/5 disabled */ + RCBA32(CIR26) = 0x00000001; RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c); RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20); RCBA32_AND_OR(0x33a4, ~0UL, (1 << 0)); - RCBA32(0x33c8) = 0; + RCBA32(PMSYNC_CFG) = 0; RCBA32_AND_OR(0x21b0, ~0UL, 0xf); } @@ -385,7 +385,7 @@ static void enable_clock_gating(struct device *dev) u32 reg32; u16 reg16; - RCBA32_AND_OR(0x2234, ~0UL, 0xf); + RCBA32_AND_OR(DMIC, ~0UL, 0xf); reg16 = pci_read_config16(dev, GEN_PMCON_1); reg16 |= (1 << 2) | (1 << 11); @@ -453,9 +453,9 @@ static void pch_fixups(struct device *dev) /* * Enable DMI ASPM in the PCH */ - RCBA32_AND_OR(0x2304, ~(1 << 10), 0); - RCBA32_OR(0x21a4, (1 << 11)|(1 << 10)); - RCBA32_OR(0x21a8, 0x3); + RCBA32_AND_OR(DMC, ~(1 << 10), 0); + RCBA32_OR(LCAP, (1 << 11)|(1 << 10)); + RCBA32_OR(LCTL, 0x3); } static void pch_decode_init(struct device *dev) @@ -768,12 +768,10 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->p_lvl3_lat = 87; fadt->flush_size = 1024; fadt->flush_stride = 16; - fadt->duty_offset = 1; - if (chip->p_cnt_throttling_supported) { - fadt->duty_width = 3; - } else { - fadt->duty_width = 0; - } + /* P_CNT not supported */ + fadt->duty_offset = 0; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x00; diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index f8540af451..e4eccd766d 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -148,6 +148,12 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) static void pch_hide_devfn(unsigned devfn) { switch (devfn) { + case PCI_DEVFN(20, 0): /* xHCI */ + if (pch_silicon_type() == PCH_TYPE_PPT) { + /* on CPT this bit is reserved */ + RCBA32_OR(FD, PCH_DISABLE_XHCI); + } + break; case PCI_DEVFN(22, 0): /* MEI #1 */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); break; diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 4369b5c162..bc6c8b333f 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -256,19 +256,8 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define PMBASE 0x40 -#define VCH 0x0000 /* 32bit */ -#define VCAP1 0x0004 /* 32bit */ -#define VCAP2 0x0008 /* 32bit */ -#define PVC 0x000c /* 16bit */ -#define PVS 0x000e /* 16bit */ - -#define V0CAP 0x0010 /* 32bit */ -#define V0CTL 0x0014 /* 32bit */ -#define V0STS 0x001a /* 16bit */ - -#define V1CAP 0x001c /* 32bit */ -#define V1CTL 0x0020 /* 32bit */ -#define V1STS 0x0026 /* 16bit */ +#define CIR0 0x0050 /* 32bit */ +#define TCLOCKDN (1u << 31) #define RCTCL 0x0100 /* 32bit */ #define ESD 0x0104 /* 32bit */ @@ -293,6 +282,10 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define RPC 0x0400 /* 32bit */ #define RPFN 0x0404 /* 32bit */ +#define CIR2 0x900 /* 16bit */ +#define CIR3 0x1100 /* 16bit */ +#define UPDCR 0x1114 /* 32bit */ + /* Root Port configuratinon space hide */ #define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) /* Get the function number assigned to a Root Port */ @@ -335,6 +328,27 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define PIRQG 6 #define PIRQH 7 +/* DMI control */ +#define V0CTL 0x2014 /* 32bit */ +#define V0STS 0x201a /* 16bit */ +#define V1CTL 0x2020 /* 32bit */ +#define V1STS 0x2026 /* 16bit */ +#define CIR31 0x2030 /* 32bit */ +#define CIR32 0x2040 /* 32bit */ +#define CIR1 0x2088 /* 32bit */ +#define REC 0x20ac /* 32bit */ +#define LCAP 0x21a4 /* 32bit */ +#define LCTL 0x21a8 /* 16bit */ +#define LSTS 0x21aa /* 16bit */ +#define DLCTL2 0x21b0 /* 16bit */ +#define DMIC 0x2234 /* 32bit */ +#define CIR30 0x2238 /* 32bit */ +#define CIR5 0x228c /* 32bit */ +#define DMC 0x2304 /* 32bit */ +#define CIR6 0x2314 /* 32bit */ +#define CIR9 0x2320 /* 32bit */ +#define DMC2 0x2324 /* 32bit - name guessed */ + /* IO Buffer Programming */ #define IOBPIRI 0x2330 #define IOBPD 0x2334 @@ -391,6 +405,26 @@ early_usb_init (const struct southbridge_usb_port *portmap); RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ ((b) << DIR_IBR) | ((a) << DIR_IAR)) +#define PRSTS 0x3310 /* 32bit */ +#define CIR7 0x3314 /* 32bit */ +#define PM_CFG 0x3318 /* 32bit */ +#define CIR8 0x3324 /* 32bit */ +#define CIR10 0x3340 /* 32bit */ +#define CIR11 0x3344 /* 32bit */ +#define CIR12 0x3360 /* 32bit */ +#define CIR14 0x3368 /* 32bit */ +#define CIR15 0x3378 /* 32bit */ +#define CIR13 0x337c /* 32bit */ +#define CIR16 0x3388 /* 32bit */ +#define CIR18 0x3390 /* 32bit */ +#define CIR17 0x33a0 /* 32bit */ +#define CIR23 0x33b0 /* 32bit */ +#define CIR19 0x33c0 /* 32bit */ +#define PMSYNC_CFG 0x33c8 /* 32bit */ +#define CIR20 0x33cc /* 32bit */ +#define CIR21 0x33d0 /* 32bit */ +#define CIR22 0x33d4 /* 32bit */ + #define RC 0x3400 /* 32bit */ #define HPTC 0x3404 /* 32bit */ #define GCS 0x3410 /* 32bit */ @@ -422,11 +456,38 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define PCH_DISABLE_MEI1 (1 << 1) #define PCH_ENABLE_DBDF (1 << 0) +/* USB Initialization Registers[13:0] */ +#define USBIR0 0x3500 /* 32bit */ +#define USBIR1 0x3504 /* 32bit */ +#define USBIR2 0x3508 /* 32bit */ +#define USBIR3 0x350c /* 32bit */ +#define USBIR4 0x3510 /* 32bit */ +#define USBIR5 0x3514 /* 32bit */ +#define USBIR6 0x3518 /* 32bit */ +#define USBIR7 0x351c /* 32bit */ +#define USBIR8 0x3520 /* 32bit */ +#define USBIR9 0x3524 /* 32bit */ +#define USBIR10 0x3528 /* 32bit */ +#define USBIR11 0x352c /* 32bit */ +#define USBIR12 0x3530 /* 32bit */ +#define USBIR13 0x3534 /* 32bit */ + +/* Miscellaneous Control Register */ +#define MISCCTL 0x3590 /* 32bit */ /* USB Port Disable Override */ #define USBPDO 0x359c /* 32bit */ /* USB Overcurrent MAP Register */ #define USBOCM1 0x35a0 /* 32bit */ #define USBOCM2 0x35a4 /* 32bit */ +/* Rate Matching Hub Wake Control Register */ +#define RMHWKCTL 0x35b0 /* 32bit */ + +#define CIR24 0x3a28 /* 32bit */ +#define CIR25 0x3a2c /* 32bit */ +#define CIR26 0x3a6c /* 32bit */ +#define CIR27 0x3a80 /* 32bit */ +#define CIR28 0x3a84 /* 32bit */ +#define CIR29 0x3a88 /* 32bit */ /* XHCI USB 3.0 */ #define XOCM 0xc0 /* 32bit */ diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 0bc75b54a5..97306e44cb 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -114,7 +114,7 @@ static void pch_pcie_pm_early(struct device *dev) /* Adjust ASPM L1 exit latency */ reg32 = pci_read_config32(dev, 0x4c); reg32 &= ~((1 << 17) | (1 << 16) | (1 << 15)); - if (RCBA32(0x2320) & (1 << 16)) { + if (RCBA32(CIR9) & (1 << 16)) { /* If RCBA+2320[15]=1 set ASPM L1 to 8-16us */ reg32 |= (1 << 17); } else { diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index 8fe3e41d6d..2c2f9d97e9 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -28,9 +28,9 @@ static void usb_ehci_init(struct device *dev) u32 reg32; /* Disable Wake on Disconnect in RMH */ - reg32 = RCBA32(0x35b0); + reg32 = RCBA32(RMHWKCTL); reg32 |= 0x22; - RCBA32(0x35b0) = reg32; + RCBA32(RMHWKCTL) = reg32; printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 8430dc8611..0095dd9ccb 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -28,7 +28,6 @@ #include #include #include - #include #include "spi.h" @@ -727,7 +726,7 @@ static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset, u32 start, end, erase_size; int ret; uint16_t hsfc; - uint16_t timeout = 1000 * 60; + unsigned int timeout = 1000 * SPI_FLASH_SECTOR_ERASE_TIMEOUT_MS; erase_size = flash->sector_size; if (offset % erase_size || len % erase_size) { @@ -1082,7 +1081,7 @@ void spi_finalize_ops(void) optype |= (spi_config.ops[i].type & 3) << (i * 2); writeb_(spi_config.ops[i].op, &cntlr->opmenu[i]); } - writew_(optype, &cntlr->optype); + writew_(optype, cntlr->optype); } __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config) diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 8909f50bc1..4e78c30db2 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -68,7 +68,6 @@ struct southbridge_intel_i82801gx_config { uint16_t alt_gp_smi_en; /* IDE configuration */ - uint32_t ide_legacy_combined; uint32_t ide_enable_primary; uint32_t ide_enable_secondary; enum sata_mode sata_mode; diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 6236ebd800..4e2f9f959e 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -331,8 +331,7 @@ static void enable_clock_gating(void) RCBA32(CG) = reg32; } -#if CONFIG(HAVE_SMI_HANDLER) -static void i82801gx_lock_smm(struct device *dev) +static void i82801gx_set_acpi_mode(struct device *dev) { if (!acpi_is_wakeup_s3()) { #if ENABLE_ACPI_MODE_IN_COREBOOT @@ -349,7 +348,6 @@ static void i82801gx_lock_smm(struct device *dev) outb(APM_CNT_ACPI_ENABLE, APM_CNT); } } -#endif #define SPIBASE 0x3020 static void i82801gx_spi_init(void) @@ -415,9 +413,8 @@ static void lpc_init(struct device *dev) /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); -#if CONFIG(HAVE_SMI_HANDLER) - i82801gx_lock_smm(dev); -#endif + if (CONFIG(HAVE_SMI_HANDLER)) + i82801gx_set_acpi_mode(dev); i82801gx_spi_init(); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 546fbced77..ba2b0282e5 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -366,7 +366,7 @@ static void enable_clock_gating(void) RCBA32(0x38c0) |= 7; } -static void i82801ix_lock_smm(struct device *dev) +static void i82801ix_set_acpi_mode(struct device *dev) { if (!acpi_is_wakeup_s3()) { #if ENABLE_ACPI_MODE_IN_COREBOOT @@ -382,11 +382,6 @@ static void i82801ix_lock_smm(struct device *dev) printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); outb(APM_CNT_ACPI_ENABLE, APM_CNT); } - /* Don't allow evil boot loaders, kernels, or - * userspace applications to deceive us: - */ - if (!CONFIG(PARALLEL_MP)) - aseg_smm_lock(); } static void lpc_init(struct device *dev) @@ -430,7 +425,13 @@ static void lpc_init(struct device *dev) i8259_configure_irq_trigger(9, 1); if (CONFIG(HAVE_SMI_HANDLER)) - i82801ix_lock_smm(dev); + i82801ix_set_acpi_mode(dev); + + /* Don't allow evil boot loaders, kernels, or + * userspace applications to deceive us: + */ + if (CONFIG(HAVE_SMI_HANDLER) && CONFIG(SMM_ASEG)) + aseg_smm_lock(); } static void i82801ix_lpc_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 5373ba2022..0fcb521430 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -371,8 +371,7 @@ static void enable_clock_gating(void) RCBA32(0x38c0) |= 7; } -#if CONFIG(HAVE_SMI_HANDLER) -static void i82801jx_lock_smm(struct device *dev) +static void i82801jx_set_acpi_mode(struct device *dev) { if (!acpi_is_wakeup_s3()) { #if ENABLE_ACPI_MODE_IN_COREBOOT @@ -389,7 +388,6 @@ static void i82801jx_lock_smm(struct device *dev) outb(APM_CNT_ACPI_ENABLE, APM_CNT); } } -#endif static void lpc_init(struct device *dev) { @@ -431,9 +429,8 @@ static void lpc_init(struct device *dev) /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); -#if CONFIG(HAVE_SMI_HANDLER) - i82801jx_lock_smm(dev); -#endif + if (CONFIG(HAVE_SMI_HANDLER)) + i82801jx_set_acpi_mode(dev); } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index fa1ca92d78..c7464a05f1 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -680,12 +680,10 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->p_lvl3_lat = 87; fadt->flush_size = 1024; fadt->flush_stride = 16; - fadt->duty_offset = 1; - if (chip->p_cnt_throttling_supported) { - fadt->duty_width = 3; - } else { - fadt->duty_width = 0; - } + /* P_CNT not supported */ + fadt->duty_offset = 0; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x32; diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc index 796e5194d1..db683fdfe6 100644 --- a/src/superio/fintek/Makefile.inc +++ b/src/superio/fintek/Makefile.inc @@ -26,3 +26,4 @@ subdirs-y += f71872 subdirs-y += f81216h subdirs-y += f81865f subdirs-y += f81866d +subdirs-y += f81803a diff --git a/src/superio/fintek/common/fan_api_call.c b/src/superio/fintek/common/fan_api_call.c new file mode 100644 index 0000000000..1bd5b2e7d4 --- /dev/null +++ b/src/superio/fintek/common/fan_api_call.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Richard Spiegel + * Copyright (C) 2019 Silverback ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "fan_control.h" + +static int check_status(int status) +{ + if (status < HWM_STATUS_SUCCESS) + return status; + return HWM_STATUS_SUCCESS; /* positive values are warnings only */ +} + +int set_fan(struct fintek_fan *fan_init) +{ + int s; + + s = set_sensor_type(CONFIG_HWM_PORT, fan_init->sensor, fan_init->stype); + if (check_status(s) != HWM_STATUS_SUCCESS) + return s; + + s = set_fan_temperature_source(CONFIG_HWM_PORT, fan_init->fan, fan_init->temp_source); + if (check_status(s) != HWM_STATUS_SUCCESS) + return s; + + s = set_fan_type_mode(CONFIG_HWM_PORT, fan_init->fan, fan_init->ftype, fan_init->fmode); + if (check_status(s) != HWM_STATUS_SUCCESS) + return s; + + s = set_pwm_frequency(CONFIG_HWM_PORT, fan_init->fan, fan_init->fan_freq); + if (check_status(s) != HWM_STATUS_SUCCESS) + return s; + + s = set_fan_speed_change_rate(CONFIG_HWM_PORT, fan_init->fan, fan_init->rate_up, + fan_init->rate_down); + if (check_status(s) != HWM_STATUS_SUCCESS) + return s; + + s = set_fan_follow(CONFIG_HWM_PORT, fan_init->fan, fan_init->follow); + if (check_status(s) != HWM_STATUS_SUCCESS) + return s; + + s = set_sections(CONFIG_HWM_PORT, fan_init->fan, fan_init->boundaries, + fan_init->sections); + if (check_status(s) != HWM_STATUS_SUCCESS) + return s; + + printk(BIOS_DEBUG, "Fan %d completed\n", fan_init->fan); + return HWM_STATUS_SUCCESS; +} diff --git a/src/superio/fintek/common/fan_control.h b/src/superio/fintek/common/fan_control.h new file mode 100644 index 0000000000..fbe784bfa1 --- /dev/null +++ b/src/superio/fintek/common/fan_control.h @@ -0,0 +1,199 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Richard Spiegel + * Copyright (C) 2019 Silverback ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_FINTEK_FAN_CONTROL_H +#define SUPERIO_FINTEK_FAN_CONTROL_H + +#include +#include + +typedef enum { + IGNORE_SENSOR = 0, + EXTERNAL_SENSOR1, + EXTERNAL_SENSOR2, + EXTERNAL_SENSOR3, + EXTERNAL_SENSOR4 +} external_sensor; + +typedef enum { + TEMP_SENSOR_THERMISTOR = 0, + TEMP_SENSOR_BJT, + TEMP_SENSOR_DEFAULT +} temp_sensor_type; + +typedef enum { + FAN_TYPE_PWM_PUSH_PULL = 0, + FAN_TYPE_DAC_POWER, + FAN_TYPE_PWM_OPEN_DRAIN, + FAN_TYPE_RESERVED +} fan_type; +#define FAN_TYPE_PWM_CHECK 1 /* bit 0 must be 0 for PWM */ + +typedef enum { + FAN_MODE_AUTO_RPM = 0, + FAN_MODE_AUTO_PWM_DAC, + FAN_MODE_MANUAL_RPM, + FAN_MODE_MANUAL_PWM_DAC, + FAN_MODE_DEFAULT +} fan_mode; + +typedef enum { + FAN_PWM_FREQ_23500 = 0, + FAN_PWM_FREQ_11750, + FAN_PWM_FREQ_5875, + FAN_PWM_FREQ_220 +} fan_pwm_freq; + +typedef enum { + FAN_TEMP_PECI = 0, + FAN_TEMP_EXTERNAL_1, + FAN_TEMP_EXTERNAL_2, + FAN_TEMP_TSI = 4, + FAN_TEMP_MXM, +} fan_temp_source; + +typedef enum { + FAN_UP_RATE_2HZ = 0, + FAN_UP_RATE_5HZ, + FAN_UP_RATE_10HZ, + FAN_UP_RATE_20HZ, + FAN_UP_RATE_DEFAULT, + FAN_UP_RATE_JUMP = 8 +} fan_rate_up; + +typedef enum { + FAN_DOWN_RATE_2HZ = 0, + FAN_DOWN_RATE_5HZ, + FAN_DOWN_RATE_10HZ, + FAN_DOWN_RATE_20HZ, + FAN_DOWN_RATE_DEFAULT, + FAN_DOWN_RATE_SAME_AS_UP, + FAN_DOWN_RATE_JUMP = 8 +} fan_rate_down; + +typedef enum { + FAN_FOLLOW_STEP = 0, + FAN_FOLLOW_INTERPOLATION +} fan_follow; + +struct fintek_fan { + uint8_t fan; + external_sensor sensor; + temp_sensor_type stype; + fan_temp_source temp_source; + fan_type ftype; + fan_mode fmode; + fan_pwm_freq fan_freq; + fan_rate_up rate_up; + fan_rate_down rate_down; + fan_follow follow; + uint8_t *boundaries; + uint8_t *sections; +}; + +#define HWM_STATUS_SUCCESS 0 +#define HWM_STATUS_INVALID_FAN -1 +#define HWM_STATUS_INVALID_TEMP_SOURCE -2 +#define HWM_STATUS_INVALID_TYPE -3 +#define HWM_STATUS_INVALID_MODE -4 +#define HWM_STATUS_INVALID_RATE -5 +#define HWM_STATUS_INVALID_FREQUENCY -6 +#define HWM_STATUS_INVALID_TEMP_SENSOR -7 +#define HWM_STATUS_INVALID_BOUNDARY_VALUE -8 +#define HWM_STATUS_INVALID_SECTION_VALUE -9 +#define HWM_STATUS_BOUNDARY_WRONG_ORDER -10 +#define HWM_STATUS_SECTIONS_WRONG_ORDER -11 +#define HWM_STATUS_WARNING_SENSOR_DISCONECTED 1 +#define HWM_STATUS_WARNING_FAN_NOT_PWM 2 + +#define CPU_DAMAGE_TEMP 110 + +/* + * Boundaries order is from highest temp. to lowest. Values from 0 to 127. + * Boundaries should be defined as u8 boundaries[FINTEK_BOUNDARIES_SIZE]. + */ +#define FINTEK_BOUNDARIES_SIZE 4 +/* + * Section defines the duty_cycle/voltage to be used based on where the + * temperature lies with respect to the boundaries. There are 5 sections + * (4 boundaries) and the order must be from highest to lowest. Values + * from 0% to 100%, will be converted internally to percent of 255. + * Sections should be defined as u8 sections[FINTEK_SECTIONS_SIZE]. + */ +#define FINTEK_SECTIONS_SIZE 5 + +/* + * When using external sensor, its type must be defined. When using PECI, + * TSI or MXM use IGNORE_SENSOR to indicate so. + */ +int set_sensor_type(u16 base_address, external_sensor sensor, + temp_sensor_type type); + +/* + * Define the temperature source used to control a fan. + */ +int set_fan_temperature_source(u16 base_address, u8 fan, + fan_temp_source source); + +/* + * Define if fan is controlled through PWM or absolute voltage powering it + * (DAC). Then, under mode, define if control is automatic (SIO) or manual + * (CPU, through ACPI). Notice there needs to be a match between type and + * mode (PWM with PWM or DAC with DAC). + */ +int set_fan_type_mode(u16 base_address, u8 fan, fan_type type, fan_mode mode); + +/* + * For fans controlled through pulse width, define the base frequency used. + */ +int set_pwm_frequency(u16 base_address, u8 fan, fan_pwm_freq frequency); + +/* + * For fintek SIO HWM there are 4 (temperature) boundaries points, defining + * 5 sections (1 fan speed per section). Start with the highest temperature/ + * speed. Temperature is in Celsius, speed is in percentile of max speed. The + * highest speed should be 100%, no requirements for minimum speed, could be + * 0 or above 0. + */ +int set_sections(u16 base_address, u8 fan, u8 *boundaries, u8 *sections); + +/* + * Define how often temperature is measured to change fan speed. + */ +int set_fan_speed_change_rate(u16 base_address, u8 fan, fan_rate_up rate_up, + fan_rate_down rate_down); + +/* + * There a 2 ways a fan can be controlled: A single speed per section, or + * interpolation. Under interpolation, the section speed is the speed at the + * lowest temperature of the section (0 Celsius for the lowest section), and + * it's the speed of the next section at the boundary to the next section. + * In between these 2 points, it's a linear function. For example, midway + * between temperature points it'll have a speed that is midway between the + * section speed and next section speed. Obviously, there's no variation for + * the highest section, reason why it must be 100% max speed. + */ +int set_fan_follow(u16 base_address, u8 fan, fan_follow follow); + +/* + * This is an upper level API which calls all the above APIs in the + * appropriate order. Any API failure will be displayed. Alerts will + * also be displayed, but will not interrupt the sequence, while errors + * will interrupt the sequence. + */ +int set_fan(struct fintek_fan *fan_init); + +#endif /* SUPERIO_FINTEK_FAN_CONTROL_H */ diff --git a/src/superio/fintek/f81803a/Kconfig b/src/superio/fintek/f81803a/Kconfig new file mode 100644 index 0000000000..e1aa537e78 --- /dev/null +++ b/src/superio/fintek/f81803a/Kconfig @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2014 Edward O'Callaghan +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_FINTEK_F81803A + bool + select SUPERIO_FINTEK_COMMON_PRE_RAM + +config SUPERIO_FINTEK_FAN_CONTROL + bool + default n + +config SUPERIO_FINTEK_FAN_API_CALL + depends on SUPERIO_FINTEK_FAN_CONTROL + bool + default n diff --git a/src/superio/fintek/f81803a/Makefile.inc b/src/superio/fintek/f81803a/Makefile.inc new file mode 100644 index 0000000000..6fe13aaab7 --- /dev/null +++ b/src/superio/fintek/f81803a/Makefile.inc @@ -0,0 +1,30 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) +bootblock-$(CONFIG_SUPERIO_FINTEK_F81803A) += ../common/early_serial.c +endif + +## Notice: For fan control at romstage, HWM must be initialized before +## the API is called. Ramstage can use devicetree to initialize it. + +romstage-$(CONFIG_SUPERIO_FINTEK_F81803A) += ../common/early_serial.c +romstage-$(CONFIG_SUPERIO_FINTEK_FAN_CONTROL) += fan_control.c +romstage-$(CONFIG_SUPERIO_FINTEK_FAN_API_CALL) += ../common/fan_api_call.c + +ramstage-$(CONFIG_SUPERIO_FINTEK_F81803A) += superio.c +ramstage-$(CONFIG_SUPERIO_FINTEK_FAN_CONTROL) += fan_control.c +ramstage-$(CONFIG_SUPERIO_FINTEK_FAN_API_CALL) += ../common/fan_api_call.c diff --git a/src/superio/fintek/f81803a/acpi/superio.asl b/src/superio/fintek/f81803a/acpi/superio.asl new file mode 100644 index 0000000000..ae8e6dc242 --- /dev/null +++ b/src/superio/fintek/f81803a/acpi/superio.asl @@ -0,0 +1,266 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz + * Copyright (C) 2013 secunet Security Networks AG + * Copyright (C) 2019, Silverback, ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the F81803A SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices and controlling power + * saving mode on logical devices or the whole chip. + * + * LDN State + * 0x1 UARTA Implemented, partially tested + * 0x2 UARTB Implemented, partially tested + * 0x4 HWM Not implemented + * 0x5 KBC Not implemented + * 0x6 GPIO6 Not implemented + * 0x7 WDT0&PLED Not implemented + * 0xa ACPI/PME/ERP Partially implemented + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/o address of the first PnP configuration register + * F81803A_SHOW_UARTA If defined, UARTA will be exposed. + * F81803A_SHOW_UARTB If defined, UARTB will be exposed. + * F81803A_SHOW_HWMON If defined, the hardware monitor will be exposed. + * F81803A_SHOW_PME If defined, the PME/EARP/ACPI will be exposed. + * + * Known issue: + * Do not enable UARTA and UARTB simultaneously, Linux boot will crash. + * Select one or the other. + */ +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME F81803A +#include + +#undef PNP_DEFAULT_PSC +#define PNP_DEFAULT_PSC Return (0) /* no power management */ + +Device(SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Fintek F81803A Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* Mutex for accesses to the configuration ports */ + Mutex(CRMX, 1) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8 + } + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + offset(0xFB), + APC5, 8, /* PME ACPI Control Register 5 */ + } + + Method(_CRS) + { + /* Announce the used i/o ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + }) + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #undef PNP_EXIT_SPECIAL_REG + #undef PNP_EXIT_SPECIAL_VAL + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x87 + #define PNP_EXIT_MAGIC_1ST 0xaa + #include + +#ifdef F81803A_SHOW_UARTA + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 1 + + Device (SUPERIO_ID(SER, SUPERIO_UART_LDN)) { + Name (_HID, EisaId ("PNP0501")) + Name (_UID, SUPERIO_UID(SER, SUPERIO_UART_LDN)) + + Method (_STA) + { + PNP_GENERIC_STA(SUPERIO_UART_LDN) + } + + Method (_CRS, 0, Serialized) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x08, 0x08, IO0) + IRQNoFlags (IR0) {} + }) + ENTER_CONFIG_MODE (SUPERIO_UART_LDN) + PNP_READ_IO(PNP_IO0, CRS, IO0) + PNP_READ_IRQ(PNP_IRQ0, CRS, IR0) + EXIT_CONFIG_MODE () + Return (CRS) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x03f8, 0x03f8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,0) { + IO (Decode16, 0x02f8, 0x02f8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (1,0) { + IO (Decode16, 0x03e8, 0x03e8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (1,0) { + IO (Decode16, 0x02e8, 0x02e8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (2,0) { + IO (Decode16, 0x0100, 0x0ff8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + EndDependentFn() + }) + + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x00, 0x00, IO0) + IRQNoFlags (IR0) {} + }) + ENTER_CONFIG_MODE (SUPERIO_UART_LDN) + PNP_WRITE_IO(PNP_IO0, Arg0, IO0) + PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0) + Store (One, PNP_DEVICE_ACTIVE) + EXIT_CONFIG_MODE () + } + } +#endif + +#ifdef F81803A_SHOW_UARTB + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 2 + + Device (SUPERIO_ID(SER, SUPERIO_UART_LDN)) { + Name (_HID, EisaId ("PNP0501")) + Name (_UID, SUPERIO_UID(SER, SUPERIO_UART_LDN)) + + Method (_STA) + { + PNP_GENERIC_STA(SUPERIO_UART_LDN) + } + + Method (_CRS, 0, Serialized) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x08, 0x08, IO0) + IRQNoFlags (IR0) {} + }) + ENTER_CONFIG_MODE (SUPERIO_UART_LDN) + PNP_READ_IO(PNP_IO0, CRS, IO0) + PNP_READ_IRQ(PNP_IRQ0, CRS, IR0) + EXIT_CONFIG_MODE () + Return (CRS) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x03f8, 0x03f8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,0) { + IO (Decode16, 0x02f8, 0x02f8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (1,0) { + IO (Decode16, 0x03e8, 0x03e8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (1,0) { + IO (Decode16, 0x02e8, 0x02e8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (2,0) { + IO (Decode16, 0x0100, 0x0ff8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + EndDependentFn() + }) + + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x00, 0x00, IO0) + IRQNoFlags (IR0) {} + }) + ENTER_CONFIG_MODE (SUPERIO_UART_LDN) + PNP_WRITE_IO(PNP_IO0, Arg0, IO0) + PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0) + Store (One, PNP_DEVICE_ACTIVE) + EXIT_CONFIG_MODE () + } + } +#endif + +#ifdef F81803A_SHOW_PME + #undef SUPERIO_PME_LDN + #define SUPERIO_PME_LDN 0x0A + + OperationRegion(APCx, SystemIO, APC5, 0x01) + Field(APCx, ByteAcc, Nolock, Preserve) /* bits in PME ACPI CONTROL Reg 5*/ + { + Offset(0x00), /*Control Reg 5 */ + , 7, + PSIN, 1 /* PSIN_FLAG */ + } + + /* routine to clear PSIN_FLAG in ACPI_CONTROL_REG_5 of SIO */ + Method(CPSI, 0, Serialized) + { + /* DBG0("SIO CPSI")*/ + ENTER_CONFIG_MODE(SUPERIO_PME_LDN) + Store(1, PSIN) + EXIT_CONFIG_MODE() + } +#endif +} diff --git a/src/superio/fintek/f81803a/f81803a.h b/src/superio/fintek/f81803a/f81803a.h new file mode 100644 index 0000000000..c986cb806e --- /dev/null +++ b/src/superio/fintek/f81803a/f81803a.h @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Datasheet: + * - Name: F81803A + */ + +#ifndef SUPERIO_FINTEK_F81803_H +#define SUPERIO_FINTEK_F81803_H + +#define LDN_REG 0x07 /* Not defined under PNP */ +/* Logical Device Numbers (LDN) */ + #define F81803A_SP1 0x01 /* UART1 */ + #define F81803A_SP2 0x02 /* UART2 */ + #define F81803A_HWM 0x04 /* Hardware Monitor */ + #define F81803A_KBC 0x05 /* Keyboard/Mouse */ + #define F81803A_GPIO 0x06 /* General Purpose I/O (GPIO) */ + #define F81803A_WDT 0x07 /* Watch Dog Timer */ + #define F81803A_PME 0x0a /* Power Management Events (PME) */ + +/* Global Control Registers */ +#define CLOCK_SELECT_REG 0x26 +#define FUNC_PROG_SELECT (1<<3) +#define PORT_SELECT_REG 0x27 + +#define TSI_LEVEL_SELECT_REG 0x28 /* FUNC_PROG_SEL = 0 */ +#define TSI_PIN_SELECT_REG 0x28 /* FUNC_PROG_SEL = 1 */ +#define MULTI_FUNC_SEL_REG1 0x29 +#define MULTI_FUNC_SEL_REG2 0x2A +#define MULTI_FUNC_SEL_REG3 0x2B +#define MULTI_FUNC_SEL_REG 0x2C +#define WAKEUP_CONTROL_REG 0x2d + +/* LUN A - PME, ACPI, ERP */ +#define PME_DEVICE_ENABLE_REG 0x30 +#define PME_ENABLE (1<<0) +#define PME_ERP_ENABLE_REG 0xE0 +#define ERP_ENABLE (1<<7) +#define ERP_PME_EN (1<<1) +#define ERP_PSOUT_EN (1<<0) +#define PME_ERP_CONTROL_1_REG 0xE1 +#define PME_ERP_CONTROL_2_REG 0xE2 +#define PME_ERP_PSIN_DEBOUNCE_REG 0xE3 +#define PME_ERP_WAKEUP_ENABLE_REG 0xE8 +#define PME_ERP_MODE_SELECT_REG 0xEC +#define PME_EVENT_ENABLE_1_REG 0xF0 +#define PME_EVENT_STATUS_1_REG 0xF1 +#define PME_EVENT_ENABLE_2_REG 0xF2 +#define PME_EVENT_STATUS_2_REG 0xF3 +#define PME_ACPI_CONTROL_1_REG 0xF4 +#define PME_ACPI_CONTROL_2_REG 0xF5 +#define PME_ACPI_CONTROL_3_REG 0xF6 +#define PME_ACPI_CONTROL_4_REG 0xF7 +#define PME_ACPI_CONTROL_5_REG 0xFB +#define PME_ACPI_CONTROL_6_REG 0xFC + +#endif /* SUPERIO_FINTEK_F81803_H */ diff --git a/src/superio/fintek/f81803a/f81803a_hwm.h b/src/superio/fintek/f81803a/f81803a_hwm.h new file mode 100644 index 0000000000..a7647057d1 --- /dev/null +++ b/src/superio/fintek/f81803a/f81803a_hwm.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Richard Spiegel + * Copyright (C) 2019 Silverback ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_FINTEK_F81803_HWM_H +#define SUPERIO_FINTEK_F81803_HWM_H + +#define TP_SENSOR_TYPE 0x6b +#define TP_SENSOR1_TYPE_SHIFT 1 +#define TP_SENSOR2_TYPE_SHIFT 2 +#define TP_SENSOR_TYPE_MASK 0x01 +#define TP_DIODE_STATUS 0x6f +#define TP_MMX_OPEN 0x40 +#define TP_PECI_OPEN 0x20 +#define TP_TSI_OPEN 0x10 +#define TP_EXTERNAL_SENSOR2_OPEN 0x04 +#define TP_EXTERNAL_SENSOR1_OPEN 0x02 + +#define FAN_TYPE_REG 0x94 +#define FAN_TYPE_SHIFT(fan) ((fan - 1) * 2) +#define FAN_TYPE_MASK 0x03 +#define FAN_MODE_REG 0x96 + /* FUNC_PROG_SEL = 0 */ +#define FAN_MODE_SHIFT(fan) ((fan - 1) * 4) +#define FAN_MODE_MASK 0x07 + /* FUNC_PROG_SEL = 1 */ +#define FAN1_ADJ_SEL_SHIFT 0 +#define FAN1_ADJ_SEL_MASK 0x07 +#define FAN_FREQ_SEL_ADD_SHIFT(fan) (fan + 2) +#define FAN_UP_RATE_REG 0x9a +#define FAN_RATE_SHIFT(fan) ((fan - 1) * 2) +#define FAN_RATE_MASK 0x03 +#define FAN_DOWN_RATE_REG 0x9b +#define FAN_DOWN_RATE_DIFF_FROM_UP_SHIFT 7 /* FUNC_PROG_SEL = 1 */ +#define FAN_DIRECT_LOAD_EN_SHIFT 6 /* FUNC_PROG_SEL = 1 */ +#define FAN_FAULT_TIME_REG 0x9f +#define FAN_FUNC_PROG_SEL_SHIFT 7 + +#define FAN_BOUND_TEMP 0xa6 /* 4 temperatures */ +#define FAN_SECTION_SPEED 0xaa /* 5 sections */ +#define FAN_TMP_MAPPING 0xaf +#define FAN_TEMP_SEL_HIGH_SHIFT 7 +#define FAN_PWM_FREQ_SEL_SHIFT 6 +#define FAN_INTERPOLATION_SHIFT 4 +#define FAN_JUMP_UP_SHIFT 3 +#define FAN_JUMP_DOWN_SHIFT 2 +#define FAN_TEMP_SEL_LOW_SHIFT 0 +#define FAN_TEMP_SEL_LOW_MASK 0x03 +#define FAN_BIT_MASK 0x01 + +#define FAN_ADJUST(fan, start) (((fan - 1) * 0x10) + start) + +#define STATUS_INVALID_VALUE -1 +#define STATUS_INVALID_ORDER -2 + +#define FIRST_FAN 1 +#define LAST_FAN 2 +#define MAX_DUTY 100 + +#endif /* SUPERIO_FINTEK_F81803_HWM_H */ diff --git a/src/superio/fintek/f81803a/fan_control.c b/src/superio/fintek/f81803a/fan_control.c new file mode 100644 index 0000000000..17ae9c6a20 --- /dev/null +++ b/src/superio/fintek/f81803a/fan_control.c @@ -0,0 +1,362 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Richard Spiegel + * Copyright (C) 2019 Silverback ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "../common/fan_control.h" +#include "f81803a_hwm.h" + +static const char msg_err_invalid[] = "Error: invalid"; +static const char msg_err_wrong_order[] = "Error: wrong order,"; +static const char msg_err_fan[] = "fan"; +static const char msg_err_temp_source[] = "temperature source"; +static const char msg_err_type[] = "type"; +static const char msg_err_mode[] = "mode"; +static const char msg_err_rate[] = "change rate"; +static const char msg_err_frequency[] = "frequency"; +static const char msg_err_temp_sensor[] = "temperature sensor"; +static const char msg_err_bondary[] = "boundary"; +static const char msg_err_section[] = "section"; +static const char no_msg[] = ""; + +struct cross_ref { + int selection; + const char *message; +}; +static struct cross_ref msg_table[] = { + {HWM_STATUS_INVALID_FAN, msg_err_fan}, + {HWM_STATUS_INVALID_TEMP_SOURCE, msg_err_temp_source}, + {HWM_STATUS_INVALID_TYPE, msg_err_type}, + {HWM_STATUS_INVALID_MODE, msg_err_mode}, + {HWM_STATUS_INVALID_RATE, msg_err_rate}, + {HWM_STATUS_INVALID_FREQUENCY, msg_err_frequency}, + {HWM_STATUS_INVALID_TEMP_SENSOR, msg_err_temp_sensor}, + {0, NULL}, +}; + +static const char *get_msg(int err) +{ + int i = 0; + while (msg_table[i].selection) { + if (msg_table[i].selection == err) + return msg_table[i].message; + i++; + } + return no_msg; +} + +static int message_invalid_1(int err, u8 fan) +{ + if (err == HWM_STATUS_INVALID_FAN) + printk(BIOS_ERR, "%s %s %d!\n", msg_err_invalid, get_msg(err), fan); + else + printk(BIOS_ERR, "%s Fan %d %s!\n", msg_err_invalid, fan, get_msg(err)); + return err; +} + +static int message_invalid_2(int err, u8 fan) +{ + switch (err) { + case HWM_STATUS_INVALID_BOUNDARY_VALUE: + printk(BIOS_ERR, "%s fan %d %s value!\n", msg_err_invalid, fan, + msg_err_bondary); + break; + case HWM_STATUS_INVALID_SECTION_VALUE: + printk(BIOS_ERR, "%s fan %d %s value!\n", msg_err_invalid, fan, + msg_err_section); + break; + case HWM_STATUS_BOUNDARY_WRONG_ORDER: + printk(BIOS_ERR, "%s fan %d %s!\n", msg_err_wrong_order, fan, msg_err_bondary); + break; + case HWM_STATUS_SECTIONS_WRONG_ORDER: + printk(BIOS_ERR, "%s fan %d %s!\n", msg_err_wrong_order, fan, msg_err_section); + break; + default: + break; + } + return err; +} + +static void write_hwm_reg(u16 address, u8 index, u8 value) +{ + u16 index_add, data_add; + index_add = address | 0x0001; /* force odd address */ + data_add = index_add + 1; + outb(index, index_add); + outb(value, data_add); +} + +static u8 read_hwm_reg(u16 address, u8 index) +{ + u16 index_add, data_add; + index_add = address | 0x0001; /* force odd address */ + data_add = index_add + 1; + outb(index, index_add); + return inb(data_add); +} + +static void hwm_reg_modify(u16 address, u8 index, u8 shift, u8 mask, + u8 value) +{ + u8 use_mask = mask << shift; + u8 use_value = (value & mask) << shift; + u8 temp = read_hwm_reg(address, index); + + temp &= ~use_mask; + temp |= use_value; + write_hwm_reg(address, index, temp); +} + +/* + * Registers 0x94,0x95, 0x96 and 0x9b have 2 versions (banks) selected through + * bit 7 of register 0x9f. + */ +static inline void select_hwm_bank(u16 address, u8 value) +{ + hwm_reg_modify(address, FAN_FAULT_TIME_REG, FAN_FUNC_PROG_SEL_SHIFT, + FAN_BIT_MASK, value); +} + +/* + * Boundaries and sections must be presented in the same order as in the HWM + * registers, that is, from highest value to lowest. This procedure checks for + * the correct order. + */ +static int check_value_seq(u8 *values, u8 count) +{ + u8 last_value = CPU_DAMAGE_TEMP; + u8 current_value, i; + for (i = 0; i < count; i++) { + current_value = values[i]; + if (current_value > CPU_DAMAGE_TEMP) + return STATUS_INVALID_VALUE; + if (current_value >= last_value) + return STATUS_INVALID_ORDER; + last_value = current_value; + } + return HWM_STATUS_SUCCESS; +} + +int set_sensor_type(u16 base_address, external_sensor sensor, + temp_sensor_type type) +{ + u8 sensor_status = read_hwm_reg(base_address, TP_DIODE_STATUS); + + printk(BIOS_DEBUG, "%s\n", __func__); + switch (sensor) { + case EXTERNAL_SENSOR1: + if (sensor_status & TP_EXTERNAL_SENSOR1_OPEN) { + printk(BIOS_WARNING, "Sensor 1 disconected!\n"); + return HWM_STATUS_WARNING_SENSOR_DISCONECTED; + } + hwm_reg_modify(base_address, TP_SENSOR_TYPE, + TP_SENSOR1_TYPE_SHIFT, TP_SENSOR_TYPE_MASK, type); + break; + case EXTERNAL_SENSOR2: + if (sensor_status & TP_EXTERNAL_SENSOR2_OPEN) { + printk(BIOS_WARNING, "Sensor 2 disconected!\n"); + return HWM_STATUS_WARNING_SENSOR_DISCONECTED; + } + hwm_reg_modify(base_address, TP_SENSOR_TYPE, + TP_SENSOR2_TYPE_SHIFT, TP_SENSOR_TYPE_MASK, type); + break; + case IGNORE_SENSOR: + break; + default: + return message_invalid_1(HWM_STATUS_INVALID_TEMP_SENSOR, 0); + } + return HWM_STATUS_SUCCESS; +} + +int set_fan_temperature_source(u16 base_address, u8 fan, + fan_temp_source source) +{ + u8 index, high_value, low_value; + + printk(BIOS_DEBUG, "%s\n", __func__); + if ((fan < FIRST_FAN) || (fan > LAST_FAN)) + return message_invalid_1(HWM_STATUS_INVALID_FAN, fan); + index = FAN_ADJUST(fan, FAN_TMP_MAPPING); + high_value = (source >> 2) & FAN_BIT_MASK; + low_value = source & FAN_TEMP_SEL_LOW_MASK; + hwm_reg_modify(base_address, index, FAN_TEMP_SEL_HIGH_SHIFT, + FAN_BIT_MASK, high_value); + hwm_reg_modify(base_address, index, FAN_TEMP_SEL_LOW_SHIFT, + FAN_TEMP_SEL_LOW_MASK, low_value); + /* + * Fan 1 has a weight mechanism for adjusting for next fan speed. Basically the idea is + * to react more aggressively (normally CPU fan) based on how high another temperature + * (system, thermistor near the CPU, anything) is. This would be highly platform + * dependent, and by setting the weight temperature same as the control temperature. + * This code cancels the weight mechanism and make it work with any board. If a board + * wants to use the weight mechanism, OEM should implement it after calling the main + * HWM programming. + */ + if (fan == FIRST_FAN) { + select_hwm_bank(base_address, 1); + hwm_reg_modify(base_address, FAN_MODE_REG, + FAN1_ADJ_SEL_SHIFT, FAN1_ADJ_SEL_MASK, source); + select_hwm_bank(base_address, 0); + } + return HWM_STATUS_SUCCESS; +} + +int set_fan_type_mode(u16 base_address, u8 fan, fan_type type, fan_mode mode) +{ + u8 shift; + + printk(BIOS_DEBUG, "%s\n", __func__); + if ((fan < FIRST_FAN) || (fan > LAST_FAN)) + return message_invalid_1(HWM_STATUS_INVALID_FAN, fan); + select_hwm_bank(base_address, 0); + if (type < FAN_TYPE_RESERVED) { + shift = FAN_TYPE_SHIFT(fan); + hwm_reg_modify(base_address, FAN_TYPE_REG, shift, + FAN_TYPE_MASK, type); + } + if (mode < FAN_MODE_DEFAULT) { + shift = FAN_MODE_SHIFT(fan); + hwm_reg_modify(base_address, FAN_MODE_REG, shift, + FAN_MODE_MASK, mode); + } + return HWM_STATUS_SUCCESS; +} + +int set_pwm_frequency(u16 base_address, u8 fan, fan_pwm_freq frequency) +{ + u8 shift, index, byte; + + printk(BIOS_DEBUG, "%s\n", __func__); + if ((fan < FIRST_FAN) || (fan > LAST_FAN)) + return message_invalid_1(HWM_STATUS_INVALID_FAN, fan); + byte = read_hwm_reg(base_address, FAN_TYPE_REG); + shift = FAN_TYPE_SHIFT(fan); + if (((byte >> shift) & FAN_TYPE_PWM_CHECK) == FAN_TYPE_PWM_CHECK) { + printk(BIOS_WARNING, "Fan %d not programmed as PWM!\n", fan); + return HWM_STATUS_WARNING_FAN_NOT_PWM; + } + select_hwm_bank(base_address, 1); + shift = FAN_FREQ_SEL_ADD_SHIFT(fan); + byte = (frequency >> 1) & FAN_BIT_MASK; + hwm_reg_modify(base_address, FAN_MODE_REG, shift, FAN_BIT_MASK, + byte); + select_hwm_bank(base_address, 0); + index = FAN_ADJUST(fan, FAN_TMP_MAPPING); + byte = frequency & FAN_BIT_MASK; + hwm_reg_modify(base_address, index, FAN_PWM_FREQ_SEL_SHIFT, + FAN_BIT_MASK, byte); + return HWM_STATUS_SUCCESS; +} + +int set_sections(u16 base_address, u8 fan, u8 *boundaries, u8 *sections) +{ + int status, temp; + u8 i, index, value; + + printk(BIOS_DEBUG, "%s\n", __func__); + if ((fan < FIRST_FAN) || (fan > LAST_FAN)) + return message_invalid_1(HWM_STATUS_INVALID_FAN, fan); + status = check_value_seq(boundaries, + FINTEK_BOUNDARIES_SIZE); + if (status != HWM_STATUS_SUCCESS) { + if (status == STATUS_INVALID_VALUE) + return message_invalid_2(HWM_STATUS_INVALID_BOUNDARY_VALUE, fan); + return message_invalid_2(HWM_STATUS_BOUNDARY_WRONG_ORDER, fan); + } + status = check_value_seq(sections, + FINTEK_SECTIONS_SIZE); + if (status != HWM_STATUS_SUCCESS) { + if (status == STATUS_INVALID_VALUE) + return message_invalid_2(HWM_STATUS_INVALID_SECTION_VALUE, fan); + return message_invalid_2(HWM_STATUS_SECTIONS_WRONG_ORDER, fan); + } + index = FAN_ADJUST(fan, FAN_BOUND_TEMP); + for (i = 0; i < FINTEK_BOUNDARIES_SIZE; i++) { + value = boundaries[i]; + write_hwm_reg(base_address, index, value); + index++; + } + index = FAN_ADJUST(fan, FAN_SECTION_SPEED); + for (i = 0; i < FINTEK_SECTIONS_SIZE; i++) { + value = sections[i]; + if (value > 100) + return message_invalid_2(HWM_STATUS_INVALID_SECTION_VALUE, fan); + temp = (255 * value) / 100; + value = (u8) (temp & 0x00ff); + write_hwm_reg(base_address, index, value); + index++; + } + return HWM_STATUS_SUCCESS; +} + +int set_fan_speed_change_rate(u16 base_address, u8 fan, fan_rate_up rate_up, + fan_rate_down rate_down) +{ + u8 shift, index; + + printk(BIOS_DEBUG, "%s\n", __func__); + if ((fan < FIRST_FAN) || (fan > LAST_FAN)) + return message_invalid_1(HWM_STATUS_INVALID_FAN, fan); + + index = FAN_ADJUST(fan, FAN_TMP_MAPPING); + shift = FAN_RATE_SHIFT(fan); + + if (rate_up == FAN_UP_RATE_JUMP) { + hwm_reg_modify(base_address, index, FAN_JUMP_UP_SHIFT, + FAN_BIT_MASK, 1); + } else { + hwm_reg_modify(base_address, index, FAN_JUMP_UP_SHIFT, + FAN_BIT_MASK, 0); + if (rate_up < FAN_UP_RATE_DEFAULT) { + hwm_reg_modify(base_address, FAN_UP_RATE_REG, + shift, FAN_RATE_MASK, rate_up); + } + } + + if (rate_down == FAN_DOWN_RATE_JUMP) { + hwm_reg_modify(base_address, index, FAN_JUMP_DOWN_SHIFT, + FAN_BIT_MASK, 1); + } else { + hwm_reg_modify(base_address, index, FAN_JUMP_UP_SHIFT, + FAN_BIT_MASK, 0); + select_hwm_bank(base_address, 0); + if (rate_down < FAN_DOWN_RATE_DEFAULT) { + hwm_reg_modify(base_address, FAN_DOWN_RATE_REG, + shift, FAN_RATE_MASK, rate_down); + hwm_reg_modify(base_address, FAN_DOWN_RATE_REG, + FAN_DOWN_RATE_DIFF_FROM_UP_SHIFT, + FAN_BIT_MASK, 0); + } + if (rate_down == FAN_DOWN_RATE_SAME_AS_UP) { + hwm_reg_modify(base_address, FAN_DOWN_RATE_REG, + FAN_DOWN_RATE_DIFF_FROM_UP_SHIFT, + FAN_BIT_MASK, 1); + } + } + return HWM_STATUS_SUCCESS; +} + +int set_fan_follow(u16 base_address, u8 fan, fan_follow follow) +{ + u8 index; + + printk(BIOS_DEBUG, "%s\n", __func__); + if ((fan < FIRST_FAN) || (fan > LAST_FAN)) + return message_invalid_1(HWM_STATUS_INVALID_FAN, fan); + index = FAN_ADJUST(fan, FAN_TMP_MAPPING); + hwm_reg_modify(base_address, index, FAN_INTERPOLATION_SHIFT, + FAN_BIT_MASK, follow); + return HWM_STATUS_SUCCESS; +} diff --git a/src/superio/fintek/f81803a/superio.c b/src/superio/fintek/f81803a/superio.c new file mode 100644 index 0000000000..a07b69e97e --- /dev/null +++ b/src/superio/fintek/f81803a/superio.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include "f81803a.h" + +static void f81803a_pme_init(struct device *dev) +{ + pnp_enter_conf_mode(dev); + pnp_write_config(dev, LDN_REG, F81803A_PME); + /* enable ERP function*/ + /* also set PSIN to generate PSOUT*/ + pnp_write_config(dev, PME_ERP_ENABLE_REG, ERP_ENABLE | ERP_PSOUT_EN); + pnp_exit_conf_mode(dev); +} + +static void f81803a_init(struct device *dev) +{ + if (!dev->enabled) + return; + switch (dev->path.pnp.device) { + /* TODO: Might potentially need code for GPIO or WDT. */ + case F81803A_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + case F81803A_PME: + f81803a_pme_init(dev); + break; + } + +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = f81803a_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, F81803A_SP1, PNP_IO0 | PNP_IRQ0, 0x7f8, }, + { &ops, F81803A_SP2, PNP_IO0 | PNP_IRQ0, 0x7f8, }, + { &ops, F81803A_HWM, PNP_IO0 | PNP_IRQ0, 0xff8, }, + { &ops, F81803A_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x07f8, }, + { &ops, F81803A_GPIO, PNP_IO0 | PNP_IRQ0, 0x7f8, }, + { &ops, F81803A_WDT, PNP_IO0, 0x7f8 }, + { &ops, F81803A_PME, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_fintek_f81803a_ops = { + CHIP_NAME("Fintek F81803A Super I/O") + .enable_dev = enable_dev +}; diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc index de4e99cb67..eae0f63fd7 100644 --- a/src/superio/nuvoton/Makefile.inc +++ b/src/superio/nuvoton/Makefile.inc @@ -19,6 +19,7 @@ romstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_PRE_RAM) += common/early_serial.c subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d +subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5539D) += nct5539d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5572D) += nct5572d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += nct6776 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index eaa3c5af64..29418dbf9e 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -65,6 +65,10 @@ void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase) { nuvoton_pnp_enter_conf_state(dev); + if (CONFIG(SUPERIO_NUVOTON_NCT5539D_COM_A)) + /* Route COM A to GPIO8 pin group */ + pnp_write_config(dev, 0x2a, 0x40); + if (CONFIG(SUPERIO_NUVOTON_NCT6776_COM_A)) /* Route COM A to GPIO8 pin group */ pnp_write_config(dev, 0x2a, 0x40); diff --git a/src/superio/nuvoton/nct5539d/Kconfig b/src/superio/nuvoton/nct5539d/Kconfig new file mode 100644 index 0000000000..0dd14022b6 --- /dev/null +++ b/src/superio/nuvoton/nct5539d/Kconfig @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Pavel Sayekat +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_NUVOTON_NCT5539D + bool + select SUPERIO_NUVOTON_COMMON_PRE_RAM + +config SUPERIO_NUVOTON_NCT5539D_COM_A + bool + depends on SUPERIO_NUVOTON_NCT5539D + default n diff --git a/src/superio/nuvoton/nct5539d/Makefile.inc b/src/superio/nuvoton/nct5539d/Makefile.inc new file mode 100644 index 0000000000..6e3fdf25a2 --- /dev/null +++ b/src/superio/nuvoton/nct5539d/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Pavel Sayekat +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5539D) += superio.c diff --git a/src/superio/nuvoton/nct5539d/nct5539d.h b/src/superio/nuvoton/nct5539d/nct5539d.h new file mode 100644 index 0000000000..d4e8d083a9 --- /dev/null +++ b/src/superio/nuvoton/nct5539d/nct5539d.h @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Pavel Sayekat + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_NUVOTON_NCT5539D_H +#define SUPERIO_NUVOTON_NCT5539D_H + +/* Logical Device Numbers (LDN). */ +#define NCT5539D_SP1 0x02 /* UART A */ +#define NCT5539D_KBC 0x05 /* Keyboard Controller */ +#define NCT5539D_CIR 0x06 /* Consumer IR */ +#define NCT5539D_GPIO78 0x07 /* GPIO 7 & 8 */ +#define NCT5539D_WDT1_WDT3_GPIO0 0x08 /* WDT1, WDT3, GPIO 0 & KBC P20 */ +#define NCT5539D_GPIO2345 0x09 /* GPIO 2, 3, 4 & 5 */ +#define NCT5539D_ACPI 0x0A /* ACPI */ +#define NCT5539D_HWM_FPLED 0x0B /* HW Monitor, Front Panel LED */ +#define NCT5539D_WDT2 0x0D /* WDT2 */ +#define NCT5539D_CIRWUP 0x0E /* CIR Wake-Up */ +#define NCT5539D_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open-Drain */ +#define NCT5539D_GPIO_PSO 0x11 /* GPIO, RI PSOUT Wake-Up Status */ +#define NCT5539D_SWEC 0x12 /* SW Error Control */ +#define NCT5539D_FLED 0x15 /* Fading LED */ +#define NCT5539D_DS 0x16 /* Deep Sleep */ + +/* Virtual LDNs */ +#define NCT5539D_WDT1 ((0 << 8) | NCT5539D_WDT1_WDT3_GPIO0) +#define NCT5539D_WDT3 ((4 << 8) | NCT5539D_WDT1_WDT3_GPIO0) +#define NCT5539D_GPIOBASE ((3 << 8) | NCT5539D_WDT1_WDT3_GPIO0) +#define NCT5539D_GPIO0 ((1 << 8) | NCT5539D_WDT1_WDT3_GPIO0) +#define NCT5539D_GPIO2 ((0 << 8) | NCT5539D_GPIO2345) +#define NCT5539D_GPIO3 ((1 << 8) | NCT5539D_GPIO2345) +#define NCT5539D_GPIO4 ((2 << 8) | NCT5539D_GPIO2345) +#define NCT5539D_GPIO5 ((3 << 8) | NCT5539D_GPIO2345) +#define NCT5539D_GPIO7 ((1 << 8) | NCT5539D_GPIO78) +#define NCT5539D_GPIO8 ((2 << 8) | NCT5539D_GPIO78) +#define NCT5539D_DS5 ((0 << 8) | NCT5539D_DS) +#define NCT5539D_DS3 ((1 << 8) | NCT5539D_DS) + +#endif /* SUPERIO_NUVOTON_NCT5539D_H */ diff --git a/src/superio/nuvoton/nct5539d/superio.c b/src/superio/nuvoton/nct5539d/superio.c new file mode 100644 index 0000000000..e38f845042 --- /dev/null +++ b/src/superio/nuvoton/nct5539d/superio.c @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Felix Held + * Copyright (C) 2014 Edward O'Callaghan + * Copyright (C) 2015 Matt DeVillier + * Copyright (C) 2016 Omar Pakker +* Copyright (C) 2019 Pavel Sayekat + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include "nct5539d.h" + + +static void nct5539d_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case NCT5539D_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = nct5539d_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, NCT5539D_SP1, PNP_IO0 | PNP_IRQ0, + 0x0ff8, }, + { NULL, NCT5539D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, + 0x0fff, 0x0fff, }, + { NULL, NCT5539D_CIR, PNP_IO0 | PNP_IRQ0, + 0x0ff8, }, + { NULL, NCT5539D_ACPI}, + { NULL, NCT5539D_HWM_FPLED, PNP_IO0 | PNP_IRQ0, + 0x0ffe, 0x0ffe, }, + { NULL, NCT5539D_WDT2}, + { NULL, NCT5539D_CIRWUP, PNP_IO0 | PNP_IRQ0, + 0x0ff8, }, + { NULL, NCT5539D_GPIO_PP_OD}, + { NULL, NCT5539D_WDT1}, + { NULL, NCT5539D_WDT3}, + { NULL, NCT5539D_GPIOBASE, PNP_IO0, + 0x0ff8, }, + { NULL, NCT5539D_GPIO0}, + { NULL, NCT5539D_GPIO2}, + { NULL, NCT5539D_GPIO3}, + { NULL, NCT5539D_GPIO4}, + { NULL, NCT5539D_GPIO5}, + { NULL, NCT5539D_GPIO7}, + { NULL, NCT5539D_GPIO8}, + { NULL, NCT5539D_GPIO_PSO}, + { NULL, NCT5539D_SWEC}, + { NULL, NCT5539D_FLED}, + { NULL, NCT5539D_DS5}, + { NULL, NCT5539D_DS3}, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_nct5539d_ops = { + CHIP_NAME("NUVOTON NCT5539D Super I/O") + .enable_dev = enable_dev, +}; diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/S3.c index caf817ef33..0897123aa2 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/S3.c +++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/S3.c @@ -225,25 +225,25 @@ SaveDeviceContext ( switch (Device.CommonDeviceHeader->Type) { case DEV_TYPE_PCI_PRE_ESR: SavePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_PCI: Device.PciDevice++; break; case DEV_TYPE_CPCI_PRE_ESR: SaveConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_CPCI: Device.CPciDevice++; break; case DEV_TYPE_MSR_PRE_ESR: SaveMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_MSR: Device.MsrDevice++; break; case DEV_TYPE_CMSR_PRE_ESR: SaveConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_CMSR: Device.CMsrDevice++; break; @@ -256,25 +256,25 @@ SaveDeviceContext ( switch (Device.CommonDeviceHeader->Type) { case DEV_TYPE_PCI: SavePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_PCI_PRE_ESR: Device.PciDevice++; break; case DEV_TYPE_CPCI: SaveConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_CPCI_PRE_ESR: Device.CPciDevice++; break; case DEV_TYPE_MSR: SaveMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_MSR_PRE_ESR: Device.MsrDevice++; break; case DEV_TYPE_CMSR: SaveConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_CMSR_PRE_ESR: Device.CMsrDevice++; break; @@ -679,25 +679,25 @@ RestorePreESRContext ( switch (Device.CommonDeviceHeader->Type) { case DEV_TYPE_PCI_PRE_ESR: RestorePciDevice (StdHeader, Device.PciDevice, CallPoint, OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_PCI: Device.PciDevice++; break; case DEV_TYPE_CPCI_PRE_ESR: RestoreConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_CPCI: Device.CPciDevice++; break; case DEV_TYPE_MSR_PRE_ESR: RestoreMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_MSR: Device.MsrDevice++; break; case DEV_TYPE_CMSR_PRE_ESR: RestoreConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_CMSR: Device.CMsrDevice++; break; @@ -739,25 +739,25 @@ RestorePostESRContext ( switch (Device.CommonDeviceHeader->Type) { case DEV_TYPE_PCI: RestorePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_PCI_PRE_ESR: Device.PciDevice++; break; case DEV_TYPE_CPCI: RestoreConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_CPCI_PRE_ESR: Device.CPciDevice++; break; case DEV_TYPE_MSR: RestoreMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_MSR_PRE_ESR: Device.MsrDevice++; break; case DEV_TYPE_CMSR: RestoreConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_CMSR_PRE_ESR: Device.CMsrDevice++; break; diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/muc.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/muc.c index c76d228382..a6d7bb1aff 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/muc.c +++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Main/muc.c @@ -212,8 +212,7 @@ MemUFillTrainPattern ( break; case TestPatternJD256B: k >>= 1; - // break is not being used here because TestPatternJD256B also need - // to run TestPatternJD256A sequence. + // fall through - TestPatternJD256B also need to run TestPatternJD256A sequence case TestPatternJD256A: k >>= 3; ASSERT (k < sizeof (PatternJD_256)); @@ -221,8 +220,7 @@ MemUFillTrainPattern ( break; case TestPatternJD1B: k >>= 1; - // break is not being used here because TestPatternJD1B also need - // to run TestPatternJD1A sequence. + // fall through - TestPatternJD1B also need to run TestPatternJD1A sequence case TestPatternJD1A: k >>= 3; i = (UINT8) (k >> 3); diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnphy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnphy.c index 08b3a66625..d84e4172ff 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnphy.c +++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnphy.c @@ -691,8 +691,7 @@ MemNcmnGetSetTrainDlyNb ( } else if (Rank) { Index += 0x60; } - // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need - // to run AccessPhRecDly sequence. + // fall through - AccessRdDqsDly and AccessWrDatDly also need to run AccessPhRecDly sequence case AccessPhRecDly: Index += (Byte / 4); Offset = 8 * (Byte % 4); @@ -818,8 +817,7 @@ MemNcmnGetSetTrainDlyClientNb ( case AccessRdDqsDly: case AccessWrDatDly: Index += (Dimm * 0x100); - // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need - // to run AccessPhRecDly sequence. + // fall through - AccessRdDqsDly and AccessWrDatDly also need to run AccessPhRecDly sequence case AccessPhRecDly: Index += (Byte / 4); Offset = 8 * (Byte % 4); @@ -967,8 +965,7 @@ MemNcmnGetSetTrainDlyUnb ( } else if (Rank) { Index += 0x60; } - // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need - // to run AccessPhRecDly sequence. + // fall through - AccessRdDqsDly and AccessWrDatDly also need to run AccessPhRecDly sequence case AccessPhRecDly: Index += (Byte / 4); Offset = 8 * (Byte % 4); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/S3.c index a1393bebe5..6d12752b26 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/S3.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/S3.c @@ -227,25 +227,25 @@ SaveDeviceContext ( switch (Device.CommonDeviceHeader->Type) { case DEV_TYPE_PCI_PRE_ESR: SavePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_PCI: Device.PciDevice++; break; case DEV_TYPE_CPCI_PRE_ESR: SaveConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_CPCI: Device.CPciDevice++; break; case DEV_TYPE_MSR_PRE_ESR: SaveMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_MSR: Device.MsrDevice++; break; case DEV_TYPE_CMSR_PRE_ESR: SaveConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_CMSR: Device.CMsrDevice++; break; @@ -258,25 +258,25 @@ SaveDeviceContext ( switch (Device.CommonDeviceHeader->Type) { case DEV_TYPE_PCI: SavePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_PCI_PRE_ESR: Device.PciDevice++; break; case DEV_TYPE_CPCI: SaveConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_CPCI_PRE_ESR: Device.CPciDevice++; break; case DEV_TYPE_MSR: SaveMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_MSR_PRE_ESR: Device.MsrDevice++; break; case DEV_TYPE_CMSR: SaveConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_CMSR_PRE_ESR: Device.CMsrDevice++; break; @@ -673,25 +673,25 @@ RestorePreESRContext ( switch (Device.CommonDeviceHeader->Type) { case DEV_TYPE_PCI_PRE_ESR: RestorePciDevice (StdHeader, Device.PciDevice, CallPoint, OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_PCI: Device.PciDevice++; break; case DEV_TYPE_CPCI_PRE_ESR: RestoreConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_CPCI: Device.CPciDevice++; break; case DEV_TYPE_MSR_PRE_ESR: RestoreMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_MSR: Device.MsrDevice++; break; case DEV_TYPE_CMSR_PRE_ESR: RestoreConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_CMSR: Device.CMsrDevice++; break; @@ -733,25 +733,25 @@ RestorePostESRContext ( switch (Device.CommonDeviceHeader->Type) { case DEV_TYPE_PCI: RestorePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_PCI_PRE_ESR: Device.PciDevice++; break; case DEV_TYPE_CPCI: RestoreConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_CPCI_PRE_ESR: Device.CPciDevice++; break; case DEV_TYPE_MSR: RestoreMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_MSR_PRE_ESR: Device.MsrDevice++; break; case DEV_TYPE_CMSR: RestoreConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_CMSR_PRE_ESR: Device.CMsrDevice++; break; diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c index 88b85df7ac..da0eb95cf3 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c @@ -213,8 +213,7 @@ MemUFillTrainPattern ( break; case TestPatternJD256B: k >>= 1; - // break is not being used here because TestPatternJD256B also need - // to run TestPatternJD256A sequence. + // fall through - TestPatternJD256B also need to run TestPatternJD256A sequence case TestPatternJD256A: k >>= 3; ASSERT (k < sizeof (PatternJD_256)); @@ -222,8 +221,7 @@ MemUFillTrainPattern ( break; case TestPatternJD1B: k >>= 1; - // break is not being used here because TestPatternJD1B also need - // to run TestPatternJD1A sequence. + // fall through - TestPatternJD1B also need to run TestPatternJD1A sequence case TestPatternJD1A: k >>= 3; i = (UINT8) (k >> 3); diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnphy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnphy.c index 4045289a18..a312687cf8 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnphy.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnphy.c @@ -695,8 +695,7 @@ MemNcmnGetSetTrainDlyNb ( } else if (Rank) { Index += 0x60; } - // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need - // to run AccessPhRecDly sequence. + // fall through - AccessRdDqsDly and AccessWrDatDly also need to run AccessPhRecDly sequence case AccessPhRecDly: Index += (Byte / 4); Offset = 8 * (Byte % 4); @@ -822,8 +821,7 @@ MemNcmnGetSetTrainDlyClientNb ( case AccessRdDqsDly: case AccessWrDatDly: Index += (Dimm * 0x100); - // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need - // to run AccessPhRecDly sequence. + // fall through - AccessRdDqsDly and AccessWrDatDly also need to run AccessPhRecDly sequence case AccessPhRecDly: Index += (Byte / 4); Offset = 8 * (Byte % 4); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c index 95579cbef4..9152beedf1 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c @@ -224,25 +224,25 @@ SaveDeviceContext ( switch (Device.CommonDeviceHeader->Type) { case DEV_TYPE_PCI_PRE_ESR: SavePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_PCI: Device.PciDevice++; break; case DEV_TYPE_CPCI_PRE_ESR: SaveConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_CPCI: Device.CPciDevice++; break; case DEV_TYPE_MSR_PRE_ESR: SaveMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_MSR: Device.MsrDevice++; break; case DEV_TYPE_CMSR_PRE_ESR: SaveConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_CMSR: Device.CMsrDevice++; break; @@ -255,25 +255,25 @@ SaveDeviceContext ( switch (Device.CommonDeviceHeader->Type) { case DEV_TYPE_PCI: SavePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_PCI_PRE_ESR: Device.PciDevice++; break; case DEV_TYPE_CPCI: SaveConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_CPCI_PRE_ESR: Device.CPciDevice++; break; case DEV_TYPE_MSR: SaveMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_MSR_PRE_ESR: Device.MsrDevice++; break; case DEV_TYPE_CMSR: SaveConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_CMSR_PRE_ESR: Device.CMsrDevice++; break; @@ -678,25 +678,25 @@ RestorePreESRContext ( switch (Device.CommonDeviceHeader->Type) { case DEV_TYPE_PCI_PRE_ESR: RestorePciDevice (StdHeader, Device.PciDevice, CallPoint, OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_PCI: Device.PciDevice++; break; case DEV_TYPE_CPCI_PRE_ESR: RestoreConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_CPCI: Device.CPciDevice++; break; case DEV_TYPE_MSR_PRE_ESR: RestoreMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_MSR: Device.MsrDevice++; break; case DEV_TYPE_CMSR_PRE_ESR: RestoreConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_CMSR: Device.CMsrDevice++; break; @@ -738,25 +738,25 @@ RestorePostESRContext ( switch (Device.CommonDeviceHeader->Type) { case DEV_TYPE_PCI: RestorePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_PCI_PRE_ESR: Device.PciDevice++; break; case DEV_TYPE_CPCI: RestoreConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_CPCI_PRE_ESR: Device.CPciDevice++; break; case DEV_TYPE_MSR: RestoreMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_MSR_PRE_ESR: Device.MsrDevice++; break; case DEV_TYPE_CMSR: RestoreConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_CMSR_PRE_ESR: Device.CMsrDevice++; break; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.c index 322339d4a3..5c3e312158 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.c @@ -372,9 +372,7 @@ AmdIdsDebugPrintWorker ( case 'X': Flags |= PREFIX_ZERO; Width = sizeof (UINT64) * 2; - // - // break skipped on purpose - // + // fall through case 'x': if ((Flags & LONG_TYPE) == LONG_TYPE) { Value = VA_ARG (Marker, UINT64); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/muc.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/muc.c index 41ba55c652..a9aa5ca6f3 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/muc.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/muc.c @@ -211,8 +211,7 @@ MemUFillTrainPattern ( break; case TestPatternJD256B: k >>= 1; - // break is not being used here because TestPatternJD256B also need - // to run TestPatternJD256A sequence. + // fall through - TestPatternJD256B also need to run TestPatternJD256A sequence case TestPatternJD256A: k >>= 3; ASSERT (k < sizeof (PatternJD_256)); @@ -220,8 +219,7 @@ MemUFillTrainPattern ( break; case TestPatternJD1B: k >>= 1; - // break is not being used here because TestPatternJD1B also need - // to run TestPatternJD1A sequence. + // fall through - TestPatternJD1B also need to run TestPatternJD1A sequence case TestPatternJD1A: k >>= 3; i = (UINT8) (k >> 3); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnphy.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnphy.c index 060269e129..076f443876 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnphy.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnphy.c @@ -693,8 +693,7 @@ MemNcmnGetSetTrainDlyNb ( } else if (Rank) { Index += 0x60; } - // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need - // to run AccessPhRecDly sequence. + // fall through - AccessRdDqsDly and AccessWrDatDly also need to run AccessPhRecDly sequence case AccessPhRecDly: Index += (Byte / 4); Offset = 8 * (Byte % 4); @@ -820,8 +819,7 @@ MemNcmnGetSetTrainDlyClientNb ( case AccessRdDqsDly: case AccessWrDatDly: Index += (Dimm * 0x100); - // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need - // to run AccessPhRecDly sequence. + // fall through - AccessRdDqsDly and AccessWrDatDly also need to run AccessPhRecDly sequence case AccessPhRecDly: Index += (Byte / 4); Offset = 8 * (Byte % 4); @@ -975,8 +973,7 @@ MemNcmnGetSetTrainDlyUnb ( } else if (Rank) { Index += 0x60; } - // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need - // to run AccessPhRecDly sequence. + // fall through - AccessRdDqsDly and AccessWrDatDly also need to run AccessPhRecDly sequence case AccessPhRecDly: Index += (Byte / 4); Offset = 8 * (Byte % 4); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.c index ed94e79f78..ccc7343d1b 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.c @@ -242,9 +242,11 @@ F16KbSetDownCoreRegister ( case CORE_LEVEL_COMPUTE_UNIT_THREE: TempVar32_a = TempVar32_a << 1; CoresPerComputeUnit++; + // fall through case CORE_LEVEL_COMPUTE_UNIT_TWO: TempVar32_a = TempVar32_a << 1; CoresPerComputeUnit++; + // fall through case CORE_LEVEL_COMPUTE_UNIT: TempVar32_a = (TempVar32_a << 1) - 1; TempVar32_a = FOUR_CORE_COMPUTE_UNIT_BITMAP & (~TempVar32_a); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c index 4b6128e245..42aebb67d1 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c @@ -224,25 +224,25 @@ SaveDeviceContext ( switch (Device.CommonDeviceHeader->Type) { case DEV_TYPE_PCI_PRE_ESR: SavePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_PCI: Device.PciDevice++; break; case DEV_TYPE_CPCI_PRE_ESR: SaveConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_CPCI: Device.CPciDevice++; break; case DEV_TYPE_MSR_PRE_ESR: SaveMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_MSR: Device.MsrDevice++; break; case DEV_TYPE_CMSR_PRE_ESR: SaveConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_CMSR: Device.CMsrDevice++; break; @@ -255,25 +255,25 @@ SaveDeviceContext ( switch (Device.CommonDeviceHeader->Type) { case DEV_TYPE_PCI: SavePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_PCI_PRE_ESR: Device.PciDevice++; break; case DEV_TYPE_CPCI: SaveConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_CPCI_PRE_ESR: Device.CPciDevice++; break; case DEV_TYPE_MSR: SaveMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_MSR_PRE_ESR: Device.MsrDevice++; break; case DEV_TYPE_CMSR: SaveConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMask); - // Fall through to advance the pointer after saving context + // fall through - advance the pointer after saving context case DEV_TYPE_CMSR_PRE_ESR: Device.CMsrDevice++; break; @@ -678,25 +678,25 @@ RestorePreESRContext ( switch (Device.CommonDeviceHeader->Type) { case DEV_TYPE_PCI_PRE_ESR: RestorePciDevice (StdHeader, Device.PciDevice, CallPoint, OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_PCI: Device.PciDevice++; break; case DEV_TYPE_CPCI_PRE_ESR: RestoreConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_CPCI: Device.CPciDevice++; break; case DEV_TYPE_MSR_PRE_ESR: RestoreMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_MSR: Device.MsrDevice++; break; case DEV_TYPE_CMSR_PRE_ESR: RestoreConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_CMSR: Device.CMsrDevice++; break; @@ -738,25 +738,25 @@ RestorePostESRContext ( switch (Device.CommonDeviceHeader->Type) { case DEV_TYPE_PCI: RestorePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_PCI_PRE_ESR: Device.PciDevice++; break; case DEV_TYPE_CPCI: RestoreConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_CPCI_PRE_ESR: Device.CPciDevice++; break; case DEV_TYPE_MSR: RestoreMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_MSR_PRE_ESR: Device.MsrDevice++; break; case DEV_TYPE_CMSR: RestoreConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMaskPtr); - // Fall through to advance the pointer after restoring context + // fall through - advance the pointer after restoring context case DEV_TYPE_CMSR_PRE_ESR: Device.CMsrDevice++; break; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebugPrint.c b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebugPrint.c index 4163d828de..c3e4ade14b 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebugPrint.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebugPrint.c @@ -375,9 +375,7 @@ AmdIdsDebugPrintWorker ( case 'X': Flags |= PREFIX_ZERO; Width = sizeof (UINT64) * 2; - // - // break skipped on purpose - // + // fall through case 'x': if ((Flags & LONG_TYPE) == LONG_TYPE) { Value = VA_ARG (Marker, UINT64); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/muc.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/muc.c index 8d8177325e..980cd33666 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/muc.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/muc.c @@ -211,8 +211,7 @@ MemUFillTrainPattern ( break; case TestPatternJD256B: k >>= 1; - // break is not being used here because TestPatternJD256B also need - // to run TestPatternJD256A sequence. + // fall through - TestPatternJD256B also need to run TestPatternJD256A sequence case TestPatternJD256A: k >>= 3; ASSERT (k < sizeof (PatternJD_256)); @@ -220,8 +219,7 @@ MemUFillTrainPattern ( break; case TestPatternJD1B: k >>= 1; - // break is not being used here because TestPatternJD1B also need - // to run TestPatternJD1A sequence. + // fall through - TestPatternJD1B also need to run TestPatternJD1A sequence case TestPatternJD1A: k >>= 3; i = (UINT8) (k >> 3); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c index 356d4e3918..c20d5a2fd0 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c @@ -487,8 +487,7 @@ MemNcmnGetSetTrainDlyUnb ( } else if (Rank) { Index += 0x60; } - // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need - // to run AccessPhRecDly sequence. + // fall through - AccessRdDqsDly and AccessWrDatDly also need to run AccessPhRecDly sequence case AccessPhRecDly: Index += (Byte / 4); Offset = 8 * (Byte % 4); diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index 790955a1d0..fef7dff342 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -28,7 +28,7 @@ # #***************************************************************************** -ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +ifeq ($(CONFIG_SOC_AMD_MERLINFALCON)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) # AGESA V5 Files AGESA_ROOT = $(call strip_quotes,$(CONFIG_AGESA_BINARY_PI_VENDORCODE_PATH)) diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index f463b7d2e9..08e7cc6697 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -26,12 +26,13 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 || SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 +if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 || SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON config AGESA_BINARY_PI_VENDORCODE_PATH string "AGESA PI directory path" default "src/vendorcode/amd/pi/00630F01" if CPU_AMD_PI_00630F01 default "src/vendorcode/amd/pi/00730F01" if CPU_AMD_PI_00730F01 + default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_MERLINFALCON default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_STONEYRIDGE_FP4 default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_STONEYRIDGE_FT4 default "src/vendorcode/amd/pi/00660F01" if CPU_AMD_PI_00660F01 @@ -43,6 +44,8 @@ config AGESA_BINARY_PI_FILE string "AGESA PI binary file name" default "3rdparty/blobs/pi/amd/00630F01/FP3/AGESA.bin" if CPU_AMD_PI_00630F01 default "3rdparty/blobs/pi/amd/00730F01/FT3b/AGESA.bin" if CPU_AMD_PI_00730F01 + default "3rdparty/blobs/pi/amd/merlinfalcon/FP4/AGESA_CZ_FP4.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES + default "3rdparty/blobs/pi/amd/00670F00/FP4/AGESA.bin" if SOC_AMD_MERLINFALCON && !HAVE_MERLINFALCON_BINARIES default "3rdparty/blobs/pi/amd/00670F00/FP4/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4 default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4 default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01 diff --git a/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test-addrbus.c b/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test-addrbus.c index 834ade4c40..afa1ed28af 100644 --- a/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test-addrbus.c +++ b/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test-addrbus.c @@ -60,7 +60,7 @@ int __bdk_dram_test_mem_address_bus(uint64_t area, uint64_t max_address, int bur /* Clear our work area. Checking for aliases later could get false positives if it matched stale data */ - void *ptr = (area) ? bdk_phys_to_ptr(area) : NULL; + void *ptr = bdk_phys_to_ptr(area); bdk_zero_memory(ptr, max_address - area); __bdk_dram_flush_to_mem_range(area, max_address); diff --git a/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test.c b/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test.c index 5e6e4bcf11..9c78667116 100644 --- a/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test.c +++ b/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test.c @@ -101,9 +101,7 @@ static uint64_t dram_test_thread_size; void __bdk_dram_flush_to_mem(uint64_t address) { BDK_MB; - /* The DRAM code doesn't use the normal bdk_phys_to_ptr() because of the - NULL check in it. This greatly slows down the memory tests */ - char *ptr = (void*)address; + char *ptr = bdk_phys_to_ptr(address); BDK_CACHE_WBI_L2(ptr); } @@ -116,10 +114,8 @@ void __bdk_dram_flush_to_mem(uint64_t address) */ void __bdk_dram_flush_to_mem_range(uint64_t area, uint64_t max_address) { - /* The DRAM code doesn't use the normal bdk_phys_to_ptr() because of the - NULL check in it. This greatly slows down the memory tests */ - char *ptr = (void*)area; - char *end = (void*)max_address; + char *ptr = bdk_phys_to_ptr(area); + char *end = bdk_phys_to_ptr(max_address); BDK_MB; while (ptr < end) { diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-l2c.c b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-l2c.c index 6c163da2d4..aa7d6582a8 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-l2c.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-l2c.c @@ -141,7 +141,7 @@ int bdk_l2c_unlock_mem_region(bdk_node_t node, uint64_t start, uint64_t len) len += start & BDK_CACHE_LINE_MASK; start &= ~BDK_CACHE_LINE_MASK; len = (len + BDK_CACHE_LINE_MASK) & ~BDK_CACHE_LINE_MASK; - void *ptr = (start) ? bdk_phys_to_ptr(start) : NULL; + void *ptr = bdk_phys_to_ptr(start); while (len > 0) { diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c index f7d631fb5b..b9552d4052 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-qlm.c @@ -362,9 +362,12 @@ int bdk_qlm_eye_display(bdk_node_t node, int qlm, int qlm_lane, int format, cons bdk_error("Failed to allocate space for eye\n"); return -1; } - if (bdk_qlm_eye_capture(node, qlm, qlm_lane, eye_data)) - return -1; + if (bdk_qlm_eye_capture(node, qlm, qlm_lane, eye_data)) { + free(eye_data); + return -1; + } eye = eye_data; + need_free = 1; } /* Calculate the max eye width */ diff --git a/src/vendorcode/cavium/bdk/libdram/dram-spd.c b/src/vendorcode/cavium/bdk/libdram/dram-spd.c index 84df69a923..894a0604c4 100644 --- a/src/vendorcode/cavium/bdk/libdram/dram-spd.c +++ b/src/vendorcode/cavium/bdk/libdram/dram-spd.c @@ -424,7 +424,7 @@ void report_ddr3_dimm(bdk_node_t node, const dimm_config_t *dimm_config, int dram_width, int dimm_size_mb) { int spd_voltage; - const char *volt_str; + const char *volt_str = "unknown voltage"; spd_voltage = read_spd(node, dimm_config, DDR3_SPD_NOMINAL_VOLTAGE); if ((spd_voltage == 0) || (spd_voltage & 3)) @@ -464,7 +464,7 @@ void report_ddr4_dimm(bdk_node_t node, const dimm_config_t *dimm_config, int dram_width, int dimm_size_mb) { int spd_voltage; - const char *volt_str; + const char *volt_str = "unknown voltage"; spd_voltage = read_spd(node, dimm_config, DDR4_SPD_MODULE_NOMINAL_VOLTAGE); if ((spd_voltage == 0x01) || (spd_voltage & 0x02)) diff --git a/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c b/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c index 385aceec50..291fe85567 100644 --- a/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c +++ b/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c @@ -655,7 +655,7 @@ auto_set_dll_offset(bdk_node_t node, int dll_offset_mode, // run the test(s) // only 1 call should be enough, let the bursts, etc, control the load... - tot_errors = run_dram_tuning_threads(node, num_lmcs, bytemask); + run_dram_tuning_threads(node, num_lmcs, bytemask); for (lmc = 0; lmc < num_lmcs; lmc++) { // record stop cycle CSRs here for utilization measure diff --git a/src/vendorcode/cavium/bdk/libdram/lib_octeon_shared.c b/src/vendorcode/cavium/bdk/libdram/lib_octeon_shared.c index 7ee91c27c3..cb090f7da5 100644 --- a/src/vendorcode/cavium/bdk/libdram/lib_octeon_shared.c +++ b/src/vendorcode/cavium/bdk/libdram/lib_octeon_shared.c @@ -1141,6 +1141,11 @@ int initialize_ddr_clock(bdk_node_t node, override_pll_settings = 1; } + if (best_en_idx >= ARRAY_SIZE(_en)) { + error_print("ERROR: best_en_idx %u exceeds _en array size\n", best_en_idx); + return -1; + } + if (override_pll_settings) { best_pll_MHz = ddr_ref_hertz * (best_clkf+1) / (best_clkr+1) / 1000000; best_calculated_ddr_hertz = ddr_ref_hertz * (best_clkf + 1) / ((best_clkr + 1) * (_en[best_en_idx])); diff --git a/src/vendorcode/cavium/bdk/libdram/libdram.c b/src/vendorcode/cavium/bdk/libdram/libdram.c index 214aa05b24..740de8498f 100644 --- a/src/vendorcode/cavium/bdk/libdram/libdram.c +++ b/src/vendorcode/cavium/bdk/libdram/libdram.c @@ -79,10 +79,7 @@ static void bdk_dram_clear_mem(bdk_node_t node) write to the cache line isn't good enough because partial LMC writes may be enabled */ ddr_print("N%d: Rewriting DRAM: start 0 length 0x%llx\n", node, skip); - volatile uint64_t *ptr = bdk_phys_to_ptr(bdk_numa_get_address(node, 8)); - /* The above pointer got address 8 to avoid NULL pointer checking - in bdk_phys_to_ptr(). Correct it here */ - ptr--; + volatile uint64_t *ptr = bdk_phys_to_ptr(bdk_numa_get_address(node, 0)); uint64_t *end = bdk_phys_to_ptr(bdk_numa_get_address(node, skip)); while (ptr < end) { diff --git a/src/vendorcode/cavium/include/bdk/libbdk-dram/bdk-dram-test.h b/src/vendorcode/cavium/include/bdk/libbdk-dram/bdk-dram-test.h index 60f07fa0c5..168ef03dcd 100644 --- a/src/vendorcode/cavium/include/bdk/libbdk-dram/bdk-dram-test.h +++ b/src/vendorcode/cavium/include/bdk/libbdk-dram/bdk-dram-test.h @@ -161,17 +161,13 @@ extern int __bdk_dram_retry_failure2(int burst, uint64_t address1, uint64_t dat static inline void __bdk_dram_write64(uint64_t address, uint64_t data) { - /* The DRAM code doesn't use the normal bdk_phys_to_ptr() because of the - NULL check in it. This greatly slows down the memory tests */ - volatile uint64_t *ptr = (void*)address; + volatile uint64_t *ptr = bdk_phys_to_ptr(address); *ptr = data; } static inline uint64_t __bdk_dram_read64(uint64_t address) { - /* The DRAM code doesn't use the normal bdk_phys_to_ptr() because of the - NULL check in it. This greatly slows down the memory tests */ - volatile uint64_t *ptr = (void*)address; + volatile uint64_t *ptr = bdk_phys_to_ptr(address); return *ptr; } diff --git a/src/vendorcode/eltan/security/Makefile.inc b/src/vendorcode/eltan/security/Makefile.inc index 26b324ba58..16f17fddd7 100644 --- a/src/vendorcode/eltan/security/Makefile.inc +++ b/src/vendorcode/eltan/security/Makefile.inc @@ -1,6 +1,6 @@ ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Eltan B.V. +## Copyright (C) 2018-2019 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -16,12 +16,9 @@ subdirs-y += lib subdirs-y += verified_boot subdirs-y += mboot -ifeq ($(CONFIG_MBOOT), y) +ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBOOT)),) CPPFLAGS_common += -I$(src)/vendorcode/eltan/security/mboot CPPFLAGS_common += -I$(src)/vendorcode/eltan/security/include -endif - -ifeq ($(CONFIG_VERIFIED_BOOT), y) CPPFLAGS_common += -I$(src)/vendorcode/eltan/security/verified_boot endif diff --git a/util/abuild/abuild b/util/abuild/abuild index abfedba614..ef4e46b8ed 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -462,10 +462,26 @@ function build_config return fi + local required_arches + required_arches=$(grep -E "^CONFIG_ARCH_(BOOTBLOCK|R.MSTAGE|VERSTAGE)" "$TARGET/${BUILD_NAME}/config.build" | \ sed "s,^CONFIG_ARCH_[^_]*_\([^=]*\)=.*$,\1," |sort -u |tr 'A-Z\n\r' 'a-z ') - # shellcheck disable=SC2016,SC2059 - missing_arches=$(printf 'include .xcompile\nall: ; @echo $(foreach arch,'"$required_arches"',$(if $(filter $(arch),$(SUBARCH_SUPPORTED)),,$(arch)))' | $MAKE --no-print-directory -f -) + + missing_arches="$($MAKE --no-print-directory -f - \ + REQUIRED_ARCHES="$required_arches" <<'EOF' +include .xcompile +.PHONY: missing_arches +missing_arches: + $(if $(XCOMPILE_COMPLETE),,$(error .xcompile is invalid.)) + @echo $(foreach arch,$(REQUIRED_ARCHES),$(if $(filter $(arch),$(SUBARCH_SUPPORTED)),,$(arch))) +EOF +)" + # shellcheck disable=SC2181 + if [[ $? -ne 0 ]]; then + echo "Calculating missing_arches failed" >&2 + exit 1 + fi + if [ -n "$missing_arches" ]; then printf "skipping %s because we're missing compilers for (%s)\n" "$BUILD_NAME" "$missing_arches" return @@ -625,7 +641,7 @@ getoptbrand="$(getopt -V)" # shellcheck disable=SC2086 if [ "${getoptbrand:0:6}" == "getopt" ]; then # Detected GNU getopt that supports long options. - args=$(getopt -l version,verbose,quiet,help,all,target:,board-variant:,payloads:,cpus:,silent,junit,config,loglevel:,remove,prefix:,update,scan-build,ccache,blobs,clang,any-toolchain,clean,outdir:,chromeos,xmlfile:,kconfig:,dir:,root:,recursive,checksum:,timeless,exitcode -o Vvqhat:b:p:c:sJCl:rP:uyBLAzo:xX:K:d:R:Ie -- "$@") || exit 1 + args=$(getopt -l version,verbose,quiet,help,all,target:,board-variant:,payloads:,cpus:,silent,junit,config,loglevel:,remove,prefix:,update,scan-build,ccache,blobs,clang,any-toolchain,clean,outdir:,chromeos,xmlfile:,kconfig:,dir:,root:,recursive,checksum:,timeless,exitcode,asserts -o Vvqhat:b:p:c:sJCl:rP:uyBLAzo:xX:K:d:R:Ie -- "$@") || exit 1 eval set -- $args retval=$? else @@ -677,6 +693,9 @@ while true ; do SCANBUILD_ARGS=${SCANBUILD_ARGS:-'-k'} configoptions="${configoptions}CONFIG_FATAL_ASSERTS=y\n" ;; + --asserts) shift + configoptions="${configoptions}CONFIG_FATAL_ASSERTS=y\n" + ;; -y|--ccache) shift customizing="${customizing}, ccache" configoptions="${configoptions}CONFIG_CCACHE=y\n" @@ -743,13 +762,18 @@ if [ -z "$TARGET" ] || [ "$TARGET" = "/" ]; then exit 1 fi +if ! mkdir -p "$TARGET"; then + echo "Unable to create build directory" + exit 1 +fi + customizing=$(echo "$customizing" | cut -c3-) if [ "$customizing" = "" ]; then customizing="default configuration" fi -FAILED_BOARDS="${TARGET}/failed_boards" -PASSED_BOARDS="${TARGET}/passing_boards" +FAILED_BOARDS="$(realpath ${TARGET}/failed_boards)" +PASSED_BOARDS="$(realpath ${TARGET}/passing_boards)" if [ "$recursive" = "false" ]; then rm -f "$FAILED_BOARDS" "$PASSED_BOARDS" diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 1ecb7aaaab..4c5b2163d4 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -148,17 +148,15 @@ static uint32_t fletcher32(const void *data, int length) c0 = 0xFFFF; c1 = 0xFFFF; - for (index = 0; index < length; index++) { - /* - * Ignore the contents of the checksum field. - */ + while (length) { + index = length >= 359 ? 359 : length; + length -= index; + do { c0 += *(pptr++); c1 += c0; - if ((index % 360) == 0) { - /* Sums[0,1] mod 64K + overflow */ - c0 = (c0 & 0xFFFF) + (c0 >> 16); - c1 = (c1 & 0xFFFF) + (c1 >> 16); - } + } while (--index); + c0 = (c0 & 0xFFFF) + (c0 >> 16); + c1 = (c1 & 0xFFFF) + (c1 >> 16); } /* Sums[0,1] mod 64K + overflow */ diff --git a/util/arm_boot_tools/mksunxiboot/description.md b/util/arm_boot_tools/mksunxiboot/description.md deleted file mode 100644 index cd90b75325..0000000000 --- a/util/arm_boot_tools/mksunxiboot/description.md +++ /dev/null @@ -1 +0,0 @@ -A simple tool to generate bootable image for sunxi platform. `C` diff --git a/util/arm_boot_tools/mksunxiboot/mksunxiboot.c b/util/arm_boot_tools/mksunxiboot/mksunxiboot.c deleted file mode 100644 index 493f476731..0000000000 --- a/util/arm_boot_tools/mksunxiboot/mksunxiboot.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * A simple tool to generate bootable image for sunxi platform. - * - * Copyright (C) 2007-2011 Allwinner Technology Co., Ltd. - * Tom Cubie - * Copyright (C) 2014 Alexandru Gagniuc - * Subject to the GNU GPL v2, or (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* boot head definition from sun4i boot code */ -struct boot_file_head { - uint32_t jump_instruction; /* one intruction jumping to real code */ - uint8_t magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style str */ - uint32_t check_sum; /* generated by PC */ - uint32_t length; /* generated by PC */ - /* We use a simplified header, only filling in what is needed by the - * boot ROM. To be compatible with Allwinner tools the larger header - * below should be used, followed by a custom header if desired. */ - uint8_t pad[12]; /* align to 32 bytes */ -}; - -static const char *BOOT0_MAGIC = "eGON.BT0"; -static const uint32_t STAMP_VALUE = 0x5F0A6C39; -static const int HEADER_SIZE = 32; -/* Checksum at most 24 KiB */ -#define SRAM_LOAD_MAX_SIZE ((24 << 10) - sizeof(struct boot_file_head)) -static const int BLOCK_SIZE = 512; - -inline static uint32_t le32_to_h(const void *src) -{ - const uint8_t *b = src; - return ((b[3] << 24) | (b[2] << 16) | (b[1] << 8) | (b[0] << 0)); -} - -inline static void h_to_le32(uint32_t val32, void *dest) -{ - uint8_t *b = dest; - b[0] = (val32 >> 0) & 0xff; - b[1] = (val32 >> 8) & 0xff; - b[2] = (val32 >> 16) & 0xff; - b[3] = (val32 >> 24) & 0xff; -}; - -static void serialize_header(void *dest, const struct boot_file_head *hdr) -{ - /* Unused fields are zero */ - memset(dest, 0, HEADER_SIZE); - - h_to_le32(hdr->jump_instruction, dest + 0); - memcpy(dest + 4, BOOT0_MAGIC, 8); - h_to_le32(hdr->check_sum, dest + 12); - h_to_le32(hdr->length, dest + 16); -} - -/* Check sum function from sun4i boot code */ -static int fill_check_sum(struct boot_file_head *hdr, const void *boot_code) -{ - size_t i; - uint8_t raw_hdr[HEADER_SIZE]; - uint32_t chksum; - - if ((hdr->length & 0x3) != 0) { - fprintf(stderr, "BUG! Load size is not 4-byte aligned\n"); - return EXIT_FAILURE; - } - - /* Fill in checksum seed */ - hdr->check_sum = STAMP_VALUE; - - chksum = 0; - /* Checksum the header */ - serialize_header(raw_hdr, hdr); - for (i = 0; i < HEADER_SIZE; i += 4) - chksum += le32_to_h(raw_hdr + i); - - /* Checksum the boot code */ - for (i = 0; i < hdr->length - HEADER_SIZE; i += 4) - chksum += le32_to_h(boot_code + i); - - /* write back check sum */ - hdr->check_sum = chksum; - - return EXIT_SUCCESS; -} - -static uint32_t align(uint32_t size, uint32_t alignment) -{ - return ((size + alignment - 1) / alignment) * alignment; -} - -static void fill_header(struct boot_file_head *hdr, size_t load_size) -{ - /* B instruction */ - hdr->jump_instruction = 0xEA000000; - /* Jump to the first instr after the header */ - hdr->jump_instruction |= (sizeof(*hdr) / sizeof(uint32_t) - 2); - /* No '0' termination in magic string */ - memcpy(&hdr->magic, BOOT0_MAGIC, 8); - - hdr->length = align(load_size + sizeof(hdr), BLOCK_SIZE); -} - -static long int fsize(FILE *file) -{ - struct stat s; - int fd = fileno(file); - if (fd == -1) return -1; - if (fstat(fd, &s) == -1) return -1; - return s.st_size; -} - -int main(int argc, char *argv[]) -{ - FILE *fd_in, *fd_out; - struct boot_file_head hdr; - long int file_size, load_size; - void *file_data; - uint8_t raw_hdr[HEADER_SIZE]; - int count; - - /* - * TODO: We could take an additional argument to see how much of the - * file to checksum. This way, the build system can tell us how large - * the bootblock is, so we can tell the BROM to load only the bootblock. - */ - if (argc < 2) { - printf("\tThis program makes an input bin file to sun4i " - "bootable image.\n" - "\tUsage: %s input_file out_putfile\n", argv[0]); - return EXIT_FAILURE; - } - - fd_in = fopen(argv[1], "rb"); - if (!fd_in) { - fprintf(stderr, "Cannot open input %s", argv[1]); - return EXIT_FAILURE; - } - - /* Get input file size */ - file_size = fsize(fd_in); - if (file_size == -1) { - fprintf(stderr, "can't determine file size\n"); - return EXIT_FAILURE; - } - if ((file_data = malloc(file_size)) == NULL) { - fprintf(stderr, "Cannot allocate memory\n"); - return EXIT_FAILURE; - } - - printf("File size: 0x%lx\n", file_size); - if (fread(file_data, file_size, 1, fd_in) != 1) { - fprintf(stderr, "Cannot read %s: %s\n", argv[1], - strerror(errno)); - return EXIT_FAILURE; - } - - load_size = align(file_size, sizeof(uint32_t)); - - if (load_size > SRAM_LOAD_MAX_SIZE) - load_size = SRAM_LOAD_MAX_SIZE; - - printf("Load size: 0x%lx\n", load_size); - - fd_out = fopen(argv[2], "w"); - if (!fd_out) { - fprintf(stderr, "Cannot open output %s\n", argv[2]); - return EXIT_FAILURE; - } - - /* Fill the header */ - fill_header(&hdr, load_size); - fill_check_sum(&hdr, file_data); - - /* Now write the header */ - serialize_header(raw_hdr, &hdr); - if (fwrite(raw_hdr, HEADER_SIZE, 1, fd_out) != 1) { - fprintf(stderr, "Cannot write header to %s: %s\n", argv[1], - strerror(errno)); - return EXIT_FAILURE; - } - - /* And finally, the boot code */ - if (fwrite(file_data, file_size, 1, fd_out) != 1) { - fprintf(stderr, "Cannot write to %s: %s\n", argv[1], - strerror(errno)); - return EXIT_FAILURE; - } - - fclose(fd_in); - fclose(fd_out); - - return EXIT_SUCCESS; -} diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 141ec5c7ae..fbe0c3a03e 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -233,7 +233,6 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) { "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f), - "p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)), "c2_latency": FormatHexLE16(FADT[96:98]), "docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)), "spi_uvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]), diff --git a/util/cbfstool/flashmap/fmap.c b/util/cbfstool/flashmap/fmap.c index 06f179f1f9..6255fc5633 100644 --- a/util/cbfstool/flashmap/fmap.c +++ b/util/cbfstool/flashmap/fmap.c @@ -236,8 +236,11 @@ int fmap_print(const struct fmap *fmap) /* Print descriptive strings for flags rather than the field */ flags = fmap->areas[i].flags; - if ((str = fmap_flags_to_string(flags)) == NULL) + str = fmap_flags_to_string(flags); + if (str == NULL) { + kv_pair_free(pair); return -1; + } kv_pair_fmt(pair, "area_flags", "%s", str); free(str); @@ -509,7 +512,8 @@ fmap_find_area_test_exit: static int fmap_flags_to_string_test(void) { - char *str, *my_str; + char *str = NULL; + char *my_str = NULL; unsigned int i; uint16_t flags; @@ -555,11 +559,11 @@ static int fmap_flags_to_string_test(void) printf("FAILURE: bad result from fmap_flags_to_string\n"); goto fmap_flags_to_string_test_exit; } - free(my_str); - free(str); status = pass; fmap_flags_to_string_test_exit: + free(str); + free(my_str); return status; } diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index a8ea815165..c4f4262e87 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -10,12 +10,12 @@ DEST ?= $(CURDIR)/xgcc all all_with_gdb: $(MAKE) build-i386 build-x64 build-arm build-mips \ build-riscv build-aarch64 build-ppc64 build-nds32le \ - build_clang build_iasl build_make + build_clang build_iasl build_make build_nasm all_without_gdb: $(MAKE) SKIP_GDB=1 build-i386 build-x64 build-arm build-mips \ build-riscv build-aarch64 build-ppc64 build-nds32le \ - build_clang build_iasl build_make + build_clang build_iasl build_make build_nasm build_tools: build_gcc build_gdb @@ -43,12 +43,15 @@ endif build_make: bash ./buildgcc -P make $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) -d $(DEST) +build_nasm: + bash ./buildgcc -P nasm $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) -d $(DEST) + ########################################################### build-i386: - @$(MAKE) build_tools BUILD_PLATFORM=i386-elf + @$(MAKE) build_tools build_nasm BUILD_PLATFORM=i386-elf build-x64: - @$(MAKE) build_tools BUILD_PLATFORM=x86_64-elf + @$(MAKE) build_tools build_nasm BUILD_PLATFORM=x86_64-elf build-arm: @$(MAKE) build_tools BUILD_PLATFORM=arm-eabi @@ -86,5 +89,6 @@ distclean: clean .PHONY: build_gcc build_iasl build_gdb build_clang all all_with_gdb \ all_without_gdb build_tools build-i386 build-x64 build-arm \ build-aarch64 build-mips build-riscv build-ppc64 build-nds32le \ + build-nasm \ clean distclean clean_tempfiles .NOTPARALLEL: diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index 8f8257c2f2..0ef6b9c1e3 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -23,6 +23,7 @@ help_toolchain help:: @echo ' iasl - Build coreboot IASL compiler (built by all cross targets)' @echo ' clang - Build coreboot clang compiler' @echo ' gnumake - Build coreboot make' + @echo ' nasm - Build coreboot nasm' @echo ' test-toolchain - Reports if toolchain components are out of date' @echo ' crossgcc-ARCH - Build cross-compiler for specific architecture' @echo ' crosstools-ARCH - Build cross-compiler with GDB for specific architecture' @@ -41,7 +42,7 @@ crossgcc: clean-for-update crossgcc-mips crossgcc-riscv crossgcc-power8 crossgcc-clean iasl \ clang crosstools-i386 crosstools-x64 crosstools-arm \ crosstools-aarch64 crosstools-mips crosstools-riscv crosstools-power8 \ - jenkins-build-toolchain gnumake + jenkins-build-toolchain gnumake nasm $(foreach arch,$(TOOLCHAIN_ARCHES),crossgcc-$(arch)): clean-for-update $(MAKE) -C util/crossgcc $(patsubst crossgcc-%,build-%,$@) build_iasl SKIP_GDB=1 @@ -58,6 +59,9 @@ clang: clean-for-update gnumake: clean-for-update $(MAKE) -C util/crossgcc build_make +nasm: clean-for-update + $(MAKE) -C util/crossgcc build_nasm + $(foreach arch,$(TOOLCHAIN_ARCHES),crosstools-$(arch)): clean-for-update $(MAKE) -C util/crossgcc $(patsubst crosstools-%,build-%,$@) build_iasl diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 327027a565..c7f63c3bee 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -53,14 +53,15 @@ MPC_VERSION=1.1.0 GCC_VERSION=8.3.0 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.32 -GDB_VERSION=8.2.1 -IASL_VERSION=20190509 -PYTHON_VERSION=3.7.2 -EXPAT_VERSION=2.2.6 +GDB_VERSION=8.3 +IASL_VERSION=20190703 +PYTHON_VERSION=3.7.4 +EXPAT_VERSION=2.2.7 # CLANG version number CLANG_VERSION=8.0.0 MAKE_VERSION=4.2.1 -CMAKE_VERSION=3.14.2 +CMAKE_VERSION=3.15.0 +NASM_VERSION=2.14.02 # GCC toolchain archive locations # These are sanitized by the jenkins toolchain test builder, so if @@ -81,12 +82,14 @@ CFE_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/cfe-${CLANG_VERSION}.src CRT_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/compiler-rt-${CLANG_VERSION}.src.tar.xz" CTE_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/clang-tools-extra-${CLANG_VERSION}.src.tar.xz" MAKE_ARCHIVE="https://ftpmirror.gnu.org/make/make-${MAKE_VERSION}.tar.bz2" -CMAKE_ARCHIVE="https://cmake.org/files/v3.14/cmake-${CMAKE_VERSION}.tar.gz" +CMAKE_ARCHIVE="https://cmake.org/files/v3.15/cmake-${CMAKE_VERSION}.tar.gz" +NASM_ARCHIVE="https://www.nasm.us/pub/nasm/releasebuilds/${NASM_VERSION}/nasm-${NASM_VERSION}.tar.bz2" ALL_ARCHIVES="$GMP_ARCHIVE $MPFR_ARCHIVE $MPC_ARCHIVE \ $GCC_ARCHIVE $BINUTILS_ARCHIVE $GDB_ARCHIVE $IASL_ARCHIVE \ $PYTHON_ARCHIVE $EXPAT_ARCHIVE $LLVM_ARCHIVE $CFE_ARCHIVE \ - $CRT_ARCHIVE $CTE_ARCHIVE $MAKE_ARCHIVE $CMAKE_ARCHIVE" + $CRT_ARCHIVE $CTE_ARCHIVE $MAKE_ARCHIVE $CMAKE_ARCHIVE \ + $NASM_ARCHIVE" # GCC toolchain directories GMP_DIR="gmp-${GMP_VERSION}" @@ -107,6 +110,7 @@ CRT_DIR="compiler-rt-${CLANG_VERSION}.src" CTE_DIR="clang-tools-extra-${CLANG_VERSION}.src" MAKE_DIR="make-${MAKE_VERSION}" CMAKE_DIR="cmake-${CMAKE_VERSION}" +NASM_DIR="nasm-${NASM_VERSION}" unset MAKELEVEL MAKEFLAGS @@ -910,6 +914,17 @@ build_CMAKE() { normalize_dirs } +build_NASM() { + CC="$(hostcc host)" CXX="$(hostcxx host)" CFLAGS="$HOSTCFLAGS" + ../${NASM_DIR}/configure --prefix="$TARGETDIR" \ + || touch .failed + # shellcheck disable=SC2086 + $MAKE $JOBS || touch .failed + $MAKE install DESTDIR=$DESTDIR || touch .failed + + normalize_dirs +} + print_supported() { case "$PRINTSUPPORTED" in AUTOCONF|autoconf) printf "%s\n" "$GCC_AUTOCONF_VERSION";; @@ -924,6 +939,7 @@ print_supported() { MPFR|mpfr) printf "%s\n" "$MPFR_VERSION";; PYTHON|python) printf "%s\n" "$PYTHON_VERSION";; MAKE|make) printf "%s\n" "$MAKE_VERSION";; + NASM|nasm) printf "%s\n" "${NASM_VERSION}";; *) printf "Unknown tool %s\n" "$PRINTSUPPORTED";; esac } @@ -1044,8 +1060,12 @@ case "$PACKAGE" in NAME="CMake" PACKAGES=CMAKE ;; + NASM|nasm) + NAME="NASM" + PACKAGES=NASM + ;; *) - printf "${red}ERROR: Unsupported package $PACKAGE. (Supported packages are GCC, GDB, CLANG, IASL, MAKE)${NC}\n\n"; + printf "${red}ERROR: Unsupported package $PACKAGE. (Supported packages are GCC, GDB, CLANG, IASL, MAKE, and NASM)${NC}\n\n"; exit 1 ;; esac diff --git a/util/crossgcc/patches/acpica-unix2-20190509_iasl.patch b/util/crossgcc/patches/acpica-unix2-20190703_iasl.patch similarity index 73% rename from util/crossgcc/patches/acpica-unix2-20190509_iasl.patch rename to util/crossgcc/patches/acpica-unix2-20190703_iasl.patch index 49df22510f..0f6097450b 100644 --- a/util/crossgcc/patches/acpica-unix2-20190509_iasl.patch +++ b/util/crossgcc/patches/acpica-unix2-20190703_iasl.patch @@ -1,6 +1,6 @@ -diff -Naur acpica-unix2-20190509_/source/compiler/asloptions.c acpica-unix2-20190509/source/compiler/asloptions.c > acpica-unix2-20190509_iasl.patch ---- acpica-unix2-20190509_/source/compiler/asloptions.c -+++ acpica-unix2-20190509/source/compiler/asloptions.c +diff -Naur acpica-unix2-20190703_/source/compiler/asloptions.c acpica-unix2-20190703/source/compiler/asloptions.c > acpica-unix2-20190703_iasl.patch +--- acpica-unix2-20190703_/source/compiler/asloptions.c ++++ acpica-unix2-20190703/source/compiler/asloptions.c @@ -126,6 +126,7 @@ if (Gbl_DoSignon) { diff --git a/util/crossgcc/patches/gdb-8.2.1_amd64.patch b/util/crossgcc/patches/gdb-8.2.1_amd64.patch deleted file mode 100644 index 978fa26f6a..0000000000 --- a/util/crossgcc/patches/gdb-8.2.1_amd64.patch +++ /dev/null @@ -1,14 +0,0 @@ -diff -urN gdb-8.2.1.orig/gdb/configure.tgt gdb-8.2.1/gdb/configure.tgt ---- gdb-8.2.1.orig/gdb/configure.tgt 2019-01-04 12:34:10.301072023 +0100 -+++ gdb-8.2.1/gdb/configure.tgt 2019-01-04 12:35:21.948388220 +0100 -@@ -732,6 +732,10 @@ - x86_64-*-rtems*) - gdb_target_obs="${amd64_tobjs} ${i386_tobjs} i386-bsd-tdep.o" - ;; -+x86_64-*-*) -+ # Target: amd64 -+ gdb_target_obs="amd64-tdep.o i386-tdep.o i387-tdep.o" -+ ;; - xtensa*-*-linux*) - # Target: GNU/Linux Xtensa - gdb_target_obs="xtensa-linux-tdep.o symfile-mem.o linux-tdep.o" diff --git a/util/crossgcc/patches/gdb-8.3_amd64.patch b/util/crossgcc/patches/gdb-8.3_amd64.patch new file mode 100644 index 0000000000..47d9a72a66 --- /dev/null +++ b/util/crossgcc/patches/gdb-8.3_amd64.patch @@ -0,0 +1,14 @@ +diff -urN gdb-3.orig/gdb/configure.tgt gdb-8.3/gdb/configure.tgt +--- gdb-8.3.orig/gdb/configure.tgt 2019-02-27 05:51:48.000000000 +0100 ++++ gdb-8.3/gdb/configure.tgt 2019-05-12 08:07:45.624984535 +0200 +@@ -772,6 +772,10 @@ + x86_64-*-rtems*) + gdb_target_obs="${amd64_tobjs} ${i386_tobjs} i386-bsd-tdep.o" + ;; ++x86_64-*-*) ++ # Target: amd6 ++ gdb_target_obs="amd64-tdep.o i386-tdep.o i387-tdep.o" ++ ;; + xtensa*-*-*linux*) + # Target: GNU/Linux Xtensa + gdb_target_obs="xtensa-linux-tdep.o symfile-mem.o linux-tdep.o" diff --git a/util/crossgcc/patches/gdb-8.2.1_no-doc.patch b/util/crossgcc/patches/gdb-8.3_no-doc.patch similarity index 100% rename from util/crossgcc/patches/gdb-8.2.1_no-doc.patch rename to util/crossgcc/patches/gdb-8.3_no-doc.patch diff --git a/util/crossgcc/patches/gdb-8.2.1_pythonhome.patch b/util/crossgcc/patches/gdb-8.3_pythonhome.patch similarity index 100% rename from util/crossgcc/patches/gdb-8.2.1_pythonhome.patch rename to util/crossgcc/patches/gdb-8.3_pythonhome.patch diff --git a/util/crossgcc/sum/Python-3.7.2.tar.xz.cksum b/util/crossgcc/sum/Python-3.7.2.tar.xz.cksum deleted file mode 100644 index 4519f883b8..0000000000 --- a/util/crossgcc/sum/Python-3.7.2.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -c3dc6928516bcb934cf4740461044c79c7c35494 tarballs/Python-3.7.2.tar.xz \ No newline at end of file diff --git a/util/crossgcc/sum/Python-3.7.4.tar.xz.cksum b/util/crossgcc/sum/Python-3.7.4.tar.xz.cksum new file mode 100644 index 0000000000..bc792af12b --- /dev/null +++ b/util/crossgcc/sum/Python-3.7.4.tar.xz.cksum @@ -0,0 +1 @@ +a862c5a58626fdad02d2047a57771ede2783fcef tarballs/Python-3.7.4.tar.xz diff --git a/util/crossgcc/sum/acpica-unix2-20190509.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20190509.tar.gz.cksum deleted file mode 100644 index 2f53d714fb..0000000000 --- a/util/crossgcc/sum/acpica-unix2-20190509.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -aa4d4f8051800e84a5ed5b71635594aaca749e8d tarballs/acpica-unix2-20190509.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum new file mode 100644 index 0000000000..9a89796d53 --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum @@ -0,0 +1 @@ +c5594944f933265a53695204a0672d0808e4a580 tarballs/acpica-unix2-20190703.tar.gz diff --git a/util/crossgcc/sum/cmake-3.14.2.tar.gz.cksum b/util/crossgcc/sum/cmake-3.14.2.tar.gz.cksum deleted file mode 100644 index 6369ac38db..0000000000 --- a/util/crossgcc/sum/cmake-3.14.2.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -94ef8e36fa93edaf6f194e0ce0065ea769b3e57c tarballs/cmake-3.14.2.tar.gz diff --git a/util/crossgcc/sum/cmake-3.15.0.tar.gz.cksum b/util/crossgcc/sum/cmake-3.15.0.tar.gz.cksum new file mode 100644 index 0000000000..3ec1605c5d --- /dev/null +++ b/util/crossgcc/sum/cmake-3.15.0.tar.gz.cksum @@ -0,0 +1 @@ +0a1c3870d566061da8b9ed02bbfe17a39c7bf3cd tarballs/cmake-3.15.0.tar.gz diff --git a/util/crossgcc/sum/expat-2.2.6.tar.bz2.cksum b/util/crossgcc/sum/expat-2.2.6.tar.bz2.cksum deleted file mode 100644 index d21481960e..0000000000 --- a/util/crossgcc/sum/expat-2.2.6.tar.bz2.cksum +++ /dev/null @@ -1 +0,0 @@ -c8947fc3119a797b55485f2f7bdaaeb49cc9df01 tarballs/expat-2.2.6.tar.bz2 diff --git a/util/crossgcc/sum/expat-2.2.7.tar.bz2.cksum b/util/crossgcc/sum/expat-2.2.7.tar.bz2.cksum new file mode 100644 index 0000000000..77f627233b --- /dev/null +++ b/util/crossgcc/sum/expat-2.2.7.tar.bz2.cksum @@ -0,0 +1 @@ +9c8a268211e3f1ae31c4d550e5be7708973ec6a6 tarballs/expat-2.2.7.tar.bz2 diff --git a/util/crossgcc/sum/gdb-8.2.1.tar.xz.cksum b/util/crossgcc/sum/gdb-8.2.1.tar.xz.cksum deleted file mode 100644 index a976106ede..0000000000 --- a/util/crossgcc/sum/gdb-8.2.1.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -023556a6d6effa1ffaadf0007cc4458cbe8dde3d tarballs/gdb-8.2.1.tar.xz diff --git a/util/crossgcc/sum/gdb-8.3.tar.xz.cksum b/util/crossgcc/sum/gdb-8.3.tar.xz.cksum new file mode 100644 index 0000000000..bc82f51e37 --- /dev/null +++ b/util/crossgcc/sum/gdb-8.3.tar.xz.cksum @@ -0,0 +1 @@ +f45de6af561f0fa0241f0d5085198556fcfd1e5e tarballs/gdb-8.3.tar.xz diff --git a/util/crossgcc/sum/nasm-2.14.02.tar.bz2.cksum b/util/crossgcc/sum/nasm-2.14.02.tar.bz2.cksum new file mode 100644 index 0000000000..f3b9de9d29 --- /dev/null +++ b/util/crossgcc/sum/nasm-2.14.02.tar.bz2.cksum @@ -0,0 +1 @@ +fe098ee4dc9c4c983696c4948e64b23e4098b92b tarballs/nasm-2.14.02.tar.bz2 diff --git a/util/ectool/Makefile b/util/ectool/Makefile index c4b94da75f..fdda265064 100644 --- a/util/ectool/Makefile +++ b/util/ectool/Makefile @@ -15,7 +15,7 @@ ## CC = gcc -CFLAGS = -O2 -Wall -W +CFLAGS = -O2 -Wall -Wextra PROGRAM = ectool INSTALL = /usr/bin/env install PREFIX = /usr/local diff --git a/util/ifdtool/Makefile b/util/ifdtool/Makefile index 4cddfc5542..cc52b1ed4a 100644 --- a/util/ifdtool/Makefile +++ b/util/ifdtool/Makefile @@ -18,7 +18,7 @@ PROGRAM = ifdtool CC = gcc INSTALL = /usr/bin/env install PREFIX = /usr/local -CFLAGS = -O2 -g -Wall -W -Wmissing-prototypes -Werror -I../../src/commonlib/include +CFLAGS = -O2 -g -Wall -Wextra -Wmissing-prototypes -Werror -I../../src/commonlib/include LDFLAGS = OBJS = ifdtool.o diff --git a/util/intelmetool/Makefile b/util/intelmetool/Makefile index 45a87c7e28..55ba82a424 100644 --- a/util/intelmetool/Makefile +++ b/util/intelmetool/Makefile @@ -17,7 +17,7 @@ PROGRAM = intelmetool CC ?= gcc INSTALL ?= /usr/bin/env install PREFIX ?= /usr/local -CFLAGS ?= -O0 -g -Wall -W -Wno-unused-parameter -Wno-sign-compare -Wno-unused-function +CFLAGS ?= -O0 -g -Wall -Wextra -Wno-unused-parameter -Wno-sign-compare -Wno-unused-function LDFLAGS += -lpci -lz OBJS = intelmetool.o me.o me_status.o mmap.o rcba.o msr.o diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index 0f74a7c257..cd02fa8abe 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -22,7 +22,7 @@ top ?= $(abspath ../..) CC ?= gcc INSTALL ?= /usr/bin/env install PREFIX ?= /usr/local -CFLAGS ?= -O2 -g -Wall -W -Wmissing-prototypes +CFLAGS ?= -O2 -g -Wall -Wextra -Wmissing-prototypes LDFLAGS += -lpci -lz CPPFLAGS += -I$(top)/src/commonlib/include diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index ff69b8cf69..d2c8ede2ca 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -110,7 +110,7 @@ static msr_t rdmsr(int addr) static int open_and_seek(int cpu, unsigned long msr, int mode, int *fd) { - char dev[512]; + char dev[32]; char temp_string[50]; snprintf(dev, sizeof(dev), "/dev/cpu/%d/msr", cpu); diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index e48a2c51f5..741aed4cca 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1024,9 +1024,17 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) gpio_registers = baytrail_score_ssus_gpio_registers; size = ARRAY_SIZE(baytrail_score_ssus_gpio_registers); break; + case PCI_DEVICE_ID_INTEL_H110: + case PCI_DEVICE_ID_INTEL_H170: + case PCI_DEVICE_ID_INTEL_Z170: + case PCI_DEVICE_ID_INTEL_Q170: + case PCI_DEVICE_ID_INTEL_Q150: case PCI_DEVICE_ID_INTEL_B150: - case PCI_DEVICE_ID_INTEL_CM236: case PCI_DEVICE_ID_INTEL_C236: + case PCI_DEVICE_ID_INTEL_C232: + case PCI_DEVICE_ID_INTEL_QM170: + case PCI_DEVICE_ID_INTEL_HM170: + case PCI_DEVICE_ID_INTEL_CM236: case PCI_DEVICE_ID_INTEL_APL_LPC: case PCI_DEVICE_ID_INTEL_DNV_LPC: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 3c0fedbfbf..0387418250 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -1772,9 +1772,17 @@ void print_gpio_groups(struct pci_dev *const sb) size_t pad_stepping = 8; switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_H110: + case PCI_DEVICE_ID_INTEL_H170: + case PCI_DEVICE_ID_INTEL_Z170: + case PCI_DEVICE_ID_INTEL_Q170: + case PCI_DEVICE_ID_INTEL_Q150: case PCI_DEVICE_ID_INTEL_B150: - case PCI_DEVICE_ID_INTEL_CM236: case PCI_DEVICE_ID_INTEL_C236: + case PCI_DEVICE_ID_INTEL_C232: + case PCI_DEVICE_ID_INTEL_QM170: + case PCI_DEVICE_ID_INTEL_HM170: + case PCI_DEVICE_ID_INTEL_CM236: community_count = ARRAY_SIZE(sunrise_communities); communities = sunrise_communities; pcr_init(sb); diff --git a/util/nvidia/Makefile.inc b/util/nvidia/Makefile.inc index 133778f592..1894fadc2b 100644 --- a/util/nvidia/Makefile.inc +++ b/util/nvidia/Makefile.inc @@ -43,6 +43,10 @@ CBOOTIMAGE_SRCS:=$(addprefix util/nvidia/cbootimage/src/,$(filter %.c,$(CBOOTIMA CBOOTIMAGE_OBJS:=$(addprefix $(objutil)/nvidia/cbootimage/,$(patsubst %.c,%.o,$(filter %.c,$(CBOOTIMAGE_RAW_SRCS)))) CBOOTIMAGE_FLAGS:=-Wall -std=c99 -O2 +ifeq ($(OS_ARCH), FreeBSD) +CBOOTIMAGE_FLAGS:=-DENODATA=ENOATTR +endif + additional-dirs += $(sort $(dir $(CBOOTIMAGE_OBJS))) $(objutil)/nvidia/cbootimage/%.o: util/nvidia/cbootimage/src/%.c diff --git a/util/nvramtool/Makefile b/util/nvramtool/Makefile index 46297a2de9..c210234dbc 100644 --- a/util/nvramtool/Makefile +++ b/util/nvramtool/Makefile @@ -19,7 +19,7 @@ PROGRAM = nvramtool CC = gcc INSTALL = /usr/bin/env install PREFIX = /usr/local -CFLAGS = -O2 -g -Wall -W -Wmissing-prototypes -I. -DCMOS_HAL=1 +CFLAGS = -O2 -g -Wall -Wextra -Wmissing-prototypes -I. -DCMOS_HAL=1 #CFLAGS = -Os -Wall CLI_OBJS = cli/nvramtool.o cli/opts.o diff --git a/util/pmh7tool/Makefile b/util/pmh7tool/Makefile index 384d3d9c4e..034ed40c59 100644 --- a/util/pmh7tool/Makefile +++ b/util/pmh7tool/Makefile @@ -14,7 +14,7 @@ ## CC = gcc -CFLAGS = -O2 -Wall -W -Werror +CFLAGS = -O2 -Wall -Wextra -Werror PROGRAM = pmh7tool INSTALL = /usr/bin/env install PREFIX = /usr/local diff --git a/util/release/build-release b/util/release/build-release index a08b405ba8..224be5b0b4 100755 --- a/util/release/build-release +++ b/util/release/build-release @@ -58,8 +58,8 @@ printf "%s-%s\n" "$VERSION_NAME" "$(git log --pretty=%H|head -1)" > .coreboot-v tstamp=$(git log --pretty=format:%ci -1) cd .. -tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude=*/.git --exclude=*/.gitignore --exclude="coreboot-${VERSION_NAME}/3rdparty/blobs" --exclude="coreboot-${VERSION_NAME}/3rdparty/fsp" -cvf - "coreboot-${VERSION_NAME}" |xz -9 > "coreboot-${VERSION_NAME}.tar.xz" -tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude=*/.git --exclude=*/.gitignore -cvf - "coreboot-${VERSION_NAME}/3rdparty/blobs" "coreboot-${VERSION_NAME}/3rdparty/fsp" |xz -9 > "coreboot-blobs-${VERSION_NAME}.tar.xz" +tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude=*/.git --exclude=*/.gitignore --exclude="coreboot-${VERSION_NAME}/3rdparty/blobs" --exclude="coreboot-${VERSION_NAME}/3rdparty/fsp" --exclude="coreboot-${VERSION_NAME}/3rdparty/intel-microcode" -cvf - "coreboot-${VERSION_NAME}" |xz -9 > "coreboot-${VERSION_NAME}.tar.xz" +tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude=*/.git --exclude=*/.gitignore -cvf - "coreboot-${VERSION_NAME}/3rdparty/blobs" "coreboot-${VERSION_NAME}/3rdparty/fsp" "coreboot-${VERSION_NAME}/3rdparty/intel-microcode" |xz -9 > "coreboot-blobs-${VERSION_NAME}.tar.xz" if [ -n "${GPG_KEY_ID}" ]; then gpg --armor --local-user "$GPG_KEY_ID" --output "coreboot-${VERSION_NAME}.tar.xz.sig" --detach-sig "coreboot-${VERSION_NAME}.tar.xz" diff --git a/util/release/genrelnotes b/util/release/genrelnotes index e4f304b727..2867cbffee 100755 --- a/util/release/genrelnotes +++ b/util/release/genrelnotes @@ -202,12 +202,12 @@ show_diff () { local new local old - new="$(comm -13 <(echo "$2") <(echo "$3"))" + new="$(comm -13 <(echo "$2") <(echo "$3") | sed 's/^/* /')" if [ -n "$new" ]; then printf "Added %s $1:\n-------------------\n%s\n\n" \ "$(echo "$new" | wc -l)" "$new" >> "$LOGFILE" fi - old="$(comm -23 <(echo "$2") <(echo "$3"))" + old="$(comm -23 <(echo "$2") <(echo "$3") | sed 's/^/* /')" if [ -n "$old" ]; then printf "Removed %s $1:\n-------------------\n%s\n\n" \ "$(echo "$old" | wc -l)" "$old" >> "$LOGFILE" diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 85e0d8ea7f..5e3a1d405e 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -815,18 +815,6 @@ static void pass1(FILE *fil, struct device *ptr, struct device *next) fprintf(fil, "\t.subsystem_vendor = 0x%04x,\n", ptr->subsystem_vendor); - for (pin = 0; pin < 4; pin++) { - if (ptr->pci_irq_info[pin].ioapic_irq_pin > 0) - fprintf(fil, - "\t.pci_irq_info[%d].ioapic_irq_pin = %d,\n", - pin, ptr->pci_irq_info[pin].ioapic_irq_pin); - - if (ptr->pci_irq_info[pin].ioapic_dst_id > 0) - fprintf(fil, - "\t.pci_irq_info[%d].ioapic_dst_id = %d,\n", - pin, ptr->pci_irq_info[pin].ioapic_dst_id); - } - if (ptr->subsystem_device > 0) fprintf(fil, "\t.subsystem_device = 0x%04x,\n", ptr->subsystem_device); @@ -843,6 +831,17 @@ static void pass1(FILE *fil, struct device *ptr, struct device *next) if (ptr->sibling) fprintf(fil, "\t.sibling = &%s,\n", ptr->sibling->name); fprintf(fil, "#if !DEVTREE_EARLY\n"); + for (pin = 0; pin < 4; pin++) { + if (ptr->pci_irq_info[pin].ioapic_irq_pin > 0) + fprintf(fil, + "\t.pci_irq_info[%d].ioapic_irq_pin = %d,\n", + pin, ptr->pci_irq_info[pin].ioapic_irq_pin); + + if (ptr->pci_irq_info[pin].ioapic_dst_id > 0) + fprintf(fil, + "\t.pci_irq_info[%d].ioapic_dst_id = %d,\n", + pin, ptr->pci_irq_info[pin].ioapic_dst_id); + } fprintf(fil, "\t.chip_ops = &%s_ops,\n", chip_ins->chip->name_underscore); if (chip_ins == &mainboard_instance) diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index 80e29efc83..d84c5a4f9b 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -80,11 +80,16 @@ CPUS?=4 lint lint-stable lint-extended: util/lint/lint $@ +ABUILD_OPTIONS=-B -J -c $(CPUS) -z -p $(JENKINS_PAYLOAD) +ABUILD_OPTIONS+=$(if $(V),-v,) +ABUILD_OPTIONS+=$(if $(JENKINS_NOCCACHE),,-y) +ABUILD_OPTIONS+=$(JENKINS_ABUILD_OPT) + what-jenkins-does: util/lint/lint lint-stable --junit util/lint/lint lint-extended --junit - util/abuild/abuild -B -J $(if $(V),-v,) $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD) -x -X $(top)/abuild-chromeos.xml - util/abuild/abuild -B -J $(if $(V),-v,) $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD) + util/abuild/abuild $(ABUILD_OPTIONS) -x -X $(top)/abuild-chromeos.xml + util/abuild/abuild $(ABUILD_OPTIONS) $(foreach tool, $(TOOLLIST), $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR="util/$(tool)" BLD="$(tool)" MFLAGS= MAKEFLAGS= MAKETARGET= junit.xml; ) unset COREBOOT_BUILD_DIR;$(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=payloads/nvramcui BLD=nvramcui MFLAGS= MAKEFLAGS= MAKETARGET=all junit.xml unset COREBOOT_BUILD_DIR;$(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=payloads/coreinfo BLD=coreinfo MFLAGS= MAKEFLAGS= MAKETARGET=defaultbuild junit.xml diff --git a/util/viatool/Makefile b/util/viatool/Makefile index b2a62917d6..f58cbd37fb 100644 --- a/util/viatool/Makefile +++ b/util/viatool/Makefile @@ -21,7 +21,7 @@ PROGRAM = viatool CC ?= gcc INSTALL ?= /usr/bin/env install PREFIX ?= /usr/local -CFLAGS ?= -O2 -g -Wall -W -I$(CURDIR) +CFLAGS ?= -O2 -g -Wall -Wextra -I$(CURDIR) LDFLAGS += -lpci -lz SRCS = viatool.c \ diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index e8d6677994..f431625878 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -98,6 +98,7 @@ fi cat <