clean up age old via epia target.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/Kconfig

@@ -622,7 +622,8 @@ config DEBUG_SMBUS
 		 || NORTHBRIDGE_VIA_VX800 \
 		 || NORTHBRIDGE_VIA_CX700 \
 		 || NORTHBRIDGE_AMD_AMDK8 \
-		 || NORTHBRIDGE_AMD_AMDFAM10)
+		 || NORTHBRIDGE_AMD_AMDFAM10 \
+		 || SOUTHBRIDGE_VIA_VT8231)
 	help
 	  This option enables additional SMBus (and SPD) debug messages.
 

src/cpu/x86/mtrr/earlymtrr.c

@@ -53,7 +53,7 @@ static void set_var_mtrr_x(
 }
 #endif
 
-static void cache_lbmem(int type)
+static inline void cache_lbmem(int type)
 {
 	/* Enable caching for 0 - 1MB using variable mtrr */
 	disable_cache();
@@ -118,7 +118,7 @@ static void early_mtrr_init(void)
 	enable_cache();
 }
 
-static int early_mtrr_init_detected(void)
+static inline int early_mtrr_init_detected(void)
 {
 	msr_t msr;
 	/* See if MTRR's are enabled.

src/mainboard/via/epia-m/romstage.c

@@ -78,7 +78,6 @@ static void enable_shadow_ram(void)
 
 static void main(unsigned long bist)
 {
-	unsigned long x;
 	device_t dev;
 
 	/*

src/mainboard/via/epia/romstage.c

@@ -13,7 +13,6 @@
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
 #include "lib/debug.c"
 #include "southbridge/via/vt8231/vt8231_early_smbus.c"
 #include "southbridge/via/vt8231/vt8231_early_serial.c"
@@ -76,10 +75,8 @@ static void enable_shadow_ram(void)
 	pci_write_config8(dev, 0x63, shadowreg);
 }
 
-static void main(unsigned long bist)
+void main(unsigned long bist)
 {
-	unsigned long x;
-	
 	if (bist == 0) {
 		early_mtrr_init();
 	}

src/northbridge/via/vt8601/raminit.c

@@ -47,7 +47,7 @@ it with the version available from LANL.
 #define DIMM_CL2 0
 #endif
 
-void dimms_read(unsigned long x)
+static void dimms_read(unsigned long x)
 {
 	uint8_t c;
 	unsigned long eax;
@@ -59,7 +59,7 @@ void dimms_read(unsigned long x)
 	}
 }
 
-void dimms_write(int x)
+static void dimms_write(int x)
 {
 	uint8_t c;
 	unsigned long eax = x;
@@ -69,7 +69,8 @@ void dimms_write(int x)
 	}
 }
 
-void dumpnorth(device_t north)
+#ifdef CONFIG_DEBUG_RAM_SETUP
+static void dumpnorth(device_t north)
 {
 	unsigned int r, c;
 	for (r = 0;; r += 16) {
@@ -84,11 +85,11 @@ void dumpnorth(device_t north)
 			break;
 	}
 }
+#endif
 
 static void sdram_set_registers(const struct mem_controller *ctrl)
 {
 	device_t north = (device_t) PCI_DEV(0, 0, 0);
-	uint8_t c, r;
 
 	print_err("vt8601 init starting\n");
 	print_debug_hex32(north);
@@ -175,7 +176,7 @@ static unsigned long spd_module_size(unsigned char slot)
 	 * module. This is just a very early first cut at sizing.
 	 */
 	/* we may run out of registers ... */
-	unsigned int banks, rows, cols, reg;
+	unsigned int banks, rows, cols;
 	unsigned int value = 0;
 	/* unsigned int module = ((0x50 + slot) << 1) + 1; */
 	unsigned int module = 0x50 + slot;
@@ -213,9 +214,9 @@ static unsigned long spd_module_size(unsigned char slot)
 	}
 	print_info("\n");
 	return value;
-
 }
 
+#if 0
 static int spd_num_chips(unsigned char slot)
 {
 	unsigned int module = 0x50 + slot;
@@ -226,6 +227,7 @@ static int spd_num_chips(unsigned char slot)
 		width = 8;
 	return 64 / width;
 }
+#endif
 
 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 {
@@ -275,7 +277,6 @@ static void set_ma_mapping(device_t north, int slot, int type)
 
 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 {
-	unsigned char i;
 	static const uint8_t ramregs[] = {
 		0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
 	};

src/southbridge/via/vt8231/vt8231.c

@@ -12,11 +12,6 @@
 /* Base 8231 controller */
 static device_t lpc_dev;
 
-void hard_reset(void)
-{
-        printk(BIOS_ERR, "NO HARD RESET ON VT8231! FIX ME!\n");
-}
-
 static void keyboard_on(void)
 {
 	unsigned char regval;

src/southbridge/via/vt8231/vt8231_early_serial.c

@@ -31,7 +31,6 @@ static void vt8231_writesioword(uint16_t reg, uint16_t val)
 
 static void enable_vt8231_serial(void) 
 {
-	unsigned long x;
 	uint8_t c;
 	device_t dev;
 	outb(6, 0x80);

src/southbridge/via/vt8231/vt8231_early_smbus.c

@@ -107,6 +107,7 @@ static int smbus_wait_until_done(void)
 	return loops ? 0 : -3;
 }
 
+#if 0
 void smbus_reset(void)
 {
 	outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
@@ -119,7 +120,9 @@ void smbus_reset(void)
 	print_debug_hex8(inb(SMBUS_IO_BASE + SMBHSTSTAT));
 	print_debug("\n");
 }
+#endif
 
+#if CONFIG_DEBUG_SMBUS
 static void smbus_print_error(unsigned char host_status_register)
 {
 
@@ -142,6 +145,7 @@ static void smbus_print_error(unsigned char host_status_register)
 		print_err("Host Busy\n");
 	}
 }
+#endif
 
 /*
  * Copied from intel/i82801dbm early smbus code - suggested by rgm.
@@ -150,7 +154,6 @@ static void smbus_print_error(unsigned char host_status_register)
  */
 static int smbus_read_byte(unsigned device, unsigned address)
 {
-	unsigned char global_control_register;
 	unsigned char global_status_register;
 	unsigned char byte;
 

src/southbridge/via/vt8231/vt8231_lpc.c

@@ -10,7 +10,6 @@
 
 /* PIRQ init
  */
-void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]);
 static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 };
 static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
 static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };
@@ -55,7 +54,6 @@ static void pci_routing_fixup(struct device *dev)
 static void vt8231_init(struct device *dev)
 {
 	unsigned char enables;
-	struct southbridge_via_vt8231_config *conf = dev->chip_info;
 
 	printk(BIOS_DEBUG, "vt8231 init\n");
 
@@ -130,7 +128,7 @@ static void vt8231_init(struct device *dev)
 	rtc_init(0);
 }
 
-void vt8231_read_resources(device_t dev)
+static void vt8231_read_resources(device_t dev)
 {
 	struct resource *res;