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intel/i945 intel/i82801gx: remove explicit pcie config accesses

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Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.

Change-Id: I46e69154cf576ddb642c34b6dd2bc0d27cc19b7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3811
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Kyösti Mälkki
2013-07-26 08:52:10 +03:00
parent 9b143e1474
commit 8aa7e83994
5 changed files with 94 additions and 97 deletions
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13
src/southbridge/intel/i82801gx/pcie.c
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@@ -55,20 +55,17 @@ static void pci_init(struct device *dev)
reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0);
pci_write_config32(dev, 0xe1, reg32);
#if CONFIG_MMCONF_SUPPORT
/* Set VC0 transaction class */
reg32 = pci_mmio_read_config32(dev, 0x114);
reg32 = pci_read_config32(dev, 0x114);
reg32 &= 0xffffff00;
reg32 |= 1;
pci_mmio_write_config32(dev, 0x114, reg32);
pci_write_config32(dev, 0x114, reg32);
/* Mask completion timeouts */
reg32 = pci_mmio_read_config32(dev, 0x148);
reg32 = pci_read_config32(dev, 0x148);
reg32 |= (1 << 14);
pci_mmio_write_config32(dev, 0x148, reg32);
#else
#error "MMIO needed for ICH7 PCIe"
#endif
pci_write_config32(dev, 0x148, reg32);
/* Enable common clock configuration */
// Are there cases when we don't want that?
reg16 = pci_read_config16(dev, 0x50);