src/mainboard: Capitalize ROM, RAM, CPU and APIC

Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15987
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/mainboard/amd/db-ft3b-lc/Makefile.inc

@@ -27,7 +27,7 @@ SPD_SOURCES  = Memphis_MEM4G16D3EABG
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \

src/mainboard/amd/db800/irq_tables.c

@@ -52,7 +52,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	{
 	 /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
 	 /* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
-	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* cpu */
+	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* CPU */
 	 {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */
 	 {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* ethernet */
 	 {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0},	/* slot1 */

src/mainboard/amd/dbm690t/fadt.c

@@ -25,7 +25,7 @@
 #include "southbridge/amd/sb600/sb600.h"
 
 /*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
 /* pm_base should be got from bar2 of rs690. Here I compact ACPI
  * registers into 32 bytes limit.
  * */

src/mainboard/amd/dinar/buildOpts.c

@@ -54,10 +54,10 @@
 #define POWER_DOWN_BY_CHANNEL		0	///< Channel power down mode
 #define POWER_DOWN_BY_CHIP_SELECT	1	///< Chip select power down mode
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  TRUE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE

src/mainboard/amd/dinar/romstage.c

@@ -94,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 
 	post_code(0x43);
-	printk(BIOS_DEBUG, "Disabling cache as ram ");
+	printk(BIOS_DEBUG, "Disabling cache as RAM ");
 	disable_cache_as_ram();
 	printk(BIOS_DEBUG, "done\n");
 

src/mainboard/amd/f2950/irq_tables.c

@@ -52,7 +52,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	{
 	 /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
 	 /* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
-	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* cpu */
+	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* CPU */
 	 {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
 	 {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},   /* ethernet */
 	 }

src/mainboard/amd/inagua/buildOpts.c

@@ -30,13 +30,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/* Select the cpu family. */
+/* Select the CPU family. */
 #define INSTALL_FAMILY_10_SUPPORT		FALSE
 #define INSTALL_FAMILY_12_SUPPORT		FALSE
 #define INSTALL_FAMILY_14_SUPPORT		TRUE
 #define INSTALL_FAMILY_15_SUPPORT		FALSE
 
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
 #define INSTALL_G34_SOCKET_SUPPORT		FALSE
 #define INSTALL_C32_SOCKET_SUPPORT 		FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT		FALSE

src/mainboard/amd/norwich/irq_tables.c

@@ -52,7 +52,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	{
 	 /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
 	 /* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
-	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* cpu */
+	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* CPU */
 	 {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */
 	 {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0},	/* slot1 */
 	 {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0},	/* slot2 */

src/mainboard/amd/parmer/buildOpts.c

@@ -30,13 +30,13 @@
 #include "Filecode.h"
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT FALSE
 #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE

src/mainboard/amd/persimmon/buildOpts.c

@@ -30,13 +30,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/*	Select the cpu family.	*/
+/*	Select the CPU family.	*/
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT TRUE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*	Select the cpu socket type.	*/
+/*	Select the CPU socket type.	*/
 #define INSTALL_G34_SOCKET_SUPPORT	FALSE
 #define INSTALL_C32_SOCKET_SUPPORT	FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE

src/mainboard/amd/pistachio/fadt.c

@@ -25,7 +25,7 @@
 #include "southbridge/amd/sb600/sb600.h"
 
 /*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
 /* pm_base should be got from bar2 of rs690. Here I compact ACPI
  * registers into 32 bytes limit.
  * */

src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl

@@ -61,7 +61,7 @@
 
             Device (SBC3)
             {
-                /*  acpi smbus   it should be 0x00040003 if 8131 present */
+                /*  ACPI smbus   it should be 0x00040003 if 8131 present */
 		Method (_ADR, 0, NotSerialized)
 		{
 			Return (DADD(\_SB.PCI0.SBDN, 0x00010003))

src/mainboard/amd/serengeti_cheetah/fadt.c

@@ -21,7 +21,7 @@
 #include <console/console.h>
 #include <arch/acpi.h>
 
-extern unsigned pm_base; /* pm_base should be set in sb acpi */
+extern unsigned pm_base; /* pm_base should be set in sb ACPI */
 
 void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
 

src/mainboard/amd/serengeti_cheetah/get_bus_conf.c

@@ -77,7 +77,7 @@ static unsigned get_hcid(unsigned i)
 
 	// we may need more way to find out hcid: subsystem id? GPIO read ?
 
-	// we need use id for 1. bus num, 2. mptable, 3. acpi table
+	// we need use id for 1. bus num, 2. mptable, 3. ACPI table
 
 	return id;
 }

src/mainboard/amd/serengeti_cheetah/readme_acpi.txt

@@ -1,4 +1,4 @@
-At this time, For acpi support We got
+At this time, For ACPI support We got
 1. support AMK K8 SRAT --- dynamically (coreboot run-time)  (src/northbridge/amd/amdk8/amdk8_acpi.c)
 2. support MADT ---- dynamically (coreboot run-time)  (src/northbridge/amd/amdk8/amdk8_acpi.c , src/mainboard/amd/serengeti_cheetah/acpi_tables.c)
 3. support DSDT ---- dynamically (Compile time, coreboot run-time, ACPI run-time) (src/mainboard/amd/serengeti_cheetah/{acpi/*, get_bus_conf.c}, src/northbridge/amd/amdk8/get_sblk_pci1234.c)

src/mainboard/amd/serengeti_cheetah/romstage.c

@@ -224,5 +224,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
 #endif
 
-        post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+        post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
 }

src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111.asl

@@ -53,7 +53,7 @@
 
 	Device (SBC3)
 	{
-		// acpi smbus it should be 0x00040003 if 8131 present
+		// ACPI smbus it should be 0x00040003 if 8131 present
 		Method (_ADR, 0, NotSerialized)
 		{
 			Return (DADD(\_SB.PCI0.SBDN, 0x00010003))

src/mainboard/amd/serengeti_cheetah_fam10/fadt.c

@@ -24,7 +24,7 @@
 #include <console/console.h>
 #include <arch/acpi.h>
 
-extern u32 pm_base; /* pm_base should be set in sb acpi */
+extern u32 pm_base; /* pm_base should be set in sb ACPI */
 
 void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
 

src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c

@@ -81,7 +81,7 @@ static u32 get_hcid(u32 i)
 		break;
 	}
 	// we may need more way to find out hcid: subsystem id? GPIO read ?
-	// we need use id for 1. bus num, 2. mptable, 3. acpi table
+	// we need use id for 1. bus num, 2. mptable, 3. ACPI table
 	return id;
 }
 

src/mainboard/amd/south_station/buildOpts.c

@@ -30,13 +30,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT TRUE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE

src/mainboard/amd/thatcher/buildOpts.c

@@ -30,13 +30,13 @@
 #include "Filecode.h"
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT FALSE
 #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE

src/mainboard/amd/torpedo/buildOpts.c

@@ -31,13 +31,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT TRUE
 #define INSTALL_FAMILY_14_SUPPORT FALSE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE

src/mainboard/amd/torpedo/fadt.c

@@ -27,7 +27,7 @@
 #include "SbPlatform.h"
 
 /*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
 /* pm_base should be got from bar2 of sb900. Here I compact ACPI
  * registers into 32 bytes limit.
  * */

src/mainboard/amd/torpedo/mptable.c

@@ -77,7 +77,7 @@ static void *smp_write_config_table(void *v)
   mptable_init(mc, LOCAL_APIC_ADDR);
   memcpy(mc->mpc_oem, "AMD     ", 8);
 
-  /*Inagua used dure core cpu with one die */
+  /*Inagua used dure core CPU with one die */
   boot_apic_id = lapicid();
   apic_version = lapic_read(LAPIC_LVR) & 0xff;
   result = cpuid(1);

src/mainboard/amd/union_station/buildOpts.c

@@ -30,13 +30,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT TRUE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE

src/mainboard/apple/macbook21/cmos.layout

@@ -72,7 +72,7 @@ entries
 984         16       h       0        check_sum
 #1000        24       r       0        amd_reserved
 
-# ram initialization internal data
+# RAM initialization internal data
 1024         8       r       0        C0WL0REOST
 1032         8       r       0        C1WL0REOST
 1040         8       r       0        RCVENMT

src/mainboard/artecgroup/dbe61/irq_tables.c

@@ -52,7 +52,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	{
 	 /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
 	 /* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
-	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* cpu */
+	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* CPU */
 	 {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */
 	 {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* ethernet */
 	 }

src/mainboard/asrock/e350m1/buildOpts.c

@@ -31,13 +31,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT TRUE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE

src/mainboard/asus/f2a85-m/buildOpts.c

@@ -43,13 +43,13 @@
 
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT FALSE
 #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE

src/mainboard/asus/f2a85-m_le/buildOpts.c

@@ -43,13 +43,13 @@
 
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT FALSE
 #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE

src/mainboard/asus/kcma-d8/resourcemap.c

@@ -196,7 +196,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of cpu 0 --> AMD SR5690 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -267,7 +267,7 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of cpu 0 --> AMD SR5690 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
@@ -451,7 +451,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of cpu 0 --> AMD SR5690 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -522,7 +522,7 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of cpu 0 --> AMD SR5690 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,

src/mainboard/asus/kcma-d8/romstage.c

@@ -532,7 +532,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x3B);
 
-	/* Wait for all APs to be stopped, otherwise ram initialization may hang */
+	/* Wait for all APs to be stopped, otherwise RAM initialization may hang */
 	if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
 		wait_all_other_cores_stopped(bsp_apicid);
 

src/mainboard/asus/kfsn4-dre/resourcemap.c

@@ -196,7 +196,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of cpu 0 --> Nvidia CK 804 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> Nvidia CK 804 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -267,7 +267,7 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of cpu 0 --> Nvidia CK 804 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> Nvidia CK 804 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,

src/mainboard/asus/kfsn4-dre_k8/resourcemap.c

@@ -196,7 +196,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of cpu 0 --> Nvidia CK 804 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> Nvidia CK 804 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -267,7 +267,7 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of cpu 0 --> Nvidia CK 804 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> Nvidia CK 804 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,

src/mainboard/asus/kgpe-d16/resourcemap.c

@@ -196,7 +196,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of cpu 0 --> AMD SR5690 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> AMD SR5690 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -267,7 +267,7 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of cpu 0 --> AMD SR5690 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> AMD SR5690 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
@@ -451,7 +451,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff110, /* link 3 of cpu 0 --> AMD SR5690 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff110, /* link 3 of CPU 0 --> AMD SR5690 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -522,7 +522,7 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000303, /* link 3 of cpu 0 --> AMD SR5690 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000303, /* link 3 of CPU 0 --> AMD SR5690 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,

src/mainboard/asus/kgpe-d16/romstage.c

@@ -573,7 +573,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x3B);
 
-	/* Wait for all APs to be stopped, otherwise ram initialization may hang */
+	/* Wait for all APs to be stopped, otherwise RAM initialization may hang */
 	if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
 		wait_all_other_cores_stopped(bsp_apicid);
 

src/mainboard/asus/m2n-e/resourcemap.c

@@ -265,7 +265,7 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
+//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
 		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,

src/mainboard/asus/p2b/dsdt.asl

@@ -28,7 +28,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE  ", "COREBOOT", 1)
 	 * 3: powered on suspend, CPU context lost			S1
 	 *    Note: Looks like 'CPU context lost' does _not_ mean the
 	 *          CPU restarts at the reset vector. Most likely only
-	 *          caches are lost, so both 0x3 and 0x4 map to acpi S1
+	 *          caches are lost, so both 0x3 and 0x4 map to ACPI S1
 	 * 4: powered on suspend, context maintained			S1
 	 * 5: working (clock control)					S0
 	 * 6: reserved

src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex

@@ -15,7 +15,7 @@
 # GNU General Public License for more details.
 
 # Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
-# BAP ODE E21XX has 2GB ram soldered down on the Q7
+# BAP ODE E21XX has 2GB RAM soldered down on the Q7
 # Memory setting for DDR-1066
 
 #	0 Number of SPD Bytes used / Total SPD Size / CRC Coverage

src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex

@@ -15,7 +15,7 @@
 # GNU General Public License for more details.
 
 # Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
-# BAP ODE E21XX has 2GB ram soldered down on the Q7
+# BAP ODE E21XX has 2GB RAM soldered down on the Q7
 # Memory setting for DDR-1333
 
 #	0 Number of SPD Bytes used / Total SPD Size / CRC Coverage

src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex

@@ -15,7 +15,7 @@
 # GNU General Public License for more details.
 
 # Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
-# BAP ODE E21XX has 2GB ram soldered down on the Q7
+# BAP ODE E21XX has 2GB RAM soldered down on the Q7
 # Memory setting for DDR-800
 
 #	0 Number of SPD Bytes used / Total SPD Size / CRC Coverage

src/mainboard/bap/ode_e21XX/Makefile.inc

@@ -27,7 +27,7 @@ SPD_SOURCES  = BAP_Q7_800 BAP_Q7_1066 BAP_Q7_1333
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \

src/mainboard/emulation/qemu-armv7/media.c

@@ -14,7 +14,7 @@
  */
 #include <boot_device.h>
 
-/* Maps directly to NOR flash up to rom size. */
+/* Maps directly to NOR flash up to ROM size. */
 static const struct mem_region_device boot_dev =
 	MEM_REGION_DEV_RO_INIT((void *)0x0, CONFIG_ROM_SIZE);
 

src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl

@@ -43,7 +43,7 @@ Scope(\_SB) {
         PRS, 256
     }
     Method(PRSC, 0) {
-        // Local5 = active cpu bitmap
+        // Local5 = active CPU bitmap
         Store(PRS, Local5)
         // Local2 = last read byte from bitmap
         Store(Zero, Local2)
@@ -56,7 +56,7 @@ Scope(\_SB) {
                 // Shift down previously read bitmap byte
                 ShiftRight(Local2, 1, Local2)
             } Else {
-                // Read next byte from cpu bitmap
+                // Read next byte from CPU bitmap
                 Store(DerefOf(Index(Local5, ShiftRight(Local0, 3))), Local2)
             }
             // Local3 = active state for this cpu

src/mainboard/emulation/qemu-i440fx/fw_cfg.c

@@ -118,21 +118,21 @@ int fw_cfg_max_cpus(void)
 /* ---------------------------------------------------------------------- */
 
 /*
- * Starting with release 1.7 qemu provides acpi tables via fw_cfg.
+ * Starting with release 1.7 qemu provides ACPI tables via fw_cfg.
  * Main advantage is that new (virtual) hardware which needs acpi
  * support JustWorks[tm] without having to patch & update the firmware
  * (seabios, coreboot, ...) accordingly.
  *
  * Qemu provides a etc/table-loader file with instructions for the
  * firmware:
- *   - A "load" instruction to fetch acpi data from fw_cfg.
+ *   - A "load" instruction to fetch ACPI data from fw_cfg.
  *   - A "pointer" instruction to patch a pointer.  This is needed to
  *     get table-to-table references right, it is basically a
- *     primitive dynamic linker for acpi tables.
+ *     primitive dynamic linker for ACPI tables.
- *   - A "checksum" instruction to generate acpi table checksums.
+ *   - A "checksum" instruction to generate ACPI table checksums.
  *
  * If a etc/table-loader file is found we'll go try loading the acpi
- * tables from fw_cfg, otherwise we'll fallback to the acpi tables
+ * tables from fw_cfg, otherwise we'll fallback to the ACPI tables
  * compiled in.
  */
 
@@ -211,7 +211,7 @@ unsigned long fw_cfg_acpi_tables(unsigned long start)
 	if (rc < 0)
 		return 0;
 
-	printk(BIOS_DEBUG, "QEMU: found acpi tables in fw_cfg.\n");
+	printk(BIOS_DEBUG, "QEMU: found ACPI tables in fw_cfg.\n");
 
 	max = rc / sizeof(*s);
 	s = malloc(rc);
@@ -259,7 +259,7 @@ unsigned long fw_cfg_acpi_tables(unsigned long start)
 
 			default:
 				/*
-				 * Should not happen.  acpi knows 1 and 2 byte ptrs
+				 * Should not happen.  ACPI knows 1 and 2 byte ptrs
 				 * too, but we are operating with 32bit offsets which
 				 * would simply not fit in there ...
 				 */
@@ -293,13 +293,13 @@ unsigned long fw_cfg_acpi_tables(unsigned long start)
 		};
 	}
 
-	printk(BIOS_DEBUG, "QEMU: loaded acpi tables from fw_cfg.\n");
+	printk(BIOS_DEBUG, "QEMU: loaded ACPI tables from fw_cfg.\n");
 	free(s);
 	free(addrs);
 	return ALIGN(current, 16);
 
 err:
-	printk(BIOS_DEBUG, "QEMU: loading acpi tables from fw_cfg failed.\n");
+	printk(BIOS_DEBUG, "QEMU: loading ACPI tables from fw_cfg failed.\n");
 	free(s);
 	free(addrs);
 	return 0;

src/mainboard/emulation/qemu-i440fx/northbridge.c

@@ -72,7 +72,7 @@ static void cpu_pci_domain_read_resources(struct device *dev)
 		fw_cfg_load_file("etc/e820", list);
 		for (i = 0; i < size/sizeof(*list); i++) {
 			switch (list[i].type) {
-			case 1: /* ram */
+			case 1: /* RAM */
 				printk(BIOS_DEBUG, "QEMU: e820/ram: 0x%08llx +0x%08llx\n",
 				       list[i].address, list[i].length);
 				if (list[i].address == 0) {
@@ -135,7 +135,7 @@ static void cpu_pci_domain_read_resources(struct device *dev)
 		 * Reserve the region between top-of-ram and the
 		 * mmconf xbar (ar 0xb0000000), so coreboot doesn't
 		 * place pci bars there.  The region isn't declared as
-		 * pci io window in the acpi tables (\_SB.PCI0._CRS).
+		 * pci io window in the ACPI tables (\_SB.PCI0._CRS).
 		 */
 		res = new_resource(dev, idx++);
 		res->base = tomk * 1024;

src/mainboard/emulation/qemu-power8/mainboard.c

@@ -26,7 +26,7 @@ static void mainboard_enable(device_t dev)
 			;
 	}
 
-	// Where does ram live?
+	// Where does RAM live?
 	ram_resource(dev, 0, 2048, 32768);
 	cbmem_recovery(0);
 }

src/mainboard/getac/p470/cmos.layout

@@ -72,7 +72,7 @@ entries
 984         16       h       0        check_sum
 #1000        24       r       0        amd_reserved
 
-# ram initialization internal data
+# RAM initialization internal data
 1024         8       r       0        C0WL0REOST
 1032         8       r       0        C1WL0REOST
 1040         8       r       0        RCVENMT

src/mainboard/getac/p470/cstates.c

@@ -4,17 +4,17 @@
 
 static acpi_cstate_t cst_entries[] = {
 	{
-		/* acpi C1 / cpu C1 */
+		/* ACPI C1 / CPU C1 */
 		1, 0x01, 1000,
 		{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 }
 	},
 	{
-		/* acpi C2 / cpu C2 */
+		/* ACPI C2 / CPU C2 */
 		2, 0x01,  500,
 		{ ACPI_ADDRESS_SPACE_IO, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 }
 	},
 	{
-		/* acpi C3 / cpu C2 */
+		/* ACPI C3 / CPU C2 */
 		2, 0x11,  250,
 		{ ACPI_ADDRESS_SPACE_IO, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 }
 	},

src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c

@@ -265,7 +265,7 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
+//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
 		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,

src/mainboard/gigabyte/ga_2761gxdk/romstage.c

@@ -193,5 +193,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
         sis_init_stage2();
-        post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+        post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
 }

src/mainboard/gigabyte/m57sli/resourcemap.c

@@ -265,7 +265,7 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
+//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
 		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,

src/mainboard/gigabyte/m57sli/romstage.c

@@ -199,5 +199,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
-        post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+        post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
 }

src/mainboard/gizmosphere/gizmo/Makefile.inc

@@ -37,7 +37,7 @@ SPD_SOURCES  = Elpida_EDJ2116DEBG
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \

src/mainboard/gizmosphere/gizmo/buildOpts.c

@@ -32,13 +32,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/*	Select the cpu family.	*/
+/*	Select the CPU family.	*/
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT TRUE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*	Select the cpu socket type.	*/
+/*	Select the CPU socket type.	*/
 #define INSTALL_G34_SOCKET_SUPPORT	FALSE
 #define INSTALL_C32_SOCKET_SUPPORT	FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE

src/mainboard/gizmosphere/gizmo2/Makefile.inc

@@ -30,7 +30,7 @@ SPD_SOURCES  = Micron_MT41J128M16JT
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \

src/mainboard/google/auron/spd/Makefile.inc

@@ -29,7 +29,7 @@ SPD_SOURCES += empty                    # 0b0111
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \

src/mainboard/google/auron_paine/spd/Makefile.inc

@@ -42,7 +42,7 @@ SPD_SOURCES += empty                    # 0b1111
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.xxd)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do xxd -rg1 $$f; \

src/mainboard/google/chell/spd/Makefile.inc

@@ -28,7 +28,7 @@ SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF     # 0b0101
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \

src/mainboard/google/cyan/spd/Makefile.inc

@@ -25,7 +25,7 @@ SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \

src/mainboard/google/falco/Makefile.inc

@@ -36,7 +36,7 @@ SPD_SOURCES += Samsung_M471B5674QH0   # 2GB / CH0 only  (RAM_ID=111)
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \

src/mainboard/google/glados/spd/Makefile.inc

@@ -26,7 +26,7 @@ SPD_SOURCES += hynix_dimm_H9CCNNNBLTALAR        # 0b0011
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \

src/mainboard/google/lars/spd/Makefile.inc

@@ -38,7 +38,7 @@ SPD_SOURCES += empty                                    # 0b1111
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \

src/mainboard/google/link/Makefile.inc

@@ -31,7 +31,7 @@ SPD_SOURCES += micron_4Gb_1600_1.35v_x16
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \

src/mainboard/google/ninja/spd/Makefile.inc

@@ -36,7 +36,7 @@ SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \

src/mainboard/google/peppy/Makefile.inc

@@ -35,7 +35,7 @@ SPD_SOURCES += Elpida_EDJ4216EFBG	# 6: 2GB / CH0 + CH1
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \

src/mainboard/google/rambi/spd/Makefile.inc

@@ -32,7 +32,7 @@ SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \

src/mainboard/google/samus/spd/Makefile.inc

@@ -37,7 +37,7 @@ SPD_SOURCES += elpida_16        # 0b1111
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \

src/mainboard/hp/dl145_g1/acpi/amd8111.asl

@@ -597,7 +597,7 @@ Device (IDE0) {
 	}
 }
 Device (PMF) {
-	// acpi smbus   it should be 0x00040003 if 8131 present
+	// ACPI smbus   it should be 0x00040003 if 8131 present
 	Method (_ADR, 0, NotSerialized)
 	{
 		Return (DADD(\_SB.PCI0.SBDN, 0x00010003))

src/mainboard/hp/dl145_g1/dsdt.asl

@@ -172,7 +172,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
 			Notify (\_SB.PWRB, 0x02)
 		}
 	}
-	OperationRegion (KSB0, SystemIO, 0x72, 0x02) // CMOS ram (?)
+	OperationRegion (KSB0, SystemIO, 0x72, 0x02) // CMOS RAM (?)
 	Field (KSB0, ByteAcc, NoLock, Preserve) {
 		KSBI,   8, // Index
 		KSBD,   8  // Data

src/mainboard/hp/dl145_g1/fadt.c

@@ -8,7 +8,7 @@
 #include <console/console.h>
 #include <arch/acpi.h>
 
-extern unsigned pm_base; /* pm_base should be set in sb acpi */
+extern unsigned pm_base; /* pm_base should be set in sb ACPI */
 
 void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
 

src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c

@@ -45,13 +45,13 @@
 
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT FALSE
 #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE

src/mainboard/ibase/mb899/cmos.layout

@@ -82,7 +82,7 @@ entries
 984         16       h       0        check_sum
 #1000        24       r       0        amd_reserved
 
-# ram initialization internal data
+# RAM initialization internal data
 1024         8       r       0        C0WL0REOST
 1032         8       r       0        C1WL0REOST
 1040         8       r       0        RCVENMT

src/mainboard/intel/d945gclf/cmos.layout

@@ -68,7 +68,7 @@ entries
 984         16       h       0        check_sum
 #1000        24       r       0        amd_reserved
 
-# ram initialization internal data
+# RAM initialization internal data
 1024         8       r       0        C0WL0REOST
 1032         8       r       0        C1WL0REOST
 1040         8       r       0        RCVENMT

src/mainboard/intel/kunimitsu/spd/Makefile.inc

@@ -38,7 +38,7 @@ SPD_SOURCES += empty                                    # 0b1111
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \

src/mainboard/iwave/iWRainbowG6/cmos.layout

@@ -75,7 +75,7 @@ entries
 984         16       h       0        check_sum
 #1000        24       r       0        amd_reserved
 
-# ram initialization internal data
+# RAM initialization internal data
 1024         8       r       0        C0WL0REOST
 1032         8       r       0        C1WL0REOST
 1040         8       r       0        RCVENMT

src/mainboard/iwill/dk8_htx/acpi/amd8111.asl

@@ -49,7 +49,7 @@
 
             Device (SBC3)
             {
-                /*  acpi smbus   it should be 0x00040003 if 8131 present */
+                /*  ACPI smbus   it should be 0x00040003 if 8131 present */
 		Method (_ADR, 0, NotSerialized)
 		{
 			Return (DADD(\_SB.PCI0.SBDN, 0x00010003))

src/mainboard/iwill/dk8_htx/fadt.c

@@ -7,7 +7,7 @@
 #include <console/console.h>
 #include <arch/acpi.h>
 
-extern unsigned pm_base; /* pm_base should be set in sb acpi */
+extern unsigned pm_base; /* pm_base should be set in sb ACPI */
 
 void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
 

src/mainboard/iwill/dk8_htx/get_bus_conf.c

@@ -64,7 +64,7 @@ static unsigned get_hcid(unsigned i)
 
 	// we may need more way to find out hcid: subsystem id? GPIO read ?
 
-	// we need use id for 1. bus num, 2. mptable, 3. acpi table
+	// we need use id for 1. bus num, 2. mptable, 3. ACPI table
 
 	return id;
 }

src/mainboard/iwill/dk8_htx/romstage.c

@@ -159,5 +159,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         dump_pci_devices();
 #endif
 
-        post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+        post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
 }

src/mainboard/jetway/nf81-t56n-lf/buildOpts.c

@@ -43,13 +43,13 @@
 
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
-/* Select the cpu family. */
+/* Select the CPU family. */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT TRUE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
 #define INSTALL_G34_SOCKET_SUPPORT	FALSE
 #define INSTALL_C32_SOCKET_SUPPORT	FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE

src/mainboard/kontron/986lcd-m/cmos.layout

@@ -85,7 +85,7 @@ entries
 984         16       h       0        check_sum
 #1000        24       r       0        amd_reserved
 
-# ram initialization internal data
+# RAM initialization internal data
 1024         8       r       0        C0WL0REOST
 1032         8       r       0        C1WL0REOST
 1040         8       r       0        RCVENMT

src/mainboard/kontron/kt690/fadt.c

@@ -25,7 +25,7 @@
 #include "southbridge/amd/sb600/sb600.h"
 
 /*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
 /* pm_base should be got from bar2 of rs690. Here I compact ACPI
  * registers into 32 bytes limit.
  * */

src/mainboard/lenovo/g505s/buildOpts.c

@@ -45,13 +45,13 @@
 
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
-/*  Select the cpu family.  */
+/*  Select the CPU family.  */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT FALSE
 #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
 
-/*  Select the cpu socket type.  */
+/*  Select the CPU socket type.  */
 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE

src/mainboard/lenovo/t400/cmos.layout

@@ -87,7 +87,7 @@ entries
 984          16       h       0        check_sum
 #1000        24       r       0        unused
 
-# ram initialization internal data
+# RAM initialization internal data
 1024        128       r       0        read_training_results
 
 # -----------------------------------------------------------------

src/mainboard/lenovo/t400/cstates.c

@@ -19,12 +19,12 @@
 
 static acpi_cstate_t cst_entries[] = {
 	{
-		/* acpi C1 / cpu C1 */
+		/* ACPI C1 / CPU C1 */
 		1, 0x01, 1000,
 		{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 }
 	},
 	{
-		/* acpi C2 / cpu C2 */
+		/* ACPI C2 / CPU C2 */
 		2, 0x01,  500,
 		{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 }
 	},

src/mainboard/lenovo/t60/cmos.layout

@@ -74,7 +74,7 @@ entries
 984         16       h       0        check_sum
 #1000        24       r       0        amd_reserved
 
-# ram initialization internal data
+# RAM initialization internal data
 1024         8       r       0        C0WL0REOST
 1032         8       r       0        C1WL0REOST
 1040         8       r       0        RCVENMT

src/mainboard/lenovo/x200/cmos.layout

@@ -84,7 +84,7 @@ entries
 984          16       h       0        check_sum
 #1000        24       r       0        unused
 
-# ram initialization internal data
+# RAM initialization internal data
 1024        128       r       0        read_training_results
 
 # -----------------------------------------------------------------

src/mainboard/lenovo/x200/cstates.c

@@ -19,12 +19,12 @@
 
 static acpi_cstate_t cst_entries[] = {
 	{
-		/* acpi C1 / cpu C1 */
+		/* ACPI C1 / CPU C1 */
 		1, 0x01, 1000,
 		{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 }
 	},
 	{
-		/* acpi C2 / cpu C2 */
+		/* ACPI C2 / CPU C2 */
 		2, 0x01,  500,
 		{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 }
 	},

src/mainboard/lenovo/x60/cmos.layout

@@ -74,7 +74,7 @@ entries
 984         16       h       0        check_sum
 #1000        24       r       0        amd_reserved
 
-# ram initialization internal data
+# RAM initialization internal data
 1024         8       r       0        C0WL0REOST
 1032         8       r       0        C1WL0REOST
 1040         8       r       0        RCVENMT

src/mainboard/lippert/frontrunner-af/buildOpts.c

@@ -31,13 +31,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/*	Select the cpu family.	*/
+/*	Select the CPU family.	*/
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT TRUE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*	Select the cpu socket type.	*/
+/*	Select the CPU socket type.	*/
 #define INSTALL_G34_SOCKET_SUPPORT	FALSE
 #define INSTALL_C32_SOCKET_SUPPORT	FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE

src/mainboard/lippert/toucan-af/buildOpts.c

@@ -31,13 +31,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/*	Select the cpu family.	*/
+/*	Select the CPU family.	*/
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT TRUE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*	Select the cpu socket type.	*/
+/*	Select the CPU socket type.	*/
 #define INSTALL_G34_SOCKET_SUPPORT	FALSE
 #define INSTALL_C32_SOCKET_SUPPORT	FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE

src/mainboard/msi/ms7260/resourcemap.c

@@ -267,7 +267,7 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
+//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
 		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,

src/mainboard/msi/ms9652_fam10/resourcemap.c

@@ -269,7 +269,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the highest bus number in configuration region i
 		 */
 		/* Verified against board configuration registers after normal proprietary BIOS boot */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,

src/mainboard/nvidia/l1_2pvv/get_bus_conf.c

@@ -79,7 +79,7 @@ static unsigned get_hcid(unsigned i)
 
 	// we may need more way to find out hcid: subsystem id? GPIO read ?
 
-	// we need use id for 1. bus num, 2. mptable, 3. acpi table
+	// we need use id for 1. bus num, 2. mptable, 3. ACPI table
 
 	return id;
 }

src/mainboard/nvidia/l1_2pvv/resourcemap.c

@@ -265,8 +265,8 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */
+//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */
-//		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */
+//		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */
 		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 

src/mainboard/nvidia/l1_2pvv/romstage.c

@@ -185,5 +185,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
-	post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+	post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
 }

src/mainboard/pcengines/apu1/Makefile.inc

@@ -39,7 +39,7 @@ SPD_SOURCES  = HYNIX-H5TQ2G83CFR HYNIX-H5TQ4G83MFR
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
 
-# Include spd rom data
+# Include spd ROM data
 $(SPD_BIN): $(SPD_DEPS)
 	for f in $+; \
 	  do for c in $$(cat $$f | grep -v ^#); \

src/mainboard/pcengines/apu1/buildOpts.c

@@ -30,13 +30,13 @@
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/*	Select the cpu family.	*/
+/*	Select the CPU family.	*/
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT TRUE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*	Select the cpu socket type.	*/
+/*	Select the CPU socket type.	*/
 #define INSTALL_G34_SOCKET_SUPPORT	FALSE
 #define INSTALL_C32_SOCKET_SUPPORT	FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE

src/mainboard/roda/rk886ex/cmos.layout

@@ -72,7 +72,7 @@ entries
 984         16       h       0        check_sum
 #1000        24       r       0        amd_reserved
 
-# ram initialization internal data
+# RAM initialization internal data
 1024         8       r       0        C0WL0REOST
 1032         8       r       0        C1WL0REOST
 1040         8       r       0        RCVENMT