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util/inteltool: Add support for Tiger Lake chips detection and GPIOs

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Add PCI IDs for Tiger Lake LP and Tiger Lake H devices and their GPIO
tables.

TEST: dump GPIOs on i5-1135G7, Tiger Lake H untested

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6071a999be9e8a372997db0369218f297e579d08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Michał Żygowski
2021-07-09 16:00:16 +02:00
committed by Michael Niewöhner
parent 0de0254a1f
commit 8ac40f3ea7
6 changed files with 1503 additions and 0 deletions
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30
util/inteltool/inteltool.h
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@ -149,6 +149,11 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM 0x9d84
#define PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM 0x0284
#define PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE 0x0285
#define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER 0xa081
#define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM 0xa082
#define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE 0xa083
#define PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER 0xa086
#define PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM 0xa087
#define PCI_DEVICE_ID_INTEL_H110 0xa143
#define PCI_DEVICE_ID_INTEL_H170 0xa144
#define PCI_DEVICE_ID_INTEL_Z170 0xa145
@ -206,6 +211,18 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_HM370 0xa30d
#define PCI_DEVICE_ID_INTEL_CM246 0xa30e
#define PCI_DEVICE_ID_INTEL_Q570 0x4384
#define PCI_DEVICE_ID_INTEL_Z590 0x4385
#define PCI_DEVICE_ID_INTEL_H570 0x4386
#define PCI_DEVICE_ID_INTEL_B560 0x4387
#define PCI_DEVICE_ID_INTEL_H510 0x4388
#define PCI_DEVICE_ID_INTEL_WM590 0x4389
#define PCI_DEVICE_ID_INTEL_QM580 0x438a
#define PCI_DEVICE_ID_INTEL_HM570 0x438b
#define PCI_DEVICE_ID_INTEL_C252 0x438c
#define PCI_DEVICE_ID_INTEL_C256 0x438d
#define PCI_DEVICE_ID_INTEL_W580 0x438f
#define PCI_DEVICE_ID_INTEL_82810 0x7120
#define PCI_DEVICE_ID_INTEL_82810_DC 0x7122
#define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124
@ -310,6 +327,13 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_CORE_CML_U1 0x9b51 /* Cometlake U (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_CML_U2 0x9b61 /* Cometlake U (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_CML_U3 0x9b71 /* Cometlake U (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_2 0x9a04 /* Tigerlake UP3 2 Cores */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_4 0x9a14 /* Tigerlake UP3 4 Cores */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_2 0x9a02 /* Tigerlake UP4 2 Cores */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_4 0x9a12 /* Tigerlake UP4 4 Cores */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_4 0x9a16 /* Tigerlake H 4 Cores */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_6 0x9a26 /* Tigerlake H 6 Cores */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_8 0x9a36 /* Tigerlake H 8 Cores */
#define PCI_DEVICE_ID_INTEL_HEWITTLAKE 0x6f00 /* Hewitt Lake */
#define PCI_DEVICE_ID_INTEL_SAPPHIRERAPIDS_SP 0x09a2 /* Sapphire Rapids SP */
@ -382,6 +406,12 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_IRIS_PLUS_655 0x3EA5
#define PCI_DEVICE_ID_INTEL_IRIS_PLUS_G7 0x8A52
#define PCI_DEVICE_ID_INTEL_UHD_GRAPHICS 0x9b41
#define PCI_DEVICE_ID_INTEL_TGL_GT2_Y 0x9A40
#define PCI_DEVICE_ID_INTEL_TGL_GT2_UY 0x9A49
#define PCI_DEVICE_ID_INTEL_TGL_GT1 0x9A60
#define PCI_DEVICE_ID_INTEL_TGL_GT1_2 0x9A68
#define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_1 0x9A78
#define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_2 0x9A70
#if !defined(__DARWIN__) && !defined(__FreeBSD__)
typedef struct { uint32_t hi, lo; } msr_t;