Initial AMD Barcelona support for rev Bx.
These are the core files for HyperTransport, DDR2 Memory, and multi-core initialization. Signed-off-by: Marc Jones <marc.jones@amd.com> Reviewed-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Myles Watson <myles@pel.cs.byu.edu> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marc Jones
20
src/cpu/amd/quadcore/Config.lb
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20
src/cpu/amd/quadcore/Config.lb
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#
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# This file is part of the LinuxBIOS project.
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#
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# Copyright (C) 2007 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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object amd_sibling.o
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122
src/cpu/amd/quadcore/amd_sibling.c
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122
src/cpu/amd/quadcore/amd_sibling.c
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/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/lapic.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <pc80/mc146818rtc.h>
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#include <smp/spinlock.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/model_10xxx_msr.h>
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#include <cpu/amd/model_10xxx_rev.h>
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#include <cpu/amd/amdfam10_sysconf.h>
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extern device_t get_node_pci(u32 nodeid, u32 fn);
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#if 0
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static int first_time = 1;
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#endif
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#include "quadcore_id.c"
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static u32 get_max_siblings(u32 nodes)
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{
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device_t dev;
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u32 nodeid;
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u32 siblings=0;
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//get max siblings from all the nodes
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for(nodeid=0; nodeid<nodes; nodeid++){
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int j;
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dev = get_node_pci(nodeid, 3);
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j = (pci_read_config32(dev, 0xe8) >> 12) & 3;
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if(siblings < j) {
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siblings = j;
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}
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}
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return siblings;
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}
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static void enable_apic_ext_id(u32 nodes)
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{
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device_t dev;
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u32 nodeid;
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//enable APIC_EXIT_ID all the nodes
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for(nodeid=0; nodeid<nodes; nodeid++){
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u32 val;
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dev = get_node_pci(nodeid, 0);
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val = pci_read_config32(dev, 0x68);
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val |= (1<<17)|(1<<18);
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pci_write_config32(dev, 0x68, val);
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}
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}
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u32 get_apicid_base(u32 ioapic_num)
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{
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u32 apicid_base;
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u32 siblings;
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u32 nb_cfg_54;
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u32 disable_siblings = !CONFIG_LOGICAL_CPUS;
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get_option(&disable_siblings, "quad_core");
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siblings = get_max_siblings(sysconf.nodes);
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if(sysconf.bsp_apicid > 0) { // io apic could start from 0
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return 0;
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} else if (sysconf.enabled_apic_ext_id) { // enabled ext id but bsp = 0
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return 1;
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}
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nb_cfg_54 = read_nb_cfg_54();
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//contruct apicid_base
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if((!disable_siblings) && (siblings>0) ) {
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/* for 8 way dual core, we will used up apicid 16:16, actualy
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16 is not allowed by current kernel and the kernel will try
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to get one that is small than 16 to make io apic work. I don't
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know when the kernel can support 256 apic id.
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(APIC_EXT_ID is enabled) */
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//4:10 for two way 8:12 for four way 16:16 for eight way
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//Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes for better consistency?
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apicid_base = nb_cfg_54 ? (siblings+1) * sysconf.nodes : 8 * siblings + sysconf.nodes;
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} else {
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apicid_base = sysconf.nodes;
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}
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if((apicid_base+ioapic_num-1)>0xf) {
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// We need to enable APIC EXT ID
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printk_spew("if the IO APIC device doesn't support 256 apic id, \r\n you need to set ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\r\n");
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enable_apic_ext_id(sysconf.nodes);
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}
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return apicid_base;
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}
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102
src/cpu/amd/quadcore/quadcore.c
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102
src/cpu/amd/quadcore/quadcore.c
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/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef SET_NB_CFG_54
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#define SET_NB_CFG_54 1
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#endif
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#include "cpu/amd/quadcore/quadcore_id.c"
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static inline u32 get_core_num_in_bsp(u32 nodeid)
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{
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u32 dword;
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dword = pci_read_config32(NODE_PCI(nodeid, 3), 0xe8);
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dword >>= 12;
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dword &= 3;
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return dword;
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}
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#if SET_NB_CFG_54 == 1
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static inline u8 set_apicid_cpuid_lo(void)
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{
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// set the NB_CFG[54]=1; why the OS will be happy with that ???
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msr_t msr;
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msr = rdmsr(NB_CFG_MSR);
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msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo
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wrmsr(NB_CFG_MSR, msr);
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return 1;
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}
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#else
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static inline void set_apicid_cpuid_lo(void) { }
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#endif
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static inline void real_start_other_core(u32 nodeid, u32 cores)
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{
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u32 dword;
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printk_debug("Start other core - nodeid: %02x cores: %02x\n", nodeid, cores);
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/* set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4
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accesses and error logging to core0 */
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dword = pci_read_config32(NODE_PCI(nodeid, 3), 0x44);
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dword |= 1 << 27; // NbMcaToMstCpuEn bit
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pci_write_config32(NODE_PCI(nodeid, 3), 0x44, dword);
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// set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1
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dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x68);
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dword |= 1 << 5;
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pci_write_config32(NODE_PCI(nodeid, 0), 0x68, dword);
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if(cores > 1) {
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dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x168);
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dword |= (1 << 0); // core2
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if(cores > 2) { // core3
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dword |= (1 << 1);
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}
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pci_write_config32(NODE_PCI(nodeid, 0), 0x168, dword);
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}
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}
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//it is running on core0 of node0
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static inline void start_other_cores(void)
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{
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u32 nodes;
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u32 nodeid;
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// disable quad_core
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if (read_option(CMOS_VSTART_quad_core, CMOS_VLEN_quad_core, 0) != 0) {
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printk_debug("Skip additional core init\n");
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return;
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}
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nodes = get_nodes();
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for (nodeid = 0; nodeid < nodes; nodeid++) {
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u32 cores = get_core_num_in_bsp(nodeid);
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printk_debug("init node: %02x cores: %02x \n", nodeid, cores);
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if (cores > 0) {
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real_start_other_core(nodeid, cores);
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}
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}
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}
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79
src/cpu/amd/quadcore/quadcore_id.c
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79
src/cpu/amd/quadcore/quadcore_id.c
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@@ -0,0 +1,79 @@
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/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/cpu.h>
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#include <cpu/amd/quadcore.h>
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#ifdef __ROMCC__
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#include <cpu/amd/model_10xxx_msr.h>
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#endif
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//called by bus_cpu_scan too
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u32 read_nb_cfg_54(void)
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{
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msr_t msr;
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msr = rdmsr(NB_CFG_MSR);
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return ( ( msr.hi >> (54-32)) & 1);
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}
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static inline u32 get_initial_apicid(void)
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{
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return ((cpuid_ebx(1) >> 24) & 0xff);
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}
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//called by amd_siblings too
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#define CORE_ID_BIT 2
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#define NODE_ID_BIT 6
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struct node_core_id get_node_core_id(u32 nb_cfg_54)
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{
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struct node_core_id id;
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u32 core_id_bits;
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u32 ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf);
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if(ApicIdCoreIdSize) {
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core_id_bits = ApicIdCoreIdSize;
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} else {
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core_id_bits = CORE_ID_BIT; //quad core
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}
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// get the apicid via cpuid(1) ebx[31:24]
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if( nb_cfg_54) {
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// when NB_CFG[54] is set, nodeid = ebx[31:26], coreid = ebx[25:24]
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id.coreid = (cpuid_ebx(1) >> 24) & 0xff;
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id.nodeid = (id.coreid>>core_id_bits);
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id.coreid &= ((1<<core_id_bits)-1);
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} else {
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// when NB_CFG[54] is clear, nodeid = ebx[29:24], coreid = ebx[31:30]
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id.nodeid = (cpuid_ebx(1) >> 24) & 0xff;
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id.coreid = (id.nodeid>>NODE_ID_BIT);
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id.nodeid &= ((1<<NODE_ID_BIT)-1);
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}
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return id;
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}
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static inline u32 get_core_num(void)
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{
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return (cpuid_ecx(0x80000008) & 0xff);
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}
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static inline struct node_core_id get_node_core_id_x(void) {
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return get_node_core_id( read_nb_cfg_54() );
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}
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