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Initial AMD Barcelona support for rev Bx.

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These are the core files for HyperTransport, DDR2 Memory, and multi-core initialization.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marc Jones
2007-12-19 01:32:08 +00:00
parent 2006b38fed
commit 8ae8c88220
90 changed files with 27619 additions and 33 deletions
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73
src/include/cpu/amd/amdfam10_sysconf.h Normal file
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/*
* This file is part of the LinuxBIOS project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef AMDFAM10_SYSCONF_H
#define AMDFAM10_SYSCONF_H
#include "../../../northbridge/amd/amdfam10/amdfam10_nums.h"
#include <cpu/x86/msr.h>
struct p_state_t {
unsigned corefreq;
unsigned power;
unsigned transition_lat;
unsigned busmaster_lat;
unsigned control;
unsigned status;
};
struct amdfam10_sysconf_t {
//ht
unsigned hc_possible_num;
unsigned pci1234[HC_POSSIBLE_NUM];
unsigned hcdn[HC_POSSIBLE_NUM];
unsigned hcid[HC_POSSIBLE_NUM]; //record ht chain type
unsigned sbdn;
unsigned sblk;
unsigned nodes;
unsigned ht_c_num; // we only can have 32 ht chain at most
unsigned ht_c_conf_bus[HC_NUMS]; // 4-->32: 4:segn, 8:bus_max, 8:bus_min, 4:linkn, 6: nodeid, 2: enable
unsigned io_addr_num;
unsigned conf_io_addr[HC_NUMS];
unsigned conf_io_addrx[HC_NUMS];
unsigned mmio_addr_num;
unsigned conf_mmio_addr[HC_NUMS*2]; // mem and pref mem
unsigned conf_mmio_addrx[HC_NUMS*2];
unsigned segbit;
unsigned hcdn_reg[HC_NUMS]; // it will be used by get_pci1234
msr_t msr_pstate[NODE_NUMS * 5]; // quad cores all cores in one node should be the same, and p0,..p5
unsigned needs_update_pstate_msrs;
struct p_state_t p_state[NODE_NUMS * 5];
unsigned p_state_num;
unsigned bsp_apicid;
int enabled_apic_ext_id;
unsigned lift_bsp_apicid;
int apicid_offset;
void *mb; // pointer for mb releated struct
};
extern struct amdfam10_sysconf_t sysconf;
#endif

35
src/include/cpu/amd/model_10xxx_msr.h Normal file
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/*
* This file is part of the LinuxBIOS project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef CPU_AMD_MODEL_10XXX_MSR_H
#define CPU_AMD_MODEL_10XXX_MSR_H
#define HWCR_MSR 0xC0010015
#define NB_CFG_MSR 0xC001001f
#define LS_CFG_MSR 0xC0011020
#define IC_CFG_MSR 0xC0011021
#define DC_CFG_MSR 0xC0011022
#define BU_CFG_MSR 0xC0011023
#define CPU_ID_FEATURES_MSR 0xC0011004
#define CPU_ID_HYPER_EXT_FEATURES 0xC001100d
#define LOGICAL_CPUS_NUM_MSR 0xC001100d
#define CPU_ID_EXT_FEATURES_MSR 0xC0011005
#endif /* CPU_AMD_MODEL_10XXX_MSR_H */

22
src/include/cpu/amd/model_10xxx_rev.h Normal file
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/*
* This file is part of the LinuxBIOS project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/cpu.h>
/* place holder for Family 10 revision code */

43
src/include/cpu/amd/quadcore.h Normal file
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/*
* This file is part of the LinuxBIOS project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef CPU_AMD_QUADCORE_H
#define CPU_AMD_QUADCORE_H
#if defined(__GNUC__)
unsigned int read_nb_cfg_54(void);
#endif
struct node_core_id {
u32 nodeid;
u32 coreid;
};
#if defined(__GNUC__)
// it can be used to get unitid and coreid it running only
struct node_core_id get_node_core_id(u32 nb_cfg_54);
#endif
#ifndef __ROMCC__
struct device;
u32 get_apicid_base(u32 ioapic_num);
void amd_sibling_init(struct device *cpu);
#endif
#endif /* CPU_AMD_QUADCORE_H */