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nb/intel/gm45: Allocate a 8M TSEG region

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Tested on Thinkpad X200.

Change-Id: I9db7a71608aaec956a7b22649498b97d58f35265
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23418
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
2018-01-24 23:25:13 +01:00
committed by Patrick Georgi
parent a050817ce5
commit 8b76605a4a
4 changed files with 35 additions and 2 deletions
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6
src/northbridge/intel/gm45/raminit.c
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@@ -1242,6 +1242,12 @@ static void program_memory_map(const dimminfo_t *const dimms, const channel_mode
uma_sizem = (gms_sizek + gsm_sizek) >> 10;
}
/* TSEG 8M */
u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
reg8 &= ~0x7;
reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */
pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8);
uma_sizem += 8;
}
const unsigned int mmio_size = get_mmio_size();