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vc/intel/fsp/mtl: Update header files from 3424_88 to 3471.85

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Update header files for FSP for Meteor Lake platform to version 3471_85,
previous version being 3424_88.

FSPM:
1. Add 'DisplayGpioPinMux' UPDs
2. Address offset changes

BUG=b:318772151
TEST=Able to build and boot google/rex to ChromeOS.

Change-Id: I11c39fc2e3099d93a488e71d571ac1af02345fbd
Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79829
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Kulkarni, Srinivas
2024-01-05 10:52:10 +05:30
committed by Subrata Banik
parent 2d6b4c84a4
commit 8b89f89ecb
1 changed files with 9 additions and 2 deletions
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11
src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
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@@ -926,9 +926,16 @@ typedef struct {
**/ **/
UINT8 DdiPort4Ddc; UINT8 DdiPort4Ddc;
/** Offset 0x02BE - Reserved /** Offset 0x02BE - GPIO PIN MUX to choose between GPP_SA and GPP_SD Group.
Default will be 0 for each Display PIN Mux which is GPP_SA Group. (0 = SA GROUP,
1 = SD GROUP). BIT0 - EDP VDDEN, BIT1 - EDP BKLTEN, BIT2 - EDP BKLTCTRL, BIT3
- DDI-A, BIT4 - DDI-1/HPD1, BIT5 - DDI-2/HPD2, BIT6 - DDI-3/HPD3, BIT7 - DDI-4/HPD4
**/ **/
UINT8 Reserved16[18]; UINT8 DisplayGpioPinMux;
/** Offset 0x02BF - Reserved
**/
UINT8 Reserved16[17];
/** Offset 0x02D0 - Per-core HT Disable /** Offset 0x02D0 - Per-core HT Disable
Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, Defines the per-core HT disable mask where: 1 - Disable selected logical core HT,