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cpu/x86: Fix various issues detected by checkpatch.pl

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Fix the following errors and warning detected by checkpatch.pl:

ERROR: spaces required around that '=' (ctx:VxV)
ERROR: space prohibited after that open parenthesis '('
ERROR: need consistent spacing around '|' (ctx:WxV)
ERROR: need consistent spacing around '|' (ctx:VxW)
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: spaces required around that '==' (ctx:VxV)
ERROR: spaces required around that ':' (ctx:ExV)
WARNING: space prohibited between function name and open parenthesis '('

TEST=Build and run on Galileo Gen2

Change-Id: I61d08055b207c607d5b7d72b0094ad8e24fbd106
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18840
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy
2017-03-15 14:15:38 -07:00
parent 5f94541329
commit 8bad6d2f90
7 changed files with 14 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/cpu/x86/car.c
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@ -62,7 +62,7 @@ void *car_get_var_ptr(void *var)
} }
#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0) #if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0)
migrated_base=(char *)find_saved_temp_mem( migrated_base = (char *)find_saved_temp_mem(
*(void **)CBMEM_FSP_HOB_PTR); *(void **)CBMEM_FSP_HOB_PTR);
/* FSP 1.0 migrates the entire DCACHE RAM */ /* FSP 1.0 migrates the entire DCACHE RAM */
offset = (char *)var - (char *)CONFIG_DCACHE_RAM_BASE; offset = (char *)var - (char *)CONFIG_DCACHE_RAM_BASE;
@ -72,7 +72,7 @@ void *car_get_var_ptr(void *var)
#endif #endif
if (migrated_base == NULL) if (migrated_base == NULL)
die( "CAR: Could not find migration base!\n"); die("CAR: Could not find migration base!\n");
return &migrated_base[offset]; return &migrated_base[offset];
} }

8
src/cpu/x86/lapic/lapic.c
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@ -53,18 +53,18 @@ void setup_lapic(void)
(lapic_read_around(LAPIC_LVT0) & (lapic_read_around(LAPIC_LVT0) &
~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY | LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
LAPIC_SEND_PENDING |LAPIC_LVT_RESERVED_1 | LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
LAPIC_DELIVERY_MODE_MASK)) LAPIC_DELIVERY_MODE_MASK))
| (LAPIC_LVT_REMOTE_IRR |LAPIC_SEND_PENDING | | (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
LAPIC_DELIVERY_MODE_EXTINT) LAPIC_DELIVERY_MODE_EXTINT)
); );
lapic_write_around(LAPIC_LVT1, lapic_write_around(LAPIC_LVT1,
(lapic_read_around(LAPIC_LVT1) & (lapic_read_around(LAPIC_LVT1) &
~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY | LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
LAPIC_SEND_PENDING |LAPIC_LVT_RESERVED_1 | LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
LAPIC_DELIVERY_MODE_MASK)) LAPIC_DELIVERY_MODE_MASK))
| (LAPIC_LVT_REMOTE_IRR |LAPIC_SEND_PENDING | | (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
LAPIC_DELIVERY_MODE_NMI) LAPIC_DELIVERY_MODE_NMI)
); );

2
src/cpu/x86/lapic/lapic_cpu_init.c
View File

@ -441,7 +441,7 @@ static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu)
continue; continue;
} }
if (IS_ENABLED(CONFIG_PARALLEL_CPU_INIT) && (cpu==bsp_cpu)) if (IS_ENABLED(CONFIG_PARALLEL_CPU_INIT) && (cpu == bsp_cpu))
continue; continue;
if (!cpu->enabled) { if (!cpu->enabled) {

2
src/cpu/x86/pae/pgtbl.c
View File

@ -90,7 +90,7 @@ void *map_2M_page(unsigned long page)
pdp[3].addr_lo = ((uint32_t)&pd[512*3])|1; pdp[3].addr_lo = ((uint32_t)&pd[512*3])|1;
/* The first half of the page table is identity mapped */ /* The first half of the page table is identity mapped */
for (i = 0; i < 1024; i++) { for (i = 0; i < 1024; i++) {
pd[i].addr_lo = ((i & 0x3ff) << 21)| 0xE3; pd[i].addr_lo = ((i & 0x3ff) << 21) | 0xE3;
pd[i].addr_hi = 0; pd[i].addr_hi = 0;
} }
/* The second half of the page table holds the mapped page */ /* The second half of the page table holds the mapped page */

5
src/cpu/x86/smm/smihandler.c
View File

@ -28,7 +28,8 @@ static int do_driver_init = 1;
typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore; typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore;
/* SMI multiprocessing semaphore */ /* SMI multiprocessing semaphore */
static volatile smi_semaphore smi_handler_status __attribute__ ((aligned (4))) = SMI_UNLOCKED; static __attribute__ ((aligned(4))) volatile smi_semaphore smi_handler_status
= SMI_UNLOCKED;
static int smi_obtain_lock(void) static int smi_obtain_lock(void)
{ {
@ -138,7 +139,7 @@ void smi_handler(u32 smm_revision)
smi_backup_pci_address(); smi_backup_pci_address();
node=nodeid(); node = nodeid();
console_init(); console_init();

2
src/cpu/x86/smm/smm_module_handler.c
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@ -28,7 +28,7 @@ typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore;
/* SMI multiprocessing semaphore */ /* SMI multiprocessing semaphore */
static volatile static volatile
smi_semaphore smi_handler_status __attribute__ ((aligned (4))) = SMI_UNLOCKED; __attribute__ ((aligned(4))) smi_semaphore smi_handler_status = SMI_UNLOCKED;
static int smi_obtain_lock(void) static int smi_obtain_lock(void)
{ {

4
src/cpu/x86/tsc/delay_tsc.c
View File

@ -70,8 +70,8 @@ static unsigned long calibrate_tsc_with_pit(void)
/* 64-bit subtract - gcc just messes up with long longs */ /* 64-bit subtract - gcc just messes up with long longs */
__asm__("subl %2,%0\n\t" __asm__("subl %2,%0\n\t"
"sbbl %3,%1" "sbbl %3,%1"
:"=a" (end.lo), "=d" (end.hi) : "=a" (end.lo), "=d" (end.hi)
:"g" (start.lo), "g" (start.hi), : "g" (start.lo), "g" (start.hi),
"0" (end.lo), "1" (end.hi)); "0" (end.lo), "1" (end.hi));
/* Error: ECPUTOOFAST */ /* Error: ECPUTOOFAST */