drivers/intel/gma/opregion: Use CBFS cache to load VBT

Thanks to x86 CBFS cache support, we can leverage cbfs_map() function
to load the VBT binary regardless of if it is compressed or not.

Change-Id: I1e37e718a71bd85b0d7dee1efc4c0391798f16f7
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

src/drivers/intel/gma/Kconfig

@@ -59,10 +59,6 @@ config INTEL_GMA_SWSMISCI
 config INTEL_GMA_LIBGFXINIT_EDID
 	bool
 
-config VBT_DATA_SIZE_KB
-	int
-	default 8
-
 config VBT_CBFS_COMPRESSION_DEFAULT_LZ4
 	def_bool n
 	help

src/drivers/intel/gma/opregion.c

@@ -19,40 +19,39 @@ const char *mainboard_vbt_filename(void)
 	return "vbt.bin";
 }
 
-static char vbt_data[CONFIG_VBT_DATA_SIZE_KB * KiB];
-static size_t vbt_data_sz;
-
 void *locate_vbt(size_t *vbt_size)
 {
-	uint32_t vbtsig = 0;
+	static void *data;
+	static size_t size;
 
-	if (vbt_data_sz != 0) {
+	if (data)
-		if (vbt_size)
+		goto out;
-			*vbt_size = vbt_data_sz;
+
-		return (void *)vbt_data;
+	data = cbfs_map(mainboard_vbt_filename(), &size);
+	if (!data || size == 0) {
+		printk(BIOS_ERR, "Could not find or load %s CBFS file\n",
+		       mainboard_vbt_filename());
+		goto err;
 	}
 
-	const char *filename = mainboard_vbt_filename();
+	if (*(uint32_t *)data == VBT_SIGNATURE) {
-
+		printk(BIOS_INFO, "Found a VBT of %zu bytes\n", size);
-	size_t file_size = cbfs_load(filename, vbt_data, sizeof(vbt_data));
+		goto out;
-
-	if (file_size == 0)
-		return NULL;
-
-	if (vbt_size)
-		*vbt_size = file_size;
-
-	memcpy(&vbtsig, vbt_data, sizeof(vbtsig));
-	if (vbtsig != VBT_SIGNATURE) {
-		printk(BIOS_ERR, "Missing/invalid signature in VBT data file!\n");
-		return NULL;
 	}
 
-	printk(BIOS_INFO, "Found a VBT of %zu bytes after decompression\n",
+	printk(BIOS_ERR, "Missing/invalid signature in VBT data file!\n");
-		file_size);
-	vbt_data_sz = file_size;
 
-	return (void *)vbt_data;
+err:
+	if (data) {
+		cbfs_unmap(data);
+		data = NULL;
+	}
+	size = 0;
+
+out:
+	if (vbt_size && size)
+		*vbt_size = size;
+	return data;
 }
 
 /* Write ASLS PCI register and prepare SWSCI register. */

src/soc/intel/alderlake/Kconfig

@@ -350,10 +350,6 @@ config CONSOLE_UART_BASE_ADDRESS
 	default 0xfe03e000
 	depends on INTEL_LPSS_UART_FOR_CONSOLE
 
-config VBT_DATA_SIZE_KB
-	int
-	default 9
-
 # Clock divider parameters for 115200 baud rate
 # Baudrate = (UART source clock * M) /(N *16)
 # ADL UART source clock: 100MHz

src/soc/intel/jasperlake/Kconfig

@@ -174,10 +174,6 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
 	hex
 	default 0xc35
 
-config VBT_DATA_SIZE_KB
-	int
-	default 9
-
 config VBOOT
 	select VBOOT_MUST_REQUEST_DISPLAY
 	select VBOOT_STARTS_IN_BOOTBLOCK

src/soc/intel/meteorlake/Kconfig

@@ -301,10 +301,6 @@ config CONSOLE_UART_BASE_ADDRESS
 	default 0xfe02c000
 	depends on INTEL_LPSS_UART_FOR_CONSOLE
 
-config VBT_DATA_SIZE_KB
-	int
-	default 9
-
 # Clock divider parameters for 115200 baud rate
 # Baudrate = (UART source clock * M) /(N *16)
 # MTL UART source clock: 100MHz

src/soc/intel/tigerlake/Kconfig

@@ -222,10 +222,6 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
 	hex
 	default 0x7fff
 
-config VBT_DATA_SIZE_KB
-	int
-	default 9
-
 config VBOOT
 	select VBOOT_MUST_REQUEST_DISPLAY
 	select VBOOT_STARTS_IN_BOOTBLOCK