sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

AGESA fam14: Common agesawrapper

Browse Source 
Use copy of amd/persimmon.

Change-Id: I7404cb164df9065bcdbaaf5367018870ea675adc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7157
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Kyösti Mälkki 2014-10-19 17:54:44 +03:00
parent 923302ae61
commit 8c20a04cae
19 changed files with 205 additions and 4568 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/amd/inagua/Makefile.inc
View File

@ -25,12 +25,10 @@ pci$(stripped_ahcibios_id).rom-type := optionrom
endif endif
romstage-y += buildOpts.c romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += BiosCallOuts.c romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c romstage-y += PlatformGnbPcie.c
ramstage-y += buildOpts.c ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c ramstage-y += PlatformGnbPcie.c

474
src/mainboard/amd/inagua/agesawrapper.c
View File

@ -1,474 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
#include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "cpuRegisters.h"
#include "cpuCacheInit.h"
#include "cpuApicUtilities.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "Dispatcher.h"
#include "cpuCacheInit.h"
#include "amdlib.h"
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
#include <arch/io.h>
#define FILECODE UNASSIGNED_FILE_FILECODE
#define MMCONF_ENABLE 1
/* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
AGESA_STATUS agesawrapper_amdinitcpuio (
VOID
)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
PciData = 1;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
* set to non-posted regions.
*/
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
PciData |= 1 << 7; // set NP (non-posted) bit
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; // last address before non-posted range
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
PciData = 0x0000F000;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
}
AGESA_STATUS agesawrapper_amdinitmmio (
VOID
)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
UINT8 BusRangeVal = 0;
UINT8 BusNum;
UINT8 Index;
/*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
for (Index = 0; Index < 8; Index++) {
BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
if (BusNum == 1) {
BusRangeVal = Index;
break;
}
}
MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE);
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
/*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000ull;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* Set Ontario Link Data */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
PciData = 0x01308002;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
}
AGESA_STATUS agesawrapper_amdinitreset (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost;
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = NULL;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitearly (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr);
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitpost (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
/* Initialize heap space */
EmptyHeap();
return status;
}
AGESA_STATUS agesawrapper_amdinitenv (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
PCI_ADDR PciAddress;
UINT32 PciValue;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
/* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
/* Write to D1F0x18 */
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x00010100;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Legacy Bridge Mode
* Modify B1D5F0x18
*/
PciAddress.Address.Bus = 1;
PciAddress.Address.Device = 5;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Legacy Bridge Mode
* Modify B1D5F0x10
*/
PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Pcie Mode
* Modify B0D1F0x18
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Pcie Mode
* Modify B0D1F0x10
*/
PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Base and Limit Address
* Modify B0D1F0x20
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x20;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96009600;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Prefetchable Memory Limit and Base
* Modify B0D1F0x24
*/
PciAddress.Address.Register = 0x24;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x8FF18001;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
VOID *
agesawrapper_getlateinitptr (
int pick
)
{
switch (pick) {
case PICK_DMI:
return DmiTable;
case PICK_PSTATE:
return AcpiPstate;
case PICK_SRAT:
return AcpiSrat;
case PICK_SLIT:
return AcpiSlit;
case PICK_WHEA_MCE:
return AcpiWheaMce;
case PICK_WHEA_CMC:
return AcpiWheaCmc;
case PICK_ALIB:
return AcpiAlib;
default:
return NULL;
}
}
AGESA_STATUS agesawrapper_amdinitmid (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
/* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio ();
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitlate (
VOID
)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_LATE_PARAMS * AmdLateParamsPtr;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr);
Status = AmdInitLate (AmdLateParamsPtr);
AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS);
DmiTable = AmdLateParamsPtr->DmiTable;
AcpiPstate = AmdLateParamsPtr->AcpiPState;
AcpiSrat = AmdLateParamsPtr->AcpiSrat;
AcpiSlit = AmdLateParamsPtr->AcpiSlit;
AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
AcpiAlib = AmdLateParamsPtr->AcpiAlib;
printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
" DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n"
" Mce:%p\n Cmc:%p\n Alib:%p\n",
__func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
/* Don't release the structure until coreboot has copied the ACPI tables.
* AmdReleaseStruct (&AmdLateParams);
*/
return Status;
}
AGESA_STATUS agesawrapper_amdlaterunaptask (
UINT32 Func,
UINT32 Data,
VOID *ConfigPtr
)
{
AGESA_STATUS Status;
AP_EXE_PARAMS ApExeParams;
memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS));
ApExeParams.StdHeader.AltImageBasePtr = 0;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
ApExeParams.StdHeader.Func = 0;
ApExeParams.StdHeader.ImageBasePtr = 0;
ApExeParams.FunctionNumber = Func;
ApExeParams.RelatedDataBlock = ConfigPtr;
Status = AmdLateRunApTask (&ApExeParams);
AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS);
return Status;
}
AGESA_STATUS agesawrapper_amdreadeventlog (
VOID
)
{
AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams;
memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS));
AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = NULL;
AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0;
Status = AmdReadEventLog (&AmdEventParams);
while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
Status = AmdReadEventLog (&AmdEventParams);
}
return Status;
}

2
src/mainboard/amd/persimmon/Makefile.inc
View File

@ -25,11 +25,9 @@ pci$(stripped_ahcibios_id).rom-type := optionrom
endif endif
romstage-y += buildOpts.c romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += BiosCallOuts.c romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c romstage-y += PlatformGnbPcie.c
ramstage-y += buildOpts.c ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c ramstage-y += PlatformGnbPcie.c

2
src/mainboard/amd/south_station/Makefile.inc
View File

@ -18,11 +18,9 @@
# #
romstage-y += buildOpts.c romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += BiosCallOuts.c romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c romstage-y += PlatformGnbPcie.c
ramstage-y += buildOpts.c ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c ramstage-y += PlatformGnbPcie.c

469
src/mainboard/amd/south_station/agesawrapper.c
View File

@ -1,469 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
#include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "cpuRegisters.h"
#include "cpuCacheInit.h"
#include "cpuApicUtilities.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "Dispatcher.h"
#include "cpuCacheInit.h"
#include "amdlib.h"
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
#include <arch/io.h>
#define FILECODE UNASSIGNED_FILE_FILECODE
#define MMCONF_ENABLE 1
/* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
AGESA_STATUS agesawrapper_amdinitcpuio (
VOID
)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
PciData = 1;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
* set to non-posted regions.
*/
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
PciData |= 1 << 7; // set NP (non-posted) bit
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; // last address before non-posted range
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
PciData = 0x0000F000;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
}
AGESA_STATUS agesawrapper_amdinitmmio (
VOID
)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
UINT8 BusRangeVal = 0;
UINT8 BusNum;
UINT8 Index;
/*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
for (Index = 0; Index < 8; Index++) {
BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
if (BusNum == 1) {
BusRangeVal = Index;
break;
}
}
MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE);
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
/*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000ull;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* Set Ontario Link Data */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
PciData = 0x01308002;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
}
AGESA_STATUS agesawrapper_amdinitreset (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost;
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = NULL;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitearly (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr);
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitpost (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
/* Initialize heap space */
EmptyHeap();
return status;
}
AGESA_STATUS agesawrapper_amdinitenv (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
PCI_ADDR PciAddress;
UINT32 PciValue;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
/* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
/* Write to D1F0x18 */
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x00010100;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Legacy Bridge Mode
* Modify B1D5F0x18
*/
PciAddress.Address.Bus = 1;
PciAddress.Address.Device = 5;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Legacy Bridge Mode
* Modify B1D5F0x10
*/
PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Pcie Mode
* Modify B0D1F0x18
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Pcie Mode
* Modify B0D1F0x10
*/
PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Base and Limit Address
* Modify B0D1F0x20
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x20;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96009600;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Prefetchable Memory Limit and Base
* Modify B0D1F0x24
*/
PciAddress.Address.Register = 0x24;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x8FF18001;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
VOID *
agesawrapper_getlateinitptr (
int pick
)
{
switch (pick) {
case PICK_DMI:
return DmiTable;
case PICK_PSTATE:
return AcpiPstate;
case PICK_SRAT:
return AcpiSrat;
case PICK_SLIT:
return AcpiSlit;
case PICK_WHEA_MCE:
return AcpiWheaMce;
case PICK_WHEA_CMC:
return AcpiWheaCmc;
case PICK_ALIB:
return AcpiAlib;
default:
return NULL;
}
}
AGESA_STATUS agesawrapper_amdinitmid (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
/* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio ();
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitlate (
VOID
)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_LATE_PARAMS * AmdLateParamsPtr;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr);
Status = AmdInitLate (AmdLateParamsPtr);
AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS);
DmiTable = AmdLateParamsPtr->DmiTable;
AcpiPstate = AmdLateParamsPtr->AcpiPState;
AcpiSrat = AmdLateParamsPtr->AcpiSrat;
AcpiSlit = AmdLateParamsPtr->AcpiSlit;
AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
AcpiAlib = AmdLateParamsPtr->AcpiAlib;
/* Don't release the structure until coreboot has copied the ACPI tables.
* AmdReleaseStruct (&AmdLateParams);
*/
return Status;
}
AGESA_STATUS agesawrapper_amdlaterunaptask (
UINT32 Func,
UINT32 Data,
VOID *ConfigPtr
)
{
AGESA_STATUS Status;
AP_EXE_PARAMS ApExeParams;
memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS));
ApExeParams.StdHeader.AltImageBasePtr = 0;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
ApExeParams.StdHeader.Func = 0;
ApExeParams.StdHeader.ImageBasePtr = 0;
ApExeParams.FunctionNumber = Func;
ApExeParams.RelatedDataBlock = ConfigPtr;
Status = AmdLateRunApTask (&ApExeParams);
AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS);
return Status;
}
AGESA_STATUS agesawrapper_amdreadeventlog (
VOID
)
{
AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams;
memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS));
AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = NULL;
AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0;
Status = AmdReadEventLog (&AmdEventParams);
while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
Status = AmdReadEventLog (&AmdEventParams);
}
return Status;
}

2
src/mainboard/amd/union_station/Makefile.inc
View File

@ -18,11 +18,9 @@
# #
romstage-y += buildOpts.c romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += BiosCallOuts.c romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c romstage-y += PlatformGnbPcie.c
ramstage-y += buildOpts.c ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c ramstage-y += PlatformGnbPcie.c

469
src/mainboard/amd/union_station/agesawrapper.c
View File

@ -1,469 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
#include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "cpuRegisters.h"
#include "cpuCacheInit.h"
#include "cpuApicUtilities.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "Dispatcher.h"
#include "cpuCacheInit.h"
#include "amdlib.h"
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
#include <arch/io.h>
#define FILECODE UNASSIGNED_FILE_FILECODE
#define MMCONF_ENABLE 1
/* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
AGESA_STATUS agesawrapper_amdinitcpuio (
VOID
)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
PciData = 1;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
* set to non-posted regions.
*/
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
PciData |= 1 << 7; // set NP (non-posted) bit
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; // last address before non-posted range
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
PciData = 0x0000F000;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
}
AGESA_STATUS agesawrapper_amdinitmmio (
VOID
)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
UINT8 BusRangeVal = 0;
UINT8 BusNum;
UINT8 Index;
/*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
for (Index = 0; Index < 8; Index++) {
BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
if (BusNum == 1) {
BusRangeVal = Index;
break;
}
}
MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE);
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
/*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000ull;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* Set Ontario Link Data */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
PciData = 0x01308002;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
}
AGESA_STATUS agesawrapper_amdinitreset (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost;
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = NULL;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitearly (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr);
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitpost (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
/* Initialize heap space */
EmptyHeap();
return status;
}
AGESA_STATUS agesawrapper_amdinitenv (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
PCI_ADDR PciAddress;
UINT32 PciValue;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
/* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
/* Write to D1F0x18 */
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x00010100;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Legacy Bridge Mode
* Modify B1D5F0x18
*/
PciAddress.Address.Bus = 1;
PciAddress.Address.Device = 5;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Legacy Bridge Mode
* Modify B1D5F0x10
*/
PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Pcie Mode
* Modify B0D1F0x18
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Pcie Mode
* Modify B0D1F0x10
*/
PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Base and Limit Address
* Modify B0D1F0x20
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x20;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96009600;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Prefetchable Memory Limit and Base
* Modify B0D1F0x24
*/
PciAddress.Address.Register = 0x24;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x8FF18001;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
VOID *
agesawrapper_getlateinitptr (
int pick
)
{
switch (pick) {
case PICK_DMI:
return DmiTable;
case PICK_PSTATE:
return AcpiPstate;
case PICK_SRAT:
return AcpiSrat;
case PICK_SLIT:
return AcpiSlit;
case PICK_WHEA_MCE:
return AcpiWheaMce;
case PICK_WHEA_CMC:
return AcpiWheaCmc;
case PICK_ALIB:
return AcpiAlib;
default:
return NULL;
}
}
AGESA_STATUS agesawrapper_amdinitmid (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
/* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio ();
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitlate (
VOID
)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_LATE_PARAMS * AmdLateParamsPtr;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr);
Status = AmdInitLate (AmdLateParamsPtr);
AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS);
DmiTable = AmdLateParamsPtr->DmiTable;
AcpiPstate = AmdLateParamsPtr->AcpiPState;
AcpiSrat = AmdLateParamsPtr->AcpiSrat;
AcpiSlit = AmdLateParamsPtr->AcpiSlit;
AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
AcpiAlib = AmdLateParamsPtr->AcpiAlib;
/* Don't release the structure until coreboot has copied the ACPI tables.
* AmdReleaseStruct (&AmdLateParams);
*/
return Status;
}
AGESA_STATUS agesawrapper_amdlaterunaptask (
UINT32 Func,
UINT32 Data,
VOID *ConfigPtr
)
{
AGESA_STATUS Status;
AP_EXE_PARAMS ApExeParams;
memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS));
ApExeParams.StdHeader.AltImageBasePtr = 0;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
ApExeParams.StdHeader.Func = 0;
ApExeParams.StdHeader.ImageBasePtr = 0;
ApExeParams.FunctionNumber = Func;
ApExeParams.RelatedDataBlock = ConfigPtr;
Status = AmdLateRunApTask (&ApExeParams);
AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS);
return Status;
}
AGESA_STATUS agesawrapper_amdreadeventlog (
VOID
)
{
AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams;
memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS));
AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = NULL;
AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0;
Status = AmdReadEventLog (&AmdEventParams);
while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
Status = AmdReadEventLog (&AmdEventParams);
}
return Status;
}

2
src/mainboard/asrock/e350m1/Makefile.inc
View File

@ -18,11 +18,9 @@
# #
romstage-y += buildOpts.c romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += BiosCallOuts.c romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c romstage-y += PlatformGnbPcie.c
ramstage-y += buildOpts.c ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c ramstage-y += PlatformGnbPcie.c

498
src/mainboard/asrock/e350m1/agesawrapper.c
View File

@ -1,498 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*-----------------------------------------------------------------------------
* M O D U L E S U S E D
*-----------------------------------------------------------------------------
*/
#include <stdint.h>
#include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "cpuRegisters.h"
#include "cpuCacheInit.h"
#include "cpuApicUtilities.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "Dispatcher.h"
#include "cpuCacheInit.h"
#include "amdlib.h"
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
#include <arch/io.h>
#define FILECODE UNASSIGNED_FILE_FILECODE
/*------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*------------------------------------------------------------------------------
*/
#define MMCONF_ENABLE 1
/* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
/*------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*------------------------------------------------------------------------------
*/
/*------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*------------------------------------------------------------------------------
*/
/*------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*------------------------------------------------------------------------------
*/
/*------------------------------------------------------------------------------
* L O C A L F U N C T I O N S
*------------------------------------------------------------------------------
*/
AGESA_STATUS agesawrapper_amdinitcpuio (
VOID
)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
PciData = 1;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
* set to non-posted regions.
*/
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
PciData |= 1 << 7; // set NP (non-posted) bit
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; // last address before non-posted range
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
PciData = 0x0000F000;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
}
AGESA_STATUS agesawrapper_amdinitmmio (
VOID
)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
UINT8 BusRangeVal = 0;
UINT8 BusNum;
UINT8 Index;
/*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
for (Index = 0; Index < 8; Index++) {
BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
if (BusNum == 1) {
BusRangeVal = Index;
break;
}
}
MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE);
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
/*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000ull;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* Set Ontario Link Data */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
PciData = 0x01308002;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
}
AGESA_STATUS agesawrapper_amdinitreset (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost;
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = NULL;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitearly (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr);
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitpost (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
/* Initialize heap space */
EmptyHeap();
return status;
}
AGESA_STATUS agesawrapper_amdinitenv (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
PCI_ADDR PciAddress;
UINT32 PciValue;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
/* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
/* Write to D1F0x18 */
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x00010100;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Legacy Bridge Mode
* Modify B1D5F0x18
*/
PciAddress.Address.Bus = 1;
PciAddress.Address.Device = 5;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Legacy Bridge Mode
* Modify B1D5F0x10
*/
PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Pcie Mode
* Modify B0D1F0x18
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Pcie Mode
* Modify B0D1F0x10
*/
PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Base and Limit Address
* Modify B0D1F0x20
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x20;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96009600;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Prefetchable Memory Limit and Base
* Modify B0D1F0x24
*/
PciAddress.Address.Register = 0x24;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x8FF18001;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
VOID *
agesawrapper_getlateinitptr (
int pick
)
{
switch (pick) {
case PICK_DMI:
return DmiTable;
case PICK_PSTATE:
return AcpiPstate;
case PICK_SRAT:
return AcpiSrat;
case PICK_SLIT:
return AcpiSlit;
case PICK_WHEA_MCE:
return AcpiWheaMce;
case PICK_WHEA_CMC:
return AcpiWheaCmc;
case PICK_ALIB:
return AcpiAlib;
default:
return NULL;
}
}
AGESA_STATUS agesawrapper_amdinitmid (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
/* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio ();
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitlate (
VOID
)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_LATE_PARAMS * AmdLateParamsPtr;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr);
Status = AmdInitLate (AmdLateParamsPtr);
AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS);
DmiTable = AmdLateParamsPtr->DmiTable;
AcpiPstate = AmdLateParamsPtr->AcpiPState;
AcpiSrat = AmdLateParamsPtr->AcpiSrat;
AcpiSlit = AmdLateParamsPtr->AcpiSlit;
AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
AcpiAlib = AmdLateParamsPtr->AcpiAlib;
/* Don't release the structure until coreboot has copied the ACPI tables.
* AmdReleaseStruct (&AmdLateParams);
*/
return Status;
}
AGESA_STATUS agesawrapper_amdlaterunaptask (
UINT32 Func,
UINT32 Data,
VOID *ConfigPtr
)
{
AGESA_STATUS Status;
AP_EXE_PARAMS ApExeParams;
memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS));
ApExeParams.StdHeader.AltImageBasePtr = 0;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
ApExeParams.StdHeader.Func = 0;
ApExeParams.StdHeader.ImageBasePtr = 0;
ApExeParams.FunctionNumber = Func;
ApExeParams.RelatedDataBlock = ConfigPtr;
Status = AmdLateRunApTask (&ApExeParams);
AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS);
return Status;
}
AGESA_STATUS agesawrapper_amdreadeventlog (
VOID
)
{
AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams;
memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS));
AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = NULL;
AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0;
Status = AmdReadEventLog (&AmdEventParams);
while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
Status = AmdReadEventLog (&AmdEventParams);
}
return Status;
}

2
src/mainboard/gizmosphere/gizmo/Makefile.inc
View File

@ -26,12 +26,10 @@ pci$(stripped_ahcibios_id).rom-type := optionrom
endif endif
romstage-y += buildOpts.c romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += BiosCallOuts.c romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c romstage-y += PlatformGnbPcie.c
ramstage-y += buildOpts.c ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c ramstage-y += PlatformGnbPcie.c

618
src/mainboard/gizmosphere/gizmo/agesawrapper.c
View File

@ -1,618 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "PlatformGnbPcieComplex.h"
#define __SIMPLE_DEVICE__
#include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <stdint.h>
#include <string.h>
#include <cpu/amd/agesa/s3_resume.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#define FILECODE UNASSIGNED_FILE_FILECODE
#define MMCONF_ENABLE 1
/* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
/*------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*------------------------------------------------------------------------------
*/
/*------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*------------------------------------------------------------------------------
*/
/*------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*------------------------------------------------------------------------------
*/
/*------------------------------------------------------------------------------
* L O C A L F U N C T I O N S
*------------------------------------------------------------------------------
*/
AGESA_STATUS agesawrapper_amdinitcpuio (
VOID
)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
PciData = 1;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
* set to non-posted regions.
*/
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
PciData |= 1 << 7; // set NP (non-posted) bit
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; // last address before non-posted range
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
PciData = 0x0000F000;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
}
AGESA_STATUS agesawrapper_amdinitmmio (
VOID
)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
UINT8 BusRangeVal = 0;
UINT8 BusNum;
UINT8 Index;
/*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
for (Index = 0; Index < 8; Index++) {
BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
if (BusNum == 1) {
BusRangeVal = Index;
break;
}
}
MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE);
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
/*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000ull;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* Set Ontario Link Data */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
PciData = 0x01308002;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
}
AGESA_STATUS agesawrapper_amdinitreset (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost;
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = NULL;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitearly (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr);
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitpost (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
/* Initialize heap space */
EmptyHeap();
return status;
}
AGESA_STATUS agesawrapper_amdinitenv (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
PCI_ADDR PciAddress;
UINT32 PciValue;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
/* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
/* Write to D1F0x18 */
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x00010100;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Legacy Bridge Mode
* Modify B1D5F0x18
*/
PciAddress.Address.Bus = 1;
PciAddress.Address.Device = 5;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Legacy Bridge Mode
* Modify B1D5F0x10
*/
PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Pcie Mode
* Modify B0D1F0x18
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Pcie Mode
* Modify B0D1F0x10
*/
PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Base and Limit Address
* Modify B0D1F0x20
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x20;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96009600;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Prefetchable Memory Limit and Base
* Modify B0D1F0x24
*/
PciAddress.Address.Register = 0x24;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x8FF18001;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
VOID *
agesawrapper_getlateinitptr (
int pick
)
{
switch (pick) {
case PICK_DMI:
return DmiTable;
case PICK_PSTATE:
return AcpiPstate;
case PICK_SRAT:
return AcpiSrat;
case PICK_SLIT:
return AcpiSlit;
case PICK_WHEA_MCE:
return AcpiWheaMce;
case PICK_WHEA_CMC:
return AcpiWheaCmc;
case PICK_ALIB:
return AcpiAlib;
default:
return NULL;
}
}
AGESA_STATUS agesawrapper_amdinitmid (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
/* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio ();
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitlate (
VOID
)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_LATE_PARAMS * AmdLateParamsPtr;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr);
Status = AmdInitLate (AmdLateParamsPtr);
AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS);
DmiTable = AmdLateParamsPtr->DmiTable;
AcpiPstate = AmdLateParamsPtr->AcpiPState;
AcpiSrat = AmdLateParamsPtr->AcpiSrat;
AcpiSlit = AmdLateParamsPtr->AcpiSlit;
AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
AcpiAlib = AmdLateParamsPtr->AcpiAlib;
printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
" DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n"
" Mce:%p\n Cmc:%p\n Alib:%p\n",
__func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
/* Don't release the structure until coreboot has copied the ACPI tables.
* AmdReleaseStruct (&AmdLateParams);
*/
return Status;
}
AGESA_STATUS agesawrapper_amdinitresume (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESUME_PARAMS *AmdResumeParamsPtr;
S3_DATA_TYPE S3DataType;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr;
AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeNonVolatile;
OemAgesaGetS3Info (S3DataType,
(u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize,
(void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage);
status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amds3laterestore (
VOID
)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
AMD_S3LATE_PARAMS AmdS3LateParams;
AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
S3_DATA_TYPE S3DataType;
memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.AllocationMethod = ByHost;
AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE;
AmdInterfaceParams.NewStructPtr = &AmdS3LateParams;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdS3LateParamsPtr = &AmdS3LateParams;
AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS);
AmdCreateStruct (&AmdInterfaceParams);
AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeVolatile;
OemAgesaGetS3Info (S3DataType,
(u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize,
(void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
Status = AmdS3LateRestore (AmdS3LateParamsPtr);
AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS);
return Status;
}
#ifndef __PRE_RAM__
AGESA_STATUS agesawrapper_amdS3Save (
VOID
)
{
AGESA_STATUS Status;
AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
S3_DATA_TYPE S3DataType;
memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdInterfaceParams.AllocationMethod = PostMemDram;
AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
AmdInterfaceParams.StdHeader.Func = 0;
AmdCreateStruct(&AmdInterfaceParams);
AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr;
AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
Status = AmdS3Save (AmdS3SaveParamsPtr);
AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS);
S3DataType = S3DataTypeNonVolatile;
Status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) {
S3DataType = S3DataTypeVolatile;
Status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage
);
}
OemAgesaSaveMtrr();
AmdReleaseStruct (&AmdInterfaceParams);
return Status;
}
#endif /* #ifndef __PRE_RAM__ */
AGESA_STATUS agesawrapper_amdlaterunaptask (
UINT32 Func,
UINT32 Data,
VOID *ConfigPtr
)
{
AGESA_STATUS Status;
AP_EXE_PARAMS ApExeParams;
memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS));
ApExeParams.StdHeader.AltImageBasePtr = 0;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
ApExeParams.StdHeader.Func = 0;
ApExeParams.StdHeader.ImageBasePtr = 0;
ApExeParams.FunctionNumber = Func;
ApExeParams.RelatedDataBlock = ConfigPtr;
Status = AmdLateRunApTask (&ApExeParams);
AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS);
return Status;
}
AGESA_STATUS agesawrapper_amdreadeventlog (
VOID
)
{
AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams;
memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS));
AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = NULL;
AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0;
Status = AmdReadEventLog (&AmdEventParams);
while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
Status = AmdReadEventLog (&AmdEventParams);
}
return Status;
}

2
src/mainboard/jetway/nf81-t56n-lf/Makefile.inc
View File

@ -25,11 +25,9 @@ pci$(stripped_ahcibios_id).rom-type := optionrom
endif endif
romstage-y += buildOpts.c romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += BiosCallOuts.c romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c romstage-y += PlatformGnbPcie.c
ramstage-y += buildOpts.c ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c ramstage-y += PlatformGnbPcie.c

555
src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c
View File

@ -1,555 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "PlatformGnbPcieComplex.h"
#define __SIMPLE_DEVICE__
#include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <stdint.h>
#include <string.h>
#include <cpu/amd/agesa/s3_resume.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#define FILECODE UNASSIGNED_FILE_FILECODE
#define MMCONF_ENABLE 1
/* ACPI table pointers returned by AmdInitLate */
void *DmiTable = NULL;
void *AcpiPstate = NULL;
void *AcpiSrat = NULL;
void *AcpiSlit = NULL;
void *AcpiWheaMce = NULL;
void *AcpiWheaCmc = NULL;
void *AcpiAlib = NULL;
AGESA_STATUS agesawrapper_amdinitcpuio(void)
{
pci_devfn_t dev;
msr_t msr;
uint32_t reg32;
dev = PCI_DEV(0, 0x18, 1);
/* Enable legacy video routing: D18F1xF4 VGA Enable */
pci_io_write_config32(dev, 0xf4, 1);
/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
* set to non-posted regions.
* Last address before processor local APIC at FEE00000
*/
pci_io_write_config32(dev, 0x84, 0x00fedf00 | (1 << 7));
/* Lowest NP address is HPET at FED00000 */
pci_io_write_config32(dev, 0x80, (0xfed00000 >> 8) | 3);
/* Map the remaining PCI hole as posted MMIO */
pci_io_write_config32(dev, 0x8C, 0x00fecf00);
msr = rdmsr(0xc001001a);
reg32 = (msr.hi << 24) | (msr.lo >> 8) | 3; /* Equivalent to msr >> 8 */
pci_io_write_config32(dev, 0x88, reg32);
/* Send all IO (0000-FFFF) to southbridge. */
pci_io_write_config32(dev, 0xc4, 0x0000f000);
pci_io_write_config32(dev, 0xc0, 0x00000003);
return AGESA_SUCCESS;
}
AGESA_STATUS agesawrapper_amdinitmmio(void)
{
uint64_t MsrReg;
uint32_t PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
uint8_t BusRangeVal = 0;
uint8_t BusNum;
uint8_t Index;
/*
* Set the MMIO Configuration Base Address and Bus Range onto MMIO
* configuration base Address MSR register.
*/
for (Index = 0; Index < 8; Index++) {
BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
if (BusNum == 1) {
BusRangeVal = Index;
break;
}
}
MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (uint64_t)(BusRangeVal << 2) | MMCONF_ENABLE);
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
/*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000ull;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* Set Ontario Link Data */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
PciData = 0x01308002;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
return AGESA_SUCCESS;
}
AGESA_STATUS agesawrapper_amdinitreset(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost;
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = NULL;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitearly(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr);
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitpost(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
/* Initialize heap space */
EmptyHeap();
return status;
}
AGESA_STATUS agesawrapper_amdinitenv(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
PCI_ADDR PciAddress;
uint32_t PciValue;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
/* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
/* Write to D1F0x18 */
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x00010100;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Legacy Bridge Mode
* Modify B1D5F0x18
*/
PciAddress.Address.Bus = 1;
PciAddress.Address.Device = 5;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Legacy Bridge Mode
* Modify B1D5F0x10
*/
PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Pcie Mode
* Modify B0D1F0x18
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Pcie Mode
* Modify B0D1F0x10
*/
PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Base and Limit Address
* Modify B0D1F0x20
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x20;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96009600;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Prefetchable Memory Limit and Base
* Modify B0D1F0x24
*/
PciAddress.Address.Register = 0x24;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x8FF18001;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
void * agesawrapper_getlateinitptr(int pick)
{
switch (pick) {
case PICK_DMI:
return DmiTable;
case PICK_PSTATE:
return AcpiPstate;
case PICK_SRAT:
return AcpiSrat;
case PICK_SLIT:
return AcpiSlit;
case PICK_WHEA_MCE:
return AcpiWheaMce;
case PICK_WHEA_CMC:
return AcpiWheaCmc;
case PICK_ALIB:
return AcpiAlib;
default:
return NULL;
}
}
AGESA_STATUS agesawrapper_amdinitmid(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
/* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio ();
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitlate(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_LATE_PARAMS * AmdLateParamsPtr;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr);
status = AmdInitLate (AmdLateParamsPtr);
AGESA_EVENTLOG(status);
ASSERT(status == AGESA_SUCCESS);
DmiTable = AmdLateParamsPtr->DmiTable;
AcpiPstate = AmdLateParamsPtr->AcpiPState;
AcpiSrat = AmdLateParamsPtr->AcpiSrat;
AcpiSlit = AmdLateParamsPtr->AcpiSlit;
AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
AcpiAlib = AmdLateParamsPtr->AcpiAlib;
printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
" DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n"
" Mce:%p\n Cmc:%p\n Alib:%p\n",
__func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
/* Don't release the structure until coreboot has copied the ACPI tables.
* AmdReleaseStruct (&AmdLateParams);
*/
return status;
}
AGESA_STATUS agesawrapper_amdinitresume(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESUME_PARAMS *AmdResumeParamsPtr;
S3_DATA_TYPE S3DataType;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr;
AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeNonVolatile;
OemAgesaGetS3Info (S3DataType,
(u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize,
(void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage);
status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amds3laterestore(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
AMD_S3LATE_PARAMS AmdS3LateParams;
AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
S3_DATA_TYPE S3DataType;
memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.AllocationMethod = ByHost;
AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE;
AmdInterfaceParams.NewStructPtr = &AmdS3LateParams;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdS3LateParamsPtr = &AmdS3LateParams;
AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS);
AmdCreateStruct (&AmdInterfaceParams);
AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeVolatile;
OemAgesaGetS3Info (S3DataType,
(u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize,
(void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
status = AmdS3LateRestore (AmdS3LateParamsPtr);
AGESA_EVENTLOG(status);
ASSERT(status == AGESA_SUCCESS);
return status;
}
#ifndef __PRE_RAM__
AGESA_STATUS agesawrapper_amdS3Save(void)
{
AGESA_STATUS status;
AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
S3_DATA_TYPE S3DataType;
memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdInterfaceParams.AllocationMethod = PostMemDram;
AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
AmdInterfaceParams.StdHeader.Func = 0;
AmdCreateStruct(&AmdInterfaceParams);
AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr;
AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
status = AmdS3Save (AmdS3SaveParamsPtr);
AGESA_EVENTLOG(status);
ASSERT(status == AGESA_SUCCESS);
S3DataType = S3DataTypeNonVolatile;
status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) {
S3DataType = S3DataTypeVolatile;
status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage
);
}
OemAgesaSaveMtrr();
AmdReleaseStruct (&AmdInterfaceParams);
return status;
}
#endif /* #ifndef __PRE_RAM__ */
AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
AGESA_STATUS status;
AP_EXE_PARAMS ApExeParams;
memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS));
ApExeParams.StdHeader.AltImageBasePtr = 0;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
ApExeParams.StdHeader.Func = 0;
ApExeParams.StdHeader.ImageBasePtr = 0;
ApExeParams.FunctionNumber = Func;
ApExeParams.RelatedDataBlock = ConfigPtr;
status = AmdLateRunApTask (&ApExeParams);
AGESA_EVENTLOG(status);
ASSERT(status == AGESA_SUCCESS);
return status;
}
AGESA_STATUS agesawrapper_amdreadeventlog(void)
{
AGESA_STATUS status;
EVENT_PARAMS AmdEventParams;
memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS));
AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = NULL;
AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0;
status = AmdReadEventLog (&AmdEventParams);
while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
status = AmdReadEventLog (&AmdEventParams);
}
return status;
}

2
src/mainboard/lippert/frontrunner-af/Makefile.inc
View File

@ -25,11 +25,9 @@ pci$(stripped_ahcibios_id).rom-type := optionrom
endif endif
romstage-y += buildOpts.c romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += BiosCallOuts.c romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c romstage-y += PlatformGnbPcie.c
ramstage-y += buildOpts.c ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c ramstage-y += PlatformGnbPcie.c

617
src/mainboard/lippert/frontrunner-af/agesawrapper.c
View File

@ -1,617 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "PlatformGnbPcieComplex.h"
#define __SIMPLE_DEVICE__
#include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <stdint.h>
#include <string.h>
#include <cpu/amd/agesa/s3_resume.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#define FILECODE UNASSIGNED_FILE_FILECODE
#define MMCONF_ENABLE 1
/* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
/*------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*------------------------------------------------------------------------------
*/
/*------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*------------------------------------------------------------------------------
*/
/*------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*------------------------------------------------------------------------------
*/
/*------------------------------------------------------------------------------
* L O C A L F U N C T I O N S
*------------------------------------------------------------------------------
*/
AGESA_STATUS agesawrapper_amdinitcpuio (
VOID
)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
PciData = 1;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
* set to non-posted regions.
*/
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
PciData |= 1 << 7; // set NP (non-posted) bit
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; // last address before non-posted range
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
PciData = 0x0000F000;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
}
AGESA_STATUS agesawrapper_amdinitmmio (
VOID
)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
UINT8 BusRangeVal = 0;
UINT8 BusNum;
UINT8 Index;
/*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
for (Index = 0; Index < 8; Index++) {
BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
if (BusNum == 1) {
BusRangeVal = Index;
break;
}
}
MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE);
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
/*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000ull;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* Set Ontario Link Data */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
PciData = 0x01308002;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
}
AGESA_STATUS agesawrapper_amdinitreset (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost;
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = NULL;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitearly (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr);
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitpost (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
/* Initialize heap space */
EmptyHeap();
return status;
}
AGESA_STATUS agesawrapper_amdinitenv (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
PCI_ADDR PciAddress;
UINT32 PciValue;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
/* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
/* Write to D1F0x18 */
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x00010100;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Legacy Bridge Mode
* Modify B1D5F0x18
*/
PciAddress.Address.Bus = 1;
PciAddress.Address.Device = 5;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Legacy Bridge Mode
* Modify B1D5F0x10
*/
PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Pcie Mode
* Modify B0D1F0x18
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Pcie Mode
* Modify B0D1F0x10
*/
PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Base and Limit Address
* Modify B0D1F0x20
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x20;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96009600;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Prefetchable Memory Limit and Base
* Modify B0D1F0x24
*/
PciAddress.Address.Register = 0x24;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x8FF18001;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
VOID *
agesawrapper_getlateinitptr (
int pick
)
{
switch (pick) {
case PICK_DMI:
return DmiTable;
case PICK_PSTATE:
return AcpiPstate;
case PICK_SRAT:
return AcpiSrat;
case PICK_SLIT:
return AcpiSlit;
case PICK_WHEA_MCE:
return AcpiWheaMce;
case PICK_WHEA_CMC:
return AcpiWheaCmc;
case PICK_ALIB:
return AcpiAlib;
default:
return NULL;
}
}
AGESA_STATUS agesawrapper_amdinitmid (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
/* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio ();
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitlate (
VOID
)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_LATE_PARAMS * AmdLateParamsPtr;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr);
Status = AmdInitLate (AmdLateParamsPtr);
AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS);
DmiTable = AmdLateParamsPtr->DmiTable;
AcpiPstate = AmdLateParamsPtr->AcpiPState;
AcpiSrat = AmdLateParamsPtr->AcpiSrat;
AcpiSlit = AmdLateParamsPtr->AcpiSlit;
AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
AcpiAlib = AmdLateParamsPtr->AcpiAlib;
printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
" DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n"
" Mce:%p\n Cmc:%p\n Alib:%p\n",
__func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
/* Don't release the structure until coreboot has copied the ACPI tables.
* AmdReleaseStruct (&AmdLateParams);
*/
return Status;
}
AGESA_STATUS agesawrapper_amdinitresume (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESUME_PARAMS *AmdResumeParamsPtr;
S3_DATA_TYPE S3DataType;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr;
AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeNonVolatile;
OemAgesaGetS3Info (S3DataType,
(u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize,
(void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage);
status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amds3laterestore (
VOID
)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
AMD_S3LATE_PARAMS AmdS3LateParams;
AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
S3_DATA_TYPE S3DataType;
memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.AllocationMethod = ByHost;
AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE;
AmdInterfaceParams.NewStructPtr = &AmdS3LateParams;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdS3LateParamsPtr = &AmdS3LateParams;
AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS);
AmdCreateStruct (&AmdInterfaceParams);
AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeVolatile;
OemAgesaGetS3Info (S3DataType,
(u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize,
(void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
Status = AmdS3LateRestore (AmdS3LateParamsPtr);
AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS);
return Status;
}
#ifndef __PRE_RAM__
AGESA_STATUS agesawrapper_amdS3Save (
VOID
)
{
AGESA_STATUS Status;
AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
S3_DATA_TYPE S3DataType;
memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdInterfaceParams.AllocationMethod = PostMemDram;
AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
AmdInterfaceParams.StdHeader.Func = 0;
AmdCreateStruct(&AmdInterfaceParams);
AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr;
AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
Status = AmdS3Save (AmdS3SaveParamsPtr);
AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS);
S3DataType = S3DataTypeNonVolatile;
Status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) {
S3DataType = S3DataTypeVolatile;
Status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage
);
}
OemAgesaSaveMtrr();
AmdReleaseStruct (&AmdInterfaceParams);
return Status;
}
#endif /* #ifndef __PRE_RAM__ */
AGESA_STATUS agesawrapper_amdlaterunaptask (
UINT32 Func,
UINT32 Data,
VOID *ConfigPtr
)
{
AGESA_STATUS Status;
AP_EXE_PARAMS ApExeParams;
memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS));
ApExeParams.StdHeader.AltImageBasePtr = 0;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
ApExeParams.StdHeader.Func = 0;
ApExeParams.StdHeader.ImageBasePtr = 0;
ApExeParams.FunctionNumber = Func;
ApExeParams.RelatedDataBlock = ConfigPtr;
Status = AmdLateRunApTask (&ApExeParams);
AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS);
return Status;
}
AGESA_STATUS agesawrapper_amdreadeventlog (
VOID
)
{
AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams;
memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS));
AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = NULL;
AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0;
Status = AmdReadEventLog (&AmdEventParams);
while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
Status = AmdReadEventLog (&AmdEventParams);
}
return Status;
}

2
src/mainboard/lippert/toucan-af/Makefile.inc
View File

@ -25,11 +25,9 @@ pci$(stripped_ahcibios_id).rom-type := optionrom
endif endif
romstage-y += buildOpts.c romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += BiosCallOuts.c romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c romstage-y += PlatformGnbPcie.c
ramstage-y += buildOpts.c ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c ramstage-y += PlatformGnbPcie.c

617
src/mainboard/lippert/toucan-af/agesawrapper.c
View File

@ -1,617 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "PlatformGnbPcieComplex.h"
#define __SIMPLE_DEVICE__
#include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <stdint.h>
#include <string.h>
#include <cpu/amd/agesa/s3_resume.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#define FILECODE UNASSIGNED_FILE_FILECODE
#define MMCONF_ENABLE 1
/* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
/*------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*------------------------------------------------------------------------------
*/
/*------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*------------------------------------------------------------------------------
*/
/*------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*------------------------------------------------------------------------------
*/
/*------------------------------------------------------------------------------
* L O C A L F U N C T I O N S
*------------------------------------------------------------------------------
*/
AGESA_STATUS agesawrapper_amdinitcpuio (
VOID
)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
PciData = 1;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
* set to non-posted regions.
*/
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
PciData |= 1 << 7; // set NP (non-posted) bit
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; // last address before non-posted range
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
PciData = 0x0000F000;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
}
AGESA_STATUS agesawrapper_amdinitmmio (
VOID
)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
UINT8 BusRangeVal = 0;
UINT8 BusNum;
UINT8 Index;
/*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
for (Index = 0; Index < 8; Index++) {
BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
if (BusNum == 1) {
BusRangeVal = Index;
break;
}
}
MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE);
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
/*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000ull;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* Set Ontario Link Data */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
PciData = 0x01308002;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
}
AGESA_STATUS agesawrapper_amdinitreset (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost;
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = NULL;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitearly (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr);
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitpost (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
/* Initialize heap space */
EmptyHeap();
return status;
}
AGESA_STATUS agesawrapper_amdinitenv (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
PCI_ADDR PciAddress;
UINT32 PciValue;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
/* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
/* Write to D1F0x18 */
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x00010100;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Legacy Bridge Mode
* Modify B1D5F0x18
*/
PciAddress.Address.Bus = 1;
PciAddress.Address.Device = 5;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Legacy Bridge Mode
* Modify B1D5F0x10
*/
PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Pcie Mode
* Modify B0D1F0x18
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Pcie Mode
* Modify B0D1F0x10
*/
PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Base and Limit Address
* Modify B0D1F0x20
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x20;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96009600;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Prefetchable Memory Limit and Base
* Modify B0D1F0x24
*/
PciAddress.Address.Register = 0x24;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x8FF18001;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
VOID *
agesawrapper_getlateinitptr (
int pick
)
{
switch (pick) {
case PICK_DMI:
return DmiTable;
case PICK_PSTATE:
return AcpiPstate;
case PICK_SRAT:
return AcpiSrat;
case PICK_SLIT:
return AcpiSlit;
case PICK_WHEA_MCE:
return AcpiWheaMce;
case PICK_WHEA_CMC:
return AcpiWheaCmc;
case PICK_ALIB:
return AcpiAlib;
default:
return NULL;
}
}
AGESA_STATUS agesawrapper_amdinitmid (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
/* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio ();
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitlate (
VOID
)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_LATE_PARAMS * AmdLateParamsPtr;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr);
Status = AmdInitLate (AmdLateParamsPtr);
AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS);
DmiTable = AmdLateParamsPtr->DmiTable;
AcpiPstate = AmdLateParamsPtr->AcpiPState;
AcpiSrat = AmdLateParamsPtr->AcpiSrat;
AcpiSlit = AmdLateParamsPtr->AcpiSlit;
AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
AcpiAlib = AmdLateParamsPtr->AcpiAlib;
printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
" DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n"
" Mce:%p\n Cmc:%p\n Alib:%p\n",
__func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
/* Don't release the structure until coreboot has copied the ACPI tables.
* AmdReleaseStruct (&AmdLateParams);
*/
return Status;
}
AGESA_STATUS agesawrapper_amdinitresume (
VOID
)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESUME_PARAMS *AmdResumeParamsPtr;
S3_DATA_TYPE S3DataType;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr;
AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeNonVolatile;
OemAgesaGetS3Info (S3DataType,
(u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize,
(void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage);
status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amds3laterestore (
VOID
)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
AMD_S3LATE_PARAMS AmdS3LateParams;
AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
S3_DATA_TYPE S3DataType;
memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.AllocationMethod = ByHost;
AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE;
AmdInterfaceParams.NewStructPtr = &AmdS3LateParams;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdS3LateParamsPtr = &AmdS3LateParams;
AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS);
AmdCreateStruct (&AmdInterfaceParams);
AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeVolatile;
OemAgesaGetS3Info (S3DataType,
(u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize,
(void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
Status = AmdS3LateRestore (AmdS3LateParamsPtr);
AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS);
return Status;
}
#ifndef __PRE_RAM__
AGESA_STATUS agesawrapper_amdS3Save (
VOID
)
{
AGESA_STATUS Status;
AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
S3_DATA_TYPE S3DataType;
memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdInterfaceParams.AllocationMethod = PostMemDram;
AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
AmdInterfaceParams.StdHeader.Func = 0;
AmdCreateStruct(&AmdInterfaceParams);
AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr;
AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
Status = AmdS3Save (AmdS3SaveParamsPtr);
AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS);
S3DataType = S3DataTypeNonVolatile;
Status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) {
S3DataType = S3DataTypeVolatile;
Status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage
);
}
OemAgesaSaveMtrr();
AmdReleaseStruct (&AmdInterfaceParams);
return Status;
}
#endif /* #ifndef __PRE_RAM__ */
AGESA_STATUS agesawrapper_amdlaterunaptask (
UINT32 Func,
UINT32 Data,
VOID *ConfigPtr
)
{
AGESA_STATUS Status;
AP_EXE_PARAMS ApExeParams;
memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS));
ApExeParams.StdHeader.AltImageBasePtr = 0;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
ApExeParams.StdHeader.Func = 0;
ApExeParams.StdHeader.ImageBasePtr = 0;
ApExeParams.FunctionNumber = Func;
ApExeParams.RelatedDataBlock = ConfigPtr;
Status = AmdLateRunApTask (&ApExeParams);
AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS);
return Status;
}
AGESA_STATUS agesawrapper_amdreadeventlog (
VOID
)
{
AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams;
memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS));
AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = NULL;
AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0;
Status = AmdReadEventLog (&AmdEventParams);
while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
Status = AmdReadEventLog (&AmdEventParams);
}
return Status;
}

2
src/northbridge/amd/agesa/family14/Makefile.inc
View File

@ -18,5 +18,7 @@
# #
romstage-y += dimmSpd.c romstage-y += dimmSpd.c
romstage-y += agesawrapper.c
ramstage-y += northbridge.c ramstage-y += northbridge.c
ramstage-y += agesawrapper.c

436
src/mainboard/amd/persimmon/agesawrapper.c → src/northbridge/amd/agesa/family14/agesawrapper.c
View File

@ -17,10 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "PlatformGnbPcieComplex.h"
#define __SIMPLE_DEVICE__ #define __SIMPLE_DEVICE__
#include <arch/io.h> #include <arch/io.h>
@ -30,6 +26,10 @@
#include <string.h> #include <string.h>
#include <cpu/amd/agesa/s3_resume.h> #include <cpu/amd/agesa/s3_resume.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "amdlib.h"
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#define FILECODE UNASSIGNED_FILE_FILECODE #define FILECODE UNASSIGNED_FILE_FILECODE
@ -37,27 +37,26 @@
#define MMCONF_ENABLE 1 #define MMCONF_ENABLE 1
/* ACPI table pointers returned by AmdInitLate */ /* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL; VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL; VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL; VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL; VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL; VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL; VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL; VOID *AcpiAlib = NULL;
AGESA_STATUS agesawrapper_amdinitcpuio ( VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly);
VOID
) AGESA_STATUS agesawrapper_amdinitcpuio(VOID)
{ {
AGESA_STATUS Status; UINT64 MsrReg;
UINT64 MsrReg; UINT32 PciData;
UINT32 PciData; PCI_ADDR PciAddress;
PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader;
AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */ /* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
PciData = 1; PciData = 1;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
@ -65,53 +64,50 @@ AGESA_STATUS agesawrapper_amdinitcpuio (
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
* set to non-posted regions. * set to non-posted regions.
*/ */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
PciData |= 1 << 7; // set NP (non-posted) bit PciData |= 1 << 7; // set NP (non-posted) bit
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */ /* Map the remaining PCI hole as posted MMIO */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; // last address before non-posted range PciData = 0x00FECF00; // last address before non-posted range
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3; MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg; PciData = (UINT32) MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */ /* Send all IO (0000-FFFF) to southbridge. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
PciData = 0x0000F000; PciData = 0x0000F000;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
PciData = 0x00000003; PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return Status; return AGESA_SUCCESS;
} }
AGESA_STATUS agesawrapper_amdinitmmio ( AGESA_STATUS agesawrapper_amdinitmmio(VOID)
VOID
)
{ {
AGESA_STATUS Status; UINT64 MsrReg;
UINT64 MsrReg; UINT32 PciData;
UINT32 PciData; PCI_ADDR PciAddress;
PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader;
AMD_CONFIG_PARAMS StdHeader;
UINT8 BusRangeVal = 0; UINT8 BusRangeVal = 0;
UINT8 BusNum; UINT8 BusNum;
UINT8 Index; UINT8 Index;
/* /*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register. Address MSR register.
*/ */
for (Index = 0; Index < 8; Index++) { for (Index = 0; Index < 8; Index++) {
BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
@ -121,31 +117,28 @@ AGESA_STATUS agesawrapper_amdinitmmio (
} }
} }
MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE); MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64) (BusRangeVal << 2) | MMCONF_ENABLE);
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
/* /*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/ */
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000ull; MsrReg = MsrReg | 0x0000400000000000ull;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
/* Set Ontario Link Data */ /* Set Ontario Link Data */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0);
PciData = 0x01308002; PciData = 0x01308002;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE4);
PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; PciData = (AMD_APU_SSID << 0x10) | AMD_APU_SVID;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS; return AGESA_SUCCESS;
return Status;
} }
AGESA_STATUS agesawrapper_amdinitreset ( AGESA_STATUS agesawrapper_amdinitreset(VOID)
VOID
)
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
@ -162,63 +155,59 @@ AGESA_STATUS agesawrapper_amdinitreset (
AmdParamStruct.StdHeader.CalloutPtr = NULL; AmdParamStruct.StdHeader.CalloutPtr = NULL;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct(&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0; AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status); AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
} }
AGESA_STATUS agesawrapper_amdinitearly ( AGESA_STATUS agesawrapper_amdinitearly(VOID)
VOID
)
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr; AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap; AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct(&AmdParamStruct);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr); OemCustomizeInitEarly(AmdEarlyParamsPtr);
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status); AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
} }
AGESA_STATUS agesawrapper_amdinitpost ( AGESA_STATUS agesawrapper_amdinitpost(VOID)
VOID
)
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap; AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct(&AmdParamStruct);
status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitPost((AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status); AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
/* Initialize heap space */ /* Initialize heap space */
EmptyHeap(); EmptyHeap();
@ -226,249 +215,237 @@ AGESA_STATUS agesawrapper_amdinitpost (
return status; return status;
} }
AGESA_STATUS agesawrapper_amdinitenv ( AGESA_STATUS agesawrapper_amdinitenv(VOID)
VOID
)
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
PCI_ADDR PciAddress; PCI_ADDR PciAddress;
UINT32 PciValue; UINT32 PciValue;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct(&AmdParamStruct);
status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitEnv((AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status); AGESA_EVENTLOG(status);
/* Initialize Subordinate Bus Number and Secondary Bus Number /* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code * In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18 Modify D1F0x18
*/ */
PciAddress.Address.Bus = 0; PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1; PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0; PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18; PciAddress.Address.Register = 0x18;
/* Write to D1F0x18 */ /* Write to D1F0x18 */
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x00010100; PciValue |= 0x00010100;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Legacy Bridge Mode /* Initialize GMM Base Address for Legacy Bridge Mode
* Modify B1D5F0x18 * Modify B1D5F0x18
*/ */
PciAddress.Address.Bus = 1; PciAddress.Address.Bus = 1;
PciAddress.Address.Device = 5; PciAddress.Address.Device = 5;
PciAddress.Address.Function = 0; PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18; PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000; PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Legacy Bridge Mode /* Initialize FB Base Address for Legacy Bridge Mode
* Modify B1D5F0x10 * Modify B1D5F0x10
*/ */
PciAddress.Address.Register = 0x10; PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000; PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Pcie Mode /* Initialize GMM Base Address for Pcie Mode
* Modify B0D1F0x18 * Modify B0D1F0x18
*/ */
PciAddress.Address.Bus = 0; PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1; PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0; PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18; PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000; PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Pcie Mode /* Initialize FB Base Address for Pcie Mode
* Modify B0D1F0x10 * Modify B0D1F0x10
*/ */
PciAddress.Address.Register = 0x10; PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000; PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Base and Limit Address /* Initialize MMIO Base and Limit Address
* Modify B0D1F0x20 * Modify B0D1F0x20
*/ */
PciAddress.Address.Bus = 0; PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1; PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0; PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x20; PciAddress.Address.Register = 0x20;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96009600; PciValue |= 0x96009600;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Prefetchable Memory Limit and Base /* Initialize MMIO Prefetchable Memory Limit and Base
* Modify B0D1F0x24 * Modify B0D1F0x24
*/ */
PciAddress.Address.Register = 0x24; PciAddress.Address.Register = 0x24;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x8FF18001; PciValue |= 0x8FF18001;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
} }
VOID * VOID *agesawrapper_getlateinitptr(int pick)
agesawrapper_getlateinitptr (
int pick
)
{ {
switch (pick) { switch (pick) {
case PICK_DMI: case PICK_DMI:
return DmiTable; return DmiTable;
case PICK_PSTATE: case PICK_PSTATE:
return AcpiPstate; return AcpiPstate;
case PICK_SRAT: case PICK_SRAT:
return AcpiSrat; return AcpiSrat;
case PICK_SLIT: case PICK_SLIT:
return AcpiSlit; return AcpiSlit;
case PICK_WHEA_MCE: case PICK_WHEA_MCE:
return AcpiWheaMce; return AcpiWheaMce;
case PICK_WHEA_CMC: case PICK_WHEA_CMC:
return AcpiWheaCmc; return AcpiWheaCmc;
case PICK_ALIB: case PICK_ALIB:
return AcpiAlib; return AcpiAlib;
default: default:
return NULL; return NULL;
} }
} }
AGESA_STATUS agesawrapper_amdinitmid ( AGESA_STATUS agesawrapper_amdinitmid(VOID)
VOID
)
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
/* Enable MMIO on AMD CPU Address Map Controller */ /* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio (); agesawrapper_amdinitcpuio();
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct(&AmdParamStruct);
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status); AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
} }
AGESA_STATUS agesawrapper_amdinitlate ( AGESA_STATUS agesawrapper_amdinitlate(VOID)
VOID
)
{ {
AGESA_STATUS Status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_LATE_PARAMS * AmdLateParamsPtr; AMD_LATE_PARAMS *AmdLateParamsPtr;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct(&AmdParamStruct);
AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n",
(u32) AmdLateParamsPtr);
Status = AmdInitLate (AmdLateParamsPtr); status = AmdInitLate(AmdLateParamsPtr);
AGESA_EVENTLOG(Status); AGESA_EVENTLOG(status);
ASSERT(Status == AGESA_SUCCESS); ASSERT(status == AGESA_SUCCESS);
DmiTable = AmdLateParamsPtr->DmiTable; DmiTable = AmdLateParamsPtr->DmiTable;
AcpiPstate = AmdLateParamsPtr->AcpiPState; AcpiPstate = AmdLateParamsPtr->AcpiPState;
AcpiSrat = AmdLateParamsPtr->AcpiSrat; AcpiSrat = AmdLateParamsPtr->AcpiSrat;
AcpiSlit = AmdLateParamsPtr->AcpiSlit; AcpiSlit = AmdLateParamsPtr->AcpiSlit;
AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce; AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc; AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
AcpiAlib = AmdLateParamsPtr->AcpiAlib; AcpiAlib = AmdLateParamsPtr->AcpiAlib;
printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
" DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n"
" Mce:%p\n Cmc:%p\n Alib:%p\n", " Mce:%p\n Cmc:%p\n Alib:%p\n",
__func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, AcpiWheaMce, AcpiWheaCmc,
AcpiWheaMce, AcpiWheaCmc, AcpiAlib); AcpiAlib);
/* Don't release the structure until coreboot has copied the ACPI tables. /* Don't release the structure until coreboot has copied the ACPI tables.
* AmdReleaseStruct (&AmdLateParams); * AmdReleaseStruct (&AmdLateParams);
*/ */
return Status; return status;
} }
AGESA_STATUS agesawrapper_amdinitresume ( AGESA_STATUS agesawrapper_amdinitresume(VOID)
VOID
)
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESUME_PARAMS *AmdResumeParamsPtr; AMD_RESUME_PARAMS *AmdResumeParamsPtr;
S3_DATA_TYPE S3DataType; S3_DATA_TYPE S3DataType;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME;
AmdParamStruct.AllocationMethod = PreMemHeap; AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct(&AmdParamStruct);
AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr;
AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeNonVolatile; S3DataType = S3DataTypeNonVolatile;
OemAgesaGetS3Info (S3DataType, OemAgesaGetS3Info(S3DataType,
(u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, (u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize,
(void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); (void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage);
status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status); AGESA_EVENTLOG(status);
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct(&AmdParamStruct);
return status; return status;
} }
AGESA_STATUS agesawrapper_amds3laterestore ( AGESA_STATUS agesawrapper_amds3laterestore(VOID)
VOID
)
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdInterfaceParams; AMD_INTERFACE_PARAMS AmdInterfaceParams;
AMD_S3LATE_PARAMS AmdS3LateParams; AMD_S3LATE_PARAMS AmdS3LateParams;
AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
S3_DATA_TYPE S3DataType; S3_DATA_TYPE S3DataType;
memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS)); memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS));
@ -476,20 +453,20 @@ AGESA_STATUS agesawrapper_amds3laterestore (
AmdInterfaceParams.AllocationMethod = ByHost; AmdInterfaceParams.AllocationMethod = ByHost;
AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE;
AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; AmdInterfaceParams.NewStructPtr = &AmdS3LateParams;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdS3LateParamsPtr = &AmdS3LateParams; AmdS3LateParamsPtr = &AmdS3LateParams;
AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS);
AmdCreateStruct (&AmdInterfaceParams); AmdCreateStruct(&AmdInterfaceParams);
AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeVolatile; S3DataType = S3DataTypeVolatile;
OemAgesaGetS3Info (S3DataType, OemAgesaGetS3Info(S3DataType,
(u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, (u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize,
(void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
Status = AmdS3LateRestore (AmdS3LateParamsPtr); Status = AmdS3LateRestore(AmdS3LateParamsPtr);
AGESA_EVENTLOG(Status); AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS); ASSERT(Status == AGESA_SUCCESS);
@ -497,85 +474,74 @@ AGESA_STATUS agesawrapper_amds3laterestore (
} }
#ifndef __PRE_RAM__ #ifndef __PRE_RAM__
AGESA_STATUS agesawrapper_amdS3Save ( AGESA_STATUS agesawrapper_amdS3Save(VOID)
VOID
)
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
AMD_INTERFACE_PARAMS AmdInterfaceParams; AMD_INTERFACE_PARAMS AmdInterfaceParams;
S3_DATA_TYPE S3DataType; S3_DATA_TYPE S3DataType;
memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS)); memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdInterfaceParams.AllocationMethod = PostMemDram; AmdInterfaceParams.AllocationMethod = PostMemDram;
AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
AmdInterfaceParams.StdHeader.Func = 0; AmdInterfaceParams.StdHeader.Func = 0;
AmdCreateStruct(&AmdInterfaceParams); AmdCreateStruct(&AmdInterfaceParams);
AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr;
AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
Status = AmdS3Save (AmdS3SaveParamsPtr); Status = AmdS3Save(AmdS3SaveParamsPtr);
AGESA_EVENTLOG(Status); AGESA_EVENTLOG(Status);
ASSERT(Status == AGESA_SUCCESS); ASSERT(Status == AGESA_SUCCESS);
S3DataType = S3DataTypeNonVolatile; S3DataType = S3DataTypeNonVolatile;
Status = OemAgesaSaveS3Info ( Status = OemAgesaSaveS3Info(S3DataType,
S3DataType, AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) {
S3DataType = S3DataTypeVolatile; S3DataType = S3DataTypeVolatile;
Status = OemAgesaSaveS3Info ( Status = OemAgesaSaveS3Info(S3DataType,
S3DataType, AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage
);
} }
OemAgesaSaveMtrr(); OemAgesaSaveMtrr();
AmdReleaseStruct (&AmdInterfaceParams); AmdReleaseStruct(&AmdInterfaceParams);
return Status; return Status;
} }
#endif /* #ifndef __PRE_RAM__ */ #endif /* #ifndef __PRE_RAM__ */
AGESA_STATUS agesawrapper_amdlaterunaptask ( AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr)
UINT32 Func,
UINT32 Data,
VOID *ConfigPtr
)
{ {
AGESA_STATUS Status; AGESA_STATUS status;
AP_EXE_PARAMS ApExeParams; AP_EXE_PARAMS ApExeParams;
memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS)); memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS));
ApExeParams.StdHeader.AltImageBasePtr = 0; ApExeParams.StdHeader.AltImageBasePtr = 0;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
ApExeParams.StdHeader.Func = 0; ApExeParams.StdHeader.Func = 0;
ApExeParams.StdHeader.ImageBasePtr = 0; ApExeParams.StdHeader.ImageBasePtr = 0;
ApExeParams.FunctionNumber = Func; ApExeParams.FunctionNumber = Func;
ApExeParams.RelatedDataBlock = ConfigPtr; ApExeParams.RelatedDataBlock = ConfigPtr;
Status = AmdLateRunApTask (&ApExeParams); status = AmdLateRunApTask(&ApExeParams);
AGESA_EVENTLOG(Status); AGESA_EVENTLOG(status);
ASSERT(Status == AGESA_SUCCESS); ASSERT(status == AGESA_SUCCESS);
return Status; return status;
} }
AGESA_STATUS agesawrapper_amdreadeventlog ( AGESA_STATUS agesawrapper_amdreadeventlog(VOID)
VOID
)
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams; EVENT_PARAMS AmdEventParams;
@ -586,12 +552,16 @@ AGESA_STATUS agesawrapper_amdreadeventlog (
AmdEventParams.StdHeader.CalloutPtr = NULL; AmdEventParams.StdHeader.CalloutPtr = NULL;
AmdEventParams.StdHeader.Func = 0; AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0; AmdEventParams.StdHeader.ImageBasePtr = 0;
Status = AmdReadEventLog (&AmdEventParams); Status = AmdReadEventLog(&AmdEventParams);
while (AmdEventParams.EventClass != 0) { while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); printk(BIOS_DEBUG,
printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); "\nEventLog: EventClass = %lx, EventInfo = %lx.\n",
printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); AmdEventParams.EventClass, AmdEventParams.EventInfo);
Status = AmdReadEventLog (&AmdEventParams); printk(BIOS_DEBUG, " Param1 = %lx, Param2 = %lx.\n",
AmdEventParams.DataParam1, AmdEventParams.DataParam2);
printk(BIOS_DEBUG, " Param3 = %lx, Param4 = %lx.\n",
AmdEventParams.DataParam3, AmdEventParams.DataParam4);
Status = AmdReadEventLog(&AmdEventParams);
} }
return Status; return Status;