arch/x86: Pass GNVS as parameter to SMM module

Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48698
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/x86/smm/smm_module_handler.c

@@ -134,8 +134,10 @@ asmlinkage void smm_handler_start(void *arg)
 
 	/* Make sure to set the global runtime. It's OK to race as the value
 	 * will be the same across CPUs as well as multiple SMIs. */
-	if (smm_runtime == NULL)
+	if (smm_runtime == NULL) {
 		smm_runtime = runtime;
+		gnvs = (void *)(uintptr_t)smm_runtime->gnvs_ptr;
+	}
 
 	if (cpu >= CONFIG_MAX_CPUS) {
 		console_init();

src/soc/intel/baytrail/smihandler.c

@@ -18,8 +18,6 @@
 #include <soc/pm.h>
 #include <soc/nvs.h>
 
-static int smm_initialized;
-
 int southbridge_io_trap_handler(int smif)
 {
 	switch (smif) {
@@ -282,7 +280,6 @@ static void southbridge_smi_store(void)
 static void southbridge_smi_apmc(void)
 {
 	uint8_t reg8;
-	em64t100_smm_state_save_area_t *state;
 
 	/* Emulate B2 register as the FADT / Linux expects it */
 
@@ -312,23 +309,6 @@ static void southbridge_smi_apmc(void)
 		enable_pm1_control(SCI_EN);
 		printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
 		break;
-	case APM_CNT_GNVS_UPDATE:
-		if (smm_initialized) {
-			printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
-			return;
-		}
-		state = smi_apmc_find_state_save(reg8);
-		if (state) {
-			/* EBX in the state save contains the GNVS pointer */
-			gnvs = (struct global_nvs *)((uint32_t)state->rbx);
-			if (smm_points_to_smram(gnvs, sizeof(*gnvs))) {
-				printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n");
-				return;
-			}
-			smm_initialized = 1;
-			printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
-		}
-		break;
 	case APM_CNT_ELOG_GSMI:
 		if (CONFIG(ELOG_GSMI))
 			southbridge_smi_gsmi();

src/soc/intel/baytrail/southcluster.c

@@ -497,8 +497,6 @@ static void southcluster_inject_dsdt(const struct device *device)
 
 	if (gnvs) {
 		acpi_create_gnvs(gnvs);
-		/* And tell SMI about it */
-		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT.  */
 		acpigen_write_scope("\\");

src/soc/intel/braswell/acpi.c

@@ -397,9 +397,6 @@ void southcluster_inject_dsdt(const struct device *device)
 		else
 			gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN;
 
-		/* And tell SMI about it */
-		apm_control(APM_CNT_GNVS_UPDATE);
-
 		/* Add it to DSDT */
 		acpigen_write_scope("\\");
 		acpigen_write_name_dword("NVSA", (u32) gnvs);

src/soc/intel/braswell/smihandler.c

@@ -18,8 +18,6 @@
 #include <soc/gpio.h>
 #include <smmstore.h>
 
-static int smm_initialized;
-
 int southbridge_io_trap_handler(int smif)
 {
 	switch (smif) {
@@ -261,7 +259,6 @@ static void southbridge_smi_store(void)
 static void southbridge_smi_apmc(void)
 {
 	uint8_t reg8;
-	em64t100_smm_state_save_area_t *state;
 
 	/* Emulate B2 register as the FADT / Linux expects it */
 
@@ -291,23 +288,6 @@ static void southbridge_smi_apmc(void)
 		enable_pm1_control(SCI_EN);
 		printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
 		break;
-	case APM_CNT_GNVS_UPDATE:
-		if (smm_initialized) {
-			printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
-			return;
-		}
-		state = smi_apmc_find_state_save(reg8);
-		if (state) {
-			/* EBX in the state save contains the GNVS pointer */
-			gnvs = (struct global_nvs *)((uint32_t)state->rbx);
-			if (smm_points_to_smram(gnvs, sizeof(*gnvs))) {
-				printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n");
-				return;
-			}
-			smm_initialized = 1;
-			printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
-		}
-		break;
 	case APM_CNT_ELOG_GSMI:
 		if (CONFIG(ELOG_GSMI))
 			southbridge_smi_gsmi();

src/soc/intel/broadwell/pch/lpc.c

@@ -646,9 +646,6 @@ static void southcluster_inject_dsdt(const struct device *device)
 			}
 		}
 
-		/* And tell SMI about it */
-		apm_control(APM_CNT_GNVS_UPDATE);
-
 		/* Add it to DSDT.  */
 		acpigen_write_scope("\\");
 		acpigen_write_name_dword("NVSA", (u32) gnvs);

src/soc/intel/broadwell/pch/smihandler.c

@@ -23,8 +23,6 @@
 #include <drivers/intel/gma/i915_reg.h>
 #include <smmstore.h>
 
-static u8 smm_initialized = 0;
-
 int southbridge_io_trap_handler(int smif)
 {
 	switch (smif) {
@@ -313,7 +311,6 @@ static void southbridge_smi_store(void)
 static void southbridge_smi_apmc(void)
 {
 	u8 reg8;
-	em64t101_smm_state_save_area_t *state;
 
 	/* Emulate B2 register as the FADT / Linux expects it */
 
@@ -333,24 +330,6 @@ static void southbridge_smi_apmc(void)
 		enable_pm1_control(SCI_EN);
 		printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
 		break;
-	case APM_CNT_GNVS_UPDATE:
-		if (smm_initialized) {
-			printk(BIOS_DEBUG,
-			       "SMI#: SMM structures already initialized!\n");
-			return;
-		}
-		state = smi_apmc_find_state_save(reg8);
-		if (state) {
-			/* EBX in the state save contains the GNVS pointer */
-			gnvs = (struct global_nvs *)((u32)state->rbx);
-			if (smm_points_to_smram(gnvs, sizeof(*gnvs))) {
-				printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n");
-				return;
-			}
-			smm_initialized = 1;
-			printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
-		}
-		break;
 	case APM_CNT_ELOG_GSMI:
 		if (CONFIG(ELOG_GSMI))
 			southbridge_smi_gsmi();

src/soc/intel/common/block/acpi/acpi.c

@@ -252,8 +252,6 @@ void southbridge_inject_dsdt(const struct device *device)
 
 	if (gnvs) {
 		acpi_create_gnvs(gnvs);
-		/* And tell SMI about it */
-		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT.  */
 		acpigen_write_scope("\\");

src/soc/intel/common/block/smm/smihandler.c

@@ -330,8 +330,6 @@ void smihandler_southbridge_apmc(
 	const struct smm_save_state_ops *save_state_ops)
 {
 	uint8_t reg8;
-	void *state = NULL;
-	static int smm_initialized = 0;
 
 	/* Emulate B2 register as the FADT / Linux expects it */
 
@@ -361,25 +359,6 @@ void smihandler_southbridge_apmc(
 		pmc_enable_pm1_control(SCI_EN);
 		printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
 		break;
-	case APM_CNT_GNVS_UPDATE:
-		if (smm_initialized) {
-			printk(BIOS_DEBUG,
-			       "SMI#: SMM structures already initialized!\n");
-			return;
-		}
-		state = find_save_state(save_state_ops, reg8);
-		if (state) {
-			/* EBX in the state save contains the GNVS pointer */
-			uint32_t reg_ebx = save_state_ops->get_reg(state, RBX);
-			gnvs = (struct global_nvs *)(uintptr_t)reg_ebx;
-			if (smm_points_to_smram(gnvs, sizeof(*gnvs))) {
-				printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n");
-				return;
-			}
-			smm_initialized = 1;
-			printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
-		}
-		break;
 	case APM_CNT_ELOG_GSMI:
 		if (CONFIG(ELOG_GSMI))
 			southbridge_smi_gsmi(save_state_ops);

src/soc/intel/denverton_ns/acpi.c

@@ -259,8 +259,6 @@ void southcluster_inject_dsdt(const struct device *device)
 
 	if (gnvs) {
 		acpi_create_gnvs(gnvs);
-		/* And tell SMI about it */
-		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT.  */
 		acpigen_write_scope("\\");

src/soc/intel/denverton_ns/smihandler.c

@@ -17,8 +17,6 @@
 #include <soc/pm.h>
 #include <soc/nvs.h>
 
-static int smm_initialized;
-
 int southbridge_io_trap_handler(int smif)
 {
 	switch (smif) {
@@ -221,7 +219,6 @@ static void southbridge_smi_store(void)
 static void southbridge_smi_apmc(void)
 {
 	uint8_t reg8;
-	em64t100_smm_state_save_area_t *state;
 
 	/* Emulate B2 register as the FADT / Linux expects it */
 
@@ -252,20 +249,6 @@ static void southbridge_smi_apmc(void)
 	case APM_CNT_FINALIZE:
 		finalize();
 		break;
-	case APM_CNT_GNVS_UPDATE:
-		if (smm_initialized) {
-			printk(BIOS_DEBUG,
-			       "SMI#: SMM structures already initialized!\n");
-			return;
-		}
-		state = smi_apmc_find_state_save(reg8);
-		if (state) {
-			/* EBX in the state save contains the GNVS pointer */
-			gnvs = (struct global_nvs *)((uint32_t)state->rbx);
-			smm_initialized = 1;
-			printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
-		}
-		break;
 	case APM_CNT_SMMSTORE:
 		if (CONFIG(SMMSTORE))
 			southbridge_smi_store();

src/soc/intel/skylake/acpi.c

@@ -553,8 +553,6 @@ void southbridge_inject_dsdt(const struct device *device)
 
 	if (gnvs) {
 		acpi_create_gnvs(gnvs);
-		/* And tell SMI about it */
-		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT.  */
 		acpigen_write_scope("\\");

src/southbridge/intel/bd82x6x/lpc.c

@@ -659,8 +659,6 @@ void southbridge_inject_dsdt(const struct device *dev)
 		chromeos_init_chromeos_acpi(&(gnvs->chromeos));
 #endif
 
-		/* And tell SMI about it */
-		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT.  */
 		acpigen_write_scope("\\");

src/southbridge/intel/bd82x6x/smihandler.c

@@ -185,23 +185,6 @@ void southbridge_smm_xhci_sleep(u8 slp_type)
 		xhci_sleep(slp_type);
 }
 
-void southbridge_update_gnvs(u8 apm_cnt, int *smm_done)
-{
-	em64t101_smm_state_save_area_t *state =
-		smi_apmc_find_state_save(apm_cnt);
-	if (state) {
-		/* EBX in the state save contains the GNVS pointer */
-		gnvs = (struct global_nvs *)((u32)state->rbx);
-		struct region r = {(uintptr_t)gnvs, sizeof(struct global_nvs)};
-		if (smm_region_overlaps_handler(&r)) {
-			printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n");
-			return;
-		}
-		*smm_done = 1;
-		printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
-	}
-}
-
 void southbridge_finalize_all(void)
 {
 	intel_me_finalize_smm();

src/southbridge/intel/common/pmutil.h

@@ -4,7 +4,6 @@
 #define INTEL_COMMON_PMUTIL_H
 
 #include <cpu/x86/smm.h>
-#include <cpu/intel/em64t101_save_state.h>
 
 #define D31F0_PMBASE		0x40
 #define D31F0_GEN_PMCON_1	0xa0
@@ -129,10 +128,8 @@ void dump_all_status(void);
 void southbridge_smm_xhci_sleep(u8 slp_type);
 void gpi_route_interrupt(u8 gpi, u8 mode);
 void southbridge_gate_memory_reset(void);
-void southbridge_update_gnvs(u8 apm_cnt, int *smm_done);
 void southbridge_finalize_all(void);
 void southbridge_smi_monitor(void);
-em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd);
 void pch_log_state(void);
 
 #endif /*INTEL_COMMON_PMUTIL_H */

src/southbridge/intel/common/smihandler.c

@@ -17,8 +17,6 @@
 
 #include "pmutil.h"
 
-static int smm_initialized = 0;
-
 u16 get_pmbase(void)
 {
 	return lpc_get_pmbase();
@@ -198,7 +196,7 @@ static void southbridge_smi_sleep(void)
  * core in case we are not running on the same core that
  * initiated the IO transaction.
  */
-em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
+static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
 {
 	em64t101_smm_state_save_area_t *state;
 	int node;
@@ -302,14 +300,6 @@ static void southbridge_smi_apmc(void)
 		write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | SCI_EN);
 		printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
 		break;
-	case APM_CNT_GNVS_UPDATE:
-		if (smm_initialized) {
-			printk(BIOS_DEBUG,
-				"SMI#: SMM structures already initialized!\n");
-			return;
-		}
-		southbridge_update_gnvs(reg8, &smm_initialized);
-		break;
 	case APM_CNT_FINALIZE:
 		if (mainboard_finalized) {
 			printk(BIOS_DEBUG, "SMI#: Already finalized\n");

src/southbridge/intel/i82801gx/lpc.c

@@ -491,8 +491,6 @@ void southbridge_inject_dsdt(const struct device *dev)
 
 		acpi_create_gnvs(gnvs);
 
-		/* And tell SMI about it */
-		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to SSDT.  */
 		acpigen_write_scope("\\");

src/southbridge/intel/i82801gx/smihandler.c

@@ -19,11 +19,6 @@
 
 /* While we read PMBASE dynamically in case it changed, let's initialize it with a sane value */
 u16 pmbase = DEFAULT_PMBASE;
-u8 smm_initialized = 0;
-
-/* This implementation was removed since it was invalid. There will be one shared
-   approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */
-void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { }
 
 int southbridge_io_trap_handler(int smif)
 {

src/southbridge/intel/i82801ix/lpc.c

@@ -461,8 +461,6 @@ void southbridge_inject_dsdt(const struct device *dev)
 		memset(gnvs, 0, sizeof(*gnvs));
 		acpi_create_gnvs(gnvs);
 
-		/* And tell SMI about it */
-		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to SSDT.  */
 		acpigen_write_scope("\\");

src/southbridge/intel/i82801ix/smihandler.c

@@ -14,10 +14,6 @@
 struct global_nvs *gnvs;
 #endif
 
-/* This implementation was removed since it was invalid. There will be one shared
-   approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */
-void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { }
-
 int southbridge_io_trap_handler(int smif)
 {
 	switch (smif) {

src/southbridge/intel/i82801jx/lpc.c

@@ -485,8 +485,6 @@ void southbridge_inject_dsdt(const struct device *dev)
 		memset(gnvs, 0, sizeof(*gnvs));
 		acpi_create_gnvs(gnvs);
 
-		/* And tell SMI about it */
-		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to SSDT.  */
 		acpigen_write_scope("\\");

src/southbridge/intel/i82801jx/smihandler.c

@@ -13,11 +13,6 @@
  * initialize it with a sane value
  */
 u16 pmbase = DEFAULT_PMBASE;
-u8 smm_initialized = 0;
-
-/* This implementation was removed since it was invalid. There will be one shared
-   approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */
-void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { }
 
 int southbridge_io_trap_handler(int smif)
 {

src/southbridge/intel/ibexpeak/lpc.c

@@ -555,8 +555,6 @@ void southbridge_inject_dsdt(const struct device *dev)
 		gnvs->mpen = 1;		/* Enable Multi Processing */
 		gnvs->pcnt = dev_count_cpu();
 
-		/* And tell SMI about it */
-		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to SSDT.  */
 		acpigen_write_scope("\\");

src/southbridge/intel/ibexpeak/smihandler.c

@@ -147,22 +147,6 @@ void southbridge_smi_monitor(void)
 #undef IOTRAP
 }
 
-void southbridge_update_gnvs(u8 apm_cnt, int *smm_done)
-{
-	em64t101_smm_state_save_area_t *state =
-		smi_apmc_find_state_save(apm_cnt);
-	if (state) {
-		/* EBX in the state save contains the GNVS pointer */
-		gnvs = (struct global_nvs *)(uintptr_t)((u32)state->rbx);
-		if (smm_points_to_smram(gnvs, sizeof(*gnvs))) {
-			printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n");
-			return;
-		}
-		*smm_done = 1;
-		printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
-	}
-}
-
 void southbridge_finalize_all(void)
 {
 	intel_me_finalize_smm();

src/southbridge/intel/lynxpoint/lpc.c

@@ -712,8 +712,6 @@ void southbridge_inject_dsdt(const struct device *dev)
 		/* Update the mem console pointer. */
 		gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
 
-		/* And tell SMI about it */
-		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT.  */
 		acpigen_write_scope("\\");

src/southbridge/intel/lynxpoint/smihandler.c

@@ -19,8 +19,6 @@
 #include "pch.h"
 #include "nvs.h"
 
-static u8 smm_initialized = 0;
-
 int southbridge_io_trap_handler(int smif)
 {
 	switch (smif) {
@@ -262,7 +260,6 @@ static void southbridge_smi_store(void)
 static void southbridge_smi_apmc(void)
 {
 	u8 reg8;
-	em64t101_smm_state_save_area_t *state;
 	static int chipset_finalized = 0;
 
 	/* Emulate B2 register as the FADT / Linux expects it */
@@ -304,24 +301,6 @@ static void southbridge_smi_apmc(void)
 		enable_pm1_control(SCI_EN);
 		printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
 		break;
-	case APM_CNT_GNVS_UPDATE:
-		if (smm_initialized) {
-			printk(BIOS_DEBUG,
-			       "SMI#: SMM structures already initialized!\n");
-			return;
-		}
-		state = smi_apmc_find_state_save(reg8);
-		if (state) {
-			/* EBX in the state save contains the GNVS pointer */
-			gnvs = (struct global_nvs *)((u32)state->rbx);
-			if (smm_points_to_smram(gnvs, sizeof(*gnvs))) {
-				printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n");
-				return;
-			}
-			smm_initialized = 1;
-			printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
-		}
-		break;
 	case APM_CNT_ROUTE_ALL_XHCI:
 		usb_xhci_route_all();
 		break;