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rs780: hide unused gfx ports and gpp ports

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Hide the unused gfx ports and gpp ports if they are not configured as hotplug.
lspci -vvv will get more accurate information under Linux,
tested on avalue/eax-785e.

Change-Id: Iaabfd362a0a01f21d0f49aa2bd2d26f9259013fb
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/206
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Kerry Sheh 2011-09-14 10:04:19 +08:00 committed by Patrick Georgi
parent a25828dd0e
commit 8c69b1d13b
4 changed files with 20 additions and 1 deletions
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2
src/southbridge/amd/rs780/gfx.c
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@ -1009,6 +1009,7 @@ static void single_port_configuration(device_t nb_dev, device_t dev)
set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 3, 1 << 3); set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 3, 1 << 3);
} }
} else { /* step 13.b Link Training was successful */ } else { /* step 13.b Link Training was successful */
AtiPcieCfg.PortDetect |= 1 << 2; /* Port 2 */
set_pcie_enable_bits(dev, 0xA2, 0xFF, 0x1); set_pcie_enable_bits(dev, 0xA2, 0xFF, 0x1);
reg32 = nbpcie_p_read_index(dev, 0x29); reg32 = nbpcie_p_read_index(dev, 0x29);
width = reg32 & 0xFF; width = reg32 & 0xFF;
@ -1064,6 +1065,7 @@ static void dual_port_configuration(device_t nb_dev, device_t dev)
set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, 1 << dev_ind); set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, 1 << dev_ind);
} else { /* step 16.b Link Training was successful */ } else { /* step 16.b Link Training was successful */
AtiPcieCfg.PortDetect |= 1 << dev_ind;
reg32 = nbpcie_p_read_index(dev, 0xa2); reg32 = nbpcie_p_read_index(dev, 0xa2);
width = (reg32 >> 4) & 0x7; width = (reg32 >> 4) & 0x7;
printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width); printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);

13
src/southbridge/amd/rs780/pcie.c
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@ -390,3 +390,16 @@ void config_gpp_core(device_t nb_dev, device_t sb_dev)
switching_gpp_configurations(nb_dev, sb_dev); switching_gpp_configurations(nb_dev, sb_dev);
ValidatePortEn(nb_dev); ValidatePortEn(nb_dev);
} }
/**
* Hide unused Gpp port
*/
void pcie_hide_unused_ports(device_t nb_dev)
{
u16 hide = 0x6FC; /* skip port 0, 1, 8 */
hide &= ~(AtiPcieCfg.PortDetect | AtiPcieCfg.PortHp);
printk(BIOS_INFO, "rs780 unused GPP ports bitmap=0x%03x, force disabled\n", hide);
set_nbmisc_enable_bits(nb_dev, 0x0C, 0xFC, (hide & 0xFC)); /* bridge 2-7 */
set_nbmisc_enable_bits(nb_dev, 0x0C, 0x30000, ((hide >> 9) & 0x3) << 16); /* bridge 9-a */
}

5
src/southbridge/amd/rs780/rs780.c
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@ -362,7 +362,10 @@ void rs780_enable(device_t dev)
if (dev->enabled) if (dev->enabled)
rs780_gpp_sb_init(nb_dev, dev, dev_ind); rs780_gpp_sb_init(nb_dev, dev, dev_ind);
if (dev_ind == 10) disable_pcie_bar3(nb_dev); if (dev_ind == 10) {
disable_pcie_bar3(nb_dev);
pcie_hide_unused_ports(nb_dev);
}
break; break;
default: default:
printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev)); printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev));

1
src/southbridge/amd/rs780/rs780.h
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@ -213,4 +213,5 @@ u32 extractbits(u32 source, int lsb, int msb);
int cpuidFamily(void); int cpuidFamily(void);
int is_family0Fh(void); int is_family0Fh(void);
int is_family10h(void); int is_family10h(void);
void pcie_hide_unused_ports(device_t nb_dev);
#endif /* RS780_H */ #endif /* RS780_H */