libpayload: Add support for arm64 in libpayload
Basic support for arm64 is enabled in libpayload. Features added: 1) mem* operations in assembly. 2) Basic exception handling and support for testing exceptions. 3) Caching support. Tested with arm64-generic board compilation. BUG=None BRANCH=None TEST=Compilation successful Original-Change-Id: I4e86301f9c6383abc078e2b70071fb84bd6e4741 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/187067 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit a70d13f3d225535843ab352290eab2e1ec7a9b4b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie3affe6a2bdd4fed3058de739d4c6aa573e5b251 Reviewed-on: http://review.coreboot.org/8063 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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Furquan Shaikh
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Marc Jones
Marc Jones
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2445274347
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8c8c377584
146
payloads/libpayload/arch/arm64/exception_asm.S
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146
payloads/libpayload/arch/arm64/exception_asm.S
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/*
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* This file is part of the libpayload project.
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*
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* Copyright 2014 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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.text
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/* Macro for exception entry
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* Store x30 before any branch
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* Branch to exception_prologue to save rest of the registers
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* Move exception id into x1
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* Branch to exception_handler
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*/
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.macro eentry id
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stp x30, xzr, [sp, #-16]!
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bl exception_prologue
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mov x1, \id
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bl exception_handler
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.endm
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/* Exception table has 16 entries and each of 128 bytes
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* Hence, 16 * 128 = 2048. Thus, 11 passed as parameter
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* to align
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*/
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.align 11
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.global exception_table
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exception_table:
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.align 7
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sync_el0:
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eentry #0
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.align 7
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irq_el0:
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eentry #0
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.align 7
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fiq_el0:
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eentry #0
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.align 7
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serror_el0:
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eentry #0
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.align 7
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sync_elx:
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eentry #1
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.align 7
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irq_elx:
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eentry #2
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.align 7
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fiq_elx:
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eentry #3
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.align 7
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serror_elx:
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eentry #4
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exception_prologue:
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/* Save all registers x0-x29 */
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stp x28, x29, [sp, #-16]!
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stp x26, x27, [sp, #-16]!
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stp x24, x25, [sp, #-16]!
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stp x22, x23, [sp, #-16]!
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stp x20, x21, [sp, #-16]!
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stp x18, x19, [sp, #-16]!
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stp x16, x17, [sp, #-16]!
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stp x14, x15, [sp, #-16]!
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stp x12, x13, [sp, #-16]!
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stp x10, x11, [sp, #-16]!
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stp x8, x9, [sp, #-16]!
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stp x6, x7, [sp, #-16]!
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stp x4, x5, [sp, #-16]!
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stp x2, x3, [sp, #-16]!
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stp x0, x1, [sp, #-16]!
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/* Save the exception reason on stack */
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mrs x1, esr_el3
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/* Save the return address on stack */
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mrs x0, elr_el3
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stp x0, x1, [sp, #-16]!
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ret
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exception_handler:
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/* Save address of saved registers into x0
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* This acts as first argument to exception_dispatch
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*/
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mov x0, sp
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bl exception_dispatch
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/* Pop return address saved on stack */
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ldp x0, x1, [sp], #16
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/* Pop exception reason saved on stack, followed by regs x0-x30 */
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ldp x0, x1, [sp], #16
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ldp x2, x3, [sp], #16
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ldp x4, x5, [sp], #16
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ldp x6, x7, [sp], #16
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ldp x8, x9, [sp], #16
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ldp x10, x11, [sp], #16
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ldp x12, x13, [sp], #16
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ldp x14, x15, [sp], #16
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ldp x16, x17, [sp], #16
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ldp x18, x19, [sp], #16
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ldp x20, x21, [sp], #16
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ldp x22, x23, [sp], #16
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ldp x24, x25, [sp], #16
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ldp x26, x27, [sp], #16
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ldp x28, x29, [sp], #16
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ldp x30, xzr, [sp], #16
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eret
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.global set_vbar
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set_vbar:
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/* Initialize the exception table address in vbar for EL3 */
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/* FIXME: Do we need to initialize for other levels too? EL1/EL2 */
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msr vbar_el3, x0
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ret
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