libpayload: Add support for arm64 in libpayload
Basic support for arm64 is enabled in libpayload. Features added: 1) mem* operations in assembly. 2) Basic exception handling and support for testing exceptions. 3) Caching support. Tested with arm64-generic board compilation. BUG=None BRANCH=None TEST=Compilation successful Original-Change-Id: I4e86301f9c6383abc078e2b70071fb84bd6e4741 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/187067 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit a70d13f3d225535843ab352290eab2e1ec7a9b4b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie3affe6a2bdd4fed3058de739d4c6aa573e5b251 Reviewed-on: http://review.coreboot.org/8063 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Furquan Shaikh
committed by
Marc Jones
Marc Jones
parent
2445274347
commit
8c8c377584
242
payloads/libpayload/arch/arm64/memset.S
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242
payloads/libpayload/arch/arm64/memset.S
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/* Copyright (c) 2012-2013, Linaro Limited
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of the Linaro nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES ; LOSS OF USE,
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DATA, OR PROFITS ; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* Assumptions:
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*
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* ARMv8-a, AArch64
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* Unaligned accesses
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*
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*/
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/* By default we assume that the DC instruction can be used to zero
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data blocks more efficiently. In some circumstances this might be
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unsafe, for example in an asymmetric multiprocessor environment with
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different DC clear lengths (neither the upper nor lower lengths are
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safe to use). The feature can be disabled by defining DONT_USE_DC.
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If code may be run in a virtualized environment, then define
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MAYBE_VIRT. This will cause the code to cache the system register
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values rather than re-reading them each call. */
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#define dstin x0
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#define val w1
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#define count x2
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#define tmp1 x3
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#define tmp1w w3
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#define tmp2 x4
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#define tmp2w w4
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#define zva_len_x x5
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#define zva_len w5
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#define zva_bits_x x6
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#define A_l x7
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#define A_lw w7
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#define dst x8
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#define tmp3w w9
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.macro def_fn f p2align=0
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.text
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.p2align \p2align
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.global \f
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.type \f, %function
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\f:
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.endm
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def_fn memset p2align=6
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mov dst, dstin /* Preserve return value. */
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ands A_lw, val, #255
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#ifndef DONT_USE_DC
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b.eq .Lzero_mem
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#endif
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orr A_lw, A_lw, A_lw, lsl #8
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orr A_lw, A_lw, A_lw, lsl #16
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orr A_l, A_l, A_l, lsl #32
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.Ltail_maybe_long:
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cmp count, #64
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b.ge .Lnot_short
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.Ltail_maybe_tiny:
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cmp count, #15
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b.le .Ltail15tiny
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.Ltail63:
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ands tmp1, count, #0x30
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b.eq .Ltail15
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add dst, dst, tmp1
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cmp tmp1w, #0x20
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b.eq 1f
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b.lt 2f
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stp A_l, A_l, [dst, #-48]
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1:
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stp A_l, A_l, [dst, #-32]
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2:
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stp A_l, A_l, [dst, #-16]
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.Ltail15:
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and count, count, #15
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add dst, dst, count
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stp A_l, A_l, [dst, #-16] /* Repeat some/all of last store. */
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ret
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.Ltail15tiny:
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/* Set up to 15 bytes. Does not assume earlier memory
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being set. */
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tbz count, #3, 1f
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str A_l, [dst], #8
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1:
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tbz count, #2, 1f
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str A_lw, [dst], #4
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1:
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tbz count, #1, 1f
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strh A_lw, [dst], #2
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1:
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tbz count, #0, 1f
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strb A_lw, [dst]
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1:
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ret
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/* Critical loop. Start at a new cache line boundary. Assuming
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* 64 bytes per line, this ensures the entire loop is in one line. */
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.p2align 6
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.Lnot_short:
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neg tmp2, dst
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ands tmp2, tmp2, #15
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b.eq 2f
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/* Bring DST to 128-bit (16-byte) alignment. We know that there's
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* more than that to set, so we simply store 16 bytes and advance by
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* the amount required to reach alignment. */
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sub count, count, tmp2
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stp A_l, A_l, [dst]
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add dst, dst, tmp2
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/* There may be less than 63 bytes to go now. */
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cmp count, #63
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b.le .Ltail63
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2:
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sub dst, dst, #16 /* Pre-bias. */
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sub count, count, #64
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1:
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stp A_l, A_l, [dst, #16]
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stp A_l, A_l, [dst, #32]
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stp A_l, A_l, [dst, #48]
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stp A_l, A_l, [dst, #64]!
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subs count, count, #64
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b.ge 1b
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tst count, #0x3f
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add dst, dst, #16
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b.ne .Ltail63
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ret
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#ifndef DONT_USE_DC
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/* For zeroing memory, check to see if we can use the ZVA feature to
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* zero entire 'cache' lines. */
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.Lzero_mem:
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mov A_l, #0
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cmp count, #63
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b.le .Ltail_maybe_tiny
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neg tmp2, dst
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ands tmp2, tmp2, #15
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b.eq 1f
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sub count, count, tmp2
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stp A_l, A_l, [dst]
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add dst, dst, tmp2
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cmp count, #63
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b.le .Ltail63
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1:
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/* For zeroing small amounts of memory, it's not worth setting up
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* the line-clear code. */
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cmp count, #128
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b.lt .Lnot_short
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#ifdef MAYBE_VIRT
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/* For efficiency when virtualized, we cache the ZVA capability. */
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adrp tmp2, .Lcache_clear
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ldr zva_len, [tmp2, #:lo12:.Lcache_clear]
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tbnz zva_len, #31, .Lnot_short
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cbnz zva_len, .Lzero_by_line
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mrs tmp1, dczid_el0
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tbz tmp1, #4, 1f
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/* ZVA not available. Remember this for next time. */
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mov zva_len, #~0
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str zva_len, [tmp2, #:lo12:.Lcache_clear]
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b .Lnot_short
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1:
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mov tmp3w, #4
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and zva_len, tmp1w, #15 /* Safety: other bits reserved. */
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lsl zva_len, tmp3w, zva_len
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str zva_len, [tmp2, #:lo12:.Lcache_clear]
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#else
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mrs tmp1, dczid_el0
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tbnz tmp1, #4, .Lnot_short
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mov tmp3w, #4
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and zva_len, tmp1w, #15 /* Safety: other bits reserved. */
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lsl zva_len, tmp3w, zva_len
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#endif
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.Lzero_by_line:
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/* Compute how far we need to go to become suitably aligned. We're
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* already at quad-word alignment. */
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cmp count, zva_len_x
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b.lt .Lnot_short /* Not enough to reach alignment. */
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sub zva_bits_x, zva_len_x, #1
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neg tmp2, dst
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ands tmp2, tmp2, zva_bits_x
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b.eq 1f /* Already aligned. */
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/* Not aligned, check that there's enough to copy after alignment. */
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sub tmp1, count, tmp2
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cmp tmp1, #64
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ccmp tmp1, zva_len_x, #8, ge /* NZCV=0b1000 */
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b.lt .Lnot_short
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/* We know that there's at least 64 bytes to zero and that it's safe
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* to overrun by 64 bytes. */
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mov count, tmp1
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2:
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stp A_l, A_l, [dst]
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stp A_l, A_l, [dst, #16]
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stp A_l, A_l, [dst, #32]
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subs tmp2, tmp2, #64
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stp A_l, A_l, [dst, #48]
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add dst, dst, #64
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b.ge 2b
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/* We've overrun a bit, so adjust dst downwards. */
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add dst, dst, tmp2
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1:
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sub count, count, zva_len_x
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3:
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dc zva, dst
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add dst, dst, zva_len_x
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subs count, count, zva_len_x
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b.ge 3b
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ands count, count, zva_bits_x
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b.ne .Ltail_maybe_long
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ret
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.size memset, .-memset
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#ifdef MAYBE_VIRT
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.bss
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.p2align 2
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.Lcache_clear:
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.space 4
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#endif
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#endif /* DONT_USE_DC */
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