libpayload: Add support for arm64 in libpayload
Basic support for arm64 is enabled in libpayload. Features added: 1) mem* operations in assembly. 2) Basic exception handling and support for testing exceptions. 3) Caching support. Tested with arm64-generic board compilation. BUG=None BRANCH=None TEST=Compilation successful Original-Change-Id: I4e86301f9c6383abc078e2b70071fb84bd6e4741 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/187067 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit a70d13f3d225535843ab352290eab2e1ec7a9b4b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie3affe6a2bdd4fed3058de739d4c6aa573e5b251 Reviewed-on: http://review.coreboot.org/8063 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Furquan Shaikh
committed by
Marc Jones
Marc Jones
parent
2445274347
commit
8c8c377584
259
payloads/libpayload/include/arm64/arch/cache.h
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259
payloads/libpayload/include/arm64/arch/cache.h
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* cache.h: Cache maintenance API for ARM64
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*/
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#ifndef ARM64_CACHE_H
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#define ARM64_CACHE_H
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#include <stddef.h>
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#include <stdint.h>
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/* SCTLR bits */
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#define SCTLR_M (1 << 0) /* MMU enable */
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#define SCTLR_A (1 << 1) /* Alignment check enable */
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#define SCTLR_C (1 << 2) /* Data/unified cache enable */
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/* Bits 4:3 are reserved */
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#define SCTLR_CP15BEN (1 << 5) /* CP15 barrier enable */
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/* Bit 6 is reserved */
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#define SCTLR_B (1 << 7) /* Endianness */
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/* Bits 9:8 */
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#define SCTLR_SW (1 << 10) /* SWP and SWPB enable */
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#define SCTLR_Z (1 << 11) /* Branch prediction enable */
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#define SCTLR_I (1 << 12) /* Instruction cache enable */
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#define SCTLR_V (1 << 13) /* Low/high exception vectors */
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#define SCTLR_RR (1 << 14) /* Round Robin select */
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/* Bits 16:15 are reserved */
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#define SCTLR_HA (1 << 17) /* Hardware Access flag enable */
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/* Bit 18 is reserved */
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/* Bits 20:19 reserved virtualization not supported */
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#define SCTLR_WXN (1 << 19) /* Write permission implies XN */
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#define SCTLR_UWXN (1 << 20) /* Unprivileged write permission
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implies PL1 XN */
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#define SCTLR_FI (1 << 21) /* Fast interrupt config enable */
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#define SCTLR_U (1 << 22) /* Unaligned access behavior */
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#define SCTLR_VE (1 << 24) /* Interrupt vectors enable */
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#define SCTLR_EE (1 << 25) /* Exception endianness */
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/* Bit 26 is reserved */
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#define SCTLR_NMFI (1 << 27) /* Non-maskable FIQ support */
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#define SCTLR_TRE (1 << 28) /* TEX remap enable */
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#define SCTLR_AFE (1 << 29) /* Access flag enable */
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#define SCTLR_TE (1 << 30) /* Thumb exception enable */
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/* Bit 31 is reserved */
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/*
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* Sync primitives
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*/
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/* data memory barrier */
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static inline void dmb(void)
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{
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asm volatile ("dmb sy" : : : "memory");
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}
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/* data sync barrier */
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static inline void dsb(void)
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{
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asm volatile ("dsb sy" : : : "memory");
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}
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/* instruction sync barrier */
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static inline void isb(void)
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{
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asm volatile ("isb" : : : "memory");
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}
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/*
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* Low-level TLB maintenance operations
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*/
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/* invalidate entire unified TLB */
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static inline void tlbiall_el3(void)
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{
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asm volatile ("tlbi alle3" : : : "memory");
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}
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/* invalidate unified TLB by VA, all ASID */
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static inline void tlbivaa(unsigned long va)
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{
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asm volatile ("tlbi vaae1, %0" : : "r" (va) : "memory");
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}
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/*
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* Low-level cache maintenance operations
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*/
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/* data cache clean and invalidate by VA to PoC */
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static inline void dccivac(unsigned long va)
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{
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asm volatile ("dc civac, %0" : : "r" (va) : "memory");
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}
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/* data cache invalidate by set/way */
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static inline void dccisw(uint32_t val)
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{
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asm volatile ("dc cisw, %0" : : "r" (val) : "memory");
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}
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/* data cache clean by VA to PoC */
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static inline void dccvac(unsigned long va)
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{
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asm volatile ("dc cvac, %0" : : "r" (va) : "memory");
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}
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/* data cache clean by set/way */
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static inline void dccsw(uint32_t val)
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{
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asm volatile ("dc csw, %0" : : "r" (val) : "memory");
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}
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/* data cache invalidate by VA to PoC */
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static inline void dcivac(unsigned long va)
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{
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asm volatile ("dc ivac, %0" : : "r" (va) : "memory");
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}
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/* data cache invalidate by set/way */
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static inline void dcisw(uint32_t val)
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{
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asm volatile ("dc isw, %0" : : "r" (val) : "memory");
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}
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/* instruction cache invalidate all by PoU */
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static inline void iciallu(void)
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{
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asm volatile ("ic iallu" : : "r" (0));
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}
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/* read cache level ID register (CLIDR) */
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static inline uint32_t read_clidr(void)
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{
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uint32_t val = 0;
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asm volatile ("mrs %0, clidr_el1" : "=r" (val));
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return val;
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}
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/* read cache size ID register register (CCSIDR) */
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static inline uint32_t read_ccsidr(void)
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{
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uint32_t val = 0;
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asm volatile ("mrs %0, ccsidr_el1" : "=r" (val));
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return val;
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}
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/* read cache size selection register (CSSELR) */
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static inline uint32_t read_csselr(void)
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{
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uint32_t val = 0;
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asm volatile ("mrs %0, csselr_el1" : "=r" (val));
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return val;
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}
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/* write to cache size selection register (CSSELR) */
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static inline void write_csselr(uint32_t val)
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{
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/*
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* Bits [3:1] - Cache level + 1 (0b000 = L1, 0b110 = L7, 0b111 is rsvd)
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* Bit 0 - 0 = data or unified cache, 1 = instruction cache
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*/
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asm volatile ("msr csselr_el1, %0" : : "r" (val));
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isb(); /* ISB to sync the change to CCSIDR */
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}
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/* read system control register (SCTLR) */
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static inline uint32_t read_sctlr_el3(void)
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{
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uint32_t val;
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asm volatile ("mrs %0, sctlr_el3" : "=r" (val));
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return val;
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}
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/* write system control register (SCTLR) */
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static inline void write_sctlr_el3(uint32_t val)
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{
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asm volatile ("msr sctlr_el3, %0" : : "r" (val) : "cc");
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isb();
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}
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/*
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* Cache maintenance API
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*/
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/* dcache clean and invalidate all (on current level given by CCSELR) */
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void dcache_clean_invalidate_all(void);
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/* dcache clean by virtual address to PoC */
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void dcache_clean_by_va(void const *addr, size_t len);
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/* dcache clean and invalidate by virtual address to PoC */
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void dcache_clean_invalidate_by_va(void const *addr, size_t len);
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/* dcache invalidate by virtual address to PoC */
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void dcache_invalidate_by_va(void const *addr, size_t len);
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void dcache_clean_all(void);
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/* dcache invalidate all (on current level given by CCSELR) */
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void dcache_invalidate_all(void);
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/* returns number of bytes per cache line */
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unsigned int dcache_line_bytes(void);
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/* dcache and MMU disable */
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void dcache_mmu_disable(void);
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/* dcache and MMU enable */
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void dcache_mmu_enable(void);
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/* perform all icache/dcache maintenance needed after loading new code */
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void cache_sync_instructions(void);
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/* tlb invalidate all */
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void tlb_invalidate_all(void);
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/*
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* Generalized setup/init functions
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*/
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/* mmu initialization (set page table address, set permissions, etc) */
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void mmu_init(void);
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enum dcache_policy {
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DCACHE_OFF,
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DCACHE_WRITEBACK,
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DCACHE_WRITETHROUGH,
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};
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/* disable the mmu for a range. Primarily useful to lock out address 0. */
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void mmu_disable_range(unsigned long start_mb, unsigned long size_mb);
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/* mmu range configuration (set dcache policy) */
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void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
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enum dcache_policy policy);
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#endif /* ARM64_CACHE_H */
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