Documentation: Add cavium SoC and mainboard
* Add documentation for CN81XX SoC * Add documentation for CN81XX EVB SFF mainboard * Add documentation for BDK * Add documentation for BOOTROM and BOOTBLOCK behaviour * Alphabetically sort vendors Change-Id: Ibfcd42788e31f684baed658dc3c4dfe1b8e4f354 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Documentation/mainboard/cavium/cavium_cn81xx_sff_evb.jpg
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Documentation/mainboard/cavium/cn8100_sff_evb.md
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# CN81xx Evaluation-board SFF
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## Specs
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* 3 mini PCIe slots
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* 4 SATA ports
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* one USB3.0 A connector
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* 20Pin JTAG
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* 4 Gigabit Ethernet
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* 2 SFP+ connectors
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* PCIe x4 slot
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* UART over USB
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* eMMC Flash or MicroSD card slot for on-board storage
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* 1 Slot with DDR-4 memory with ECC support
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* SPI flash
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* MMC and uSD-card
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## Flashing coreboot
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```eval_rst
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+---------------------+----------------+
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| Type | Value |
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+=====================+================+
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| Socketed flash | no |
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+---------------------+----------------+
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| Model | Micron 25Q128A |
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+---------------------+----------------+
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| Size | 8 MiB |
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+---------------------+----------------+
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| In circuit flashing | no |
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+---------------------+----------------+
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| Package | SOIC-8 |
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+---------------------+----------------+
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| Write protection | No |
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+---------------------+----------------+
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| Dual BIOS feature | No |
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+---------------------+----------------+
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| Internal flashing | ? |
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+---------------------+----------------+
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```
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## Notes about the hardware
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1. Cavium connected *GPIO10* to a global reset line.
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It's unclear which chips are connected, but at least the PHY and SATA chips
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are connected.
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2. The 4 QLMs can be configured using DIP switches (SW1). That means only a
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subset of of the available connectors is working at time.
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3. The boot source can be configure using DIP switches (SW1).
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4. The core and system clock frequency can be configured using DIP switches
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(SW3 / SW2).
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5. The JTAG follows Cavium's own protocol. Support for it is missing in
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OpenOCD. You have to use ARMs official hardware and software.
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## Technology
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```eval_rst
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+---------------+----------------------------------------+
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| SoC | :doc:`../../soc/cavium/cn81xx/index` |
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+---------------+----------------------------------------+
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| CPU | Cavium ARMv8-Quadcore `CN81XX`_ |
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+---------------+----------------------------------------+
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.. _CN81XX: https://www.cavium.com/product-octeon-tx-cn80xx-81xx.html
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```
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## Picture
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![][cn81xx_board]
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[cn81xx_board]: cavium_cn81xx_sff_evb.jpg
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This section contains documentation about coreboot on specific mainboards.
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## SiFive
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## Cavium
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- [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)
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- [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
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## HP
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- [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)
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## SiFive
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- [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)
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