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arch/x86/ioapic: Drop irq_on_fsb as a configurable item

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APIC Serial Bus pins were removed with ICH5 already, so a choice
'irq_on_fsb = 0' would not take effect. The related register BOOT_CONFIG
0x3 is also not documented since ICH5.

For emulation/qemu-q35 with ICH9 the choice INTERRUPT_ON_APIC_BUS was
wrong and ignored as BOOT_CONFIG register emulation was never implemented.

For ICH4 and earlier, the choice to use FSB can be made based on the
installed CPU model but this is now just hardwired to match P4 CPUs of
aopen/dxplplusu.

For sb/intel/i82371eb register BOOT_CONFIG 0x3 is also not defined
and the only possible operation mode there is APIC Serial Bus, which
requires no configuration.

Change-Id: Id433e0e67cb83b44a3041250481f307b2ed1ad18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55257
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2021-06-06 08:14:57 +03:00
parent d614e85418
commit 8c9a89de99
18 changed files with 13 additions and 73 deletions
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8
src/arch/x86/Kconfig
View File

@@ -172,14 +172,6 @@ config CMOS_DEFAULT_FILE
default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
depends on HAVE_CMOS_DEFAULT
config IOAPIC_INTERRUPTS_ON_FSB
bool
default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
bool
default n
config HPET_ADDRESS_OVERRIDE
def_bool n

4
src/arch/x86/include/arch/ioapic.h
View File

@@ -34,8 +34,8 @@ u8 get_ioapic_version(void *ioapic_base);
void setup_ioapic(void *ioapic_base, u8 ioapic_id);
void clear_ioapic(void *ioapic_base);
void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool irq_on_fsb,
bool enable_virtual_wire);
void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb);
void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool enable_virtual_wire);
#endif
#endif

17
src/arch/x86/ioapic.c
View File

@@ -119,13 +119,8 @@ u8 get_ioapic_version(void *ioapic_base)
return io_apic_read(ioapic_base, 0x01) & 0xff;
}
void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool irq_on_fsb,
bool enable_virtual_wire)
void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb)
{
int first = 0, last;
set_ioapic_id(ioapic_base, ioapic_id);
if (irq_on_fsb) {
/*
* For the Pentium 4 and above APICs deliver their interrupts
@@ -139,6 +134,13 @@ void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool irq_on_fsb,
"IOAPIC: Enabling interrupts on APIC serial bus\n");
io_apic_write(ioapic_base, 0x03, 0);
}
}
void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool enable_virtual_wire)
{
int first = 0, last;
set_ioapic_id(ioapic_base, ioapic_id);
if (enable_virtual_wire) {
route_i8259_irq0(ioapic_base);
@@ -152,6 +154,5 @@ void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool irq_on_fsb,
void setup_ioapic(void *ioapic_base, u8 ioapic_id)
{
setup_ioapic_helper(ioapic_base, ioapic_id,
CONFIG(IOAPIC_INTERRUPTS_ON_FSB), true);
setup_ioapic_helper(ioapic_base, ioapic_id, true);
}