mb/google/nissa/yaviks: Tune eMMC DLL value for boot issue

Resolve boot issue by tuning RX HS50 and HS200.

BUG=b:265611305
TEST=Reboot test 2500 times pass

Change-Id: I8a2727dc0ce9dc86c6bfb6d85567afee1734db62
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75812
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
This commit is contained in:
Chia-Ling Hou
2023-06-13 13:54:54 +08:00
committed by Felix Held
parent 165cbe505a
commit 8c9ec5af53

View File

@@ -59,7 +59,7 @@ chip soc/intel/alderlake
# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B223b" register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B193b"
# EMMC RX CMD/DATA Delay 2 # EMMC RX CMD/DATA Delay 2
# Refer to EDS-Vol2-42.3.12. # Refer to EDS-Vol2-42.3.12.
@@ -70,7 +70,7 @@ chip soc/intel/alderlake
# 11: Reserved # 11: Reserved
# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004b" register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10004"
# EMMC Rx Strobe Delay # EMMC Rx Strobe Delay
# Refer to EDS-Vol2-42.3.11. # Refer to EDS-Vol2-42.3.11.