soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC

Add new folder and basic drivers for Mediatek SoC 'MT8196'.
Refer to MT8196_Chromebook_Application_Processor_Datasheet_V1.0 for
MT8196 SPEC detail.
This patch also enables UART and ARM arch timer.

TEST=saw the coreboot uart log to bootblock
BUG=b:317009620

Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

src/soc/mediatek/mt8196/Kconfig

@@ -0,0 +1,22 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config SOC_MEDIATEK_MT8196
+	bool
+	default n
+	select ARCH_BOOTBLOCK_ARMV8_64
+	select ARCH_VERSTAGE_ARMV8_64
+	select ARCH_ROMSTAGE_ARMV8_64
+	select ARCH_RAMSTAGE_ARMV8_64
+	select HAVE_UART_SPECIAL
+	select SOC_MEDIATEK_COMMON
+	select ARM64_USE_ARCH_TIMER
+
+if SOC_MEDIATEK_MT8196
+
+config VBOOT
+	select VBOOT_MUST_REQUEST_DISPLAY
+	select VBOOT_STARTS_IN_BOOTBLOCK
+	select VBOOT_SEPARATE_VERSTAGE
+	select VBOOT_RETURN_FROM_VERSTAGE
+
+endif

src/soc/mediatek/mt8196/Makefile.mk

@@ -0,0 +1,24 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ifeq ($(CONFIG_SOC_MEDIATEK_MT8196),y)
+
+all-$(CONFIG_SPI_FLASH) += spi.c
+all-y += timer.c
+all-y += ../common/uart.c
+
+bootblock-y += bootblock.c
+bootblock-y += ../common/mmu_operations.c
+
+romstage-y += ../common/cbmem.c
+romstage-y += emi.c
+
+ramstage-y += emi.c
+ramstage-y += soc.c
+
+CPPFLAGS_common += -Isrc/soc/mediatek/mt8196/include
+CPPFLAGS_common += -Isrc/soc/mediatek/common/include
+
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
+	./util/mtkheader/gen-bl-img.py mt8196 sf $< $@
+
+endif

src/soc/mediatek/mt8196/bootblock.c

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <soc/mmu_operations.h>
+
+void bootblock_soc_init(void)
+{
+	mtk_mmu_init();
+}

src/soc/mediatek/mt8196/emi.c

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8196 Functional Specification
+ * Chapter number: 10.2
+ */
+
+#include <soc/emi.h>
+
+size_t sdram_size(void)
+{
+	return (size_t)4 * GiB;
+}

src/soc/mediatek/mt8196/include/soc/addressmap.h

@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8196_INCLUDE_SOC_ADDRESSMAP_H__
+#define __SOC_MEDIATEK_MT8196_INCLUDE_SOC_ADDRESSMAP_H__
+
+enum {
+	MCUSYS_BASE		= 0x0C000000,
+	MCUPM_CFG_BASE		= 0x0C240000,
+	IO_PHYS			= 0x10000000,
+};
+
+enum {
+	MCUCFG_BASE		= MCUSYS_BASE,
+};
+
+enum {
+	CKSYS_BASE		= IO_PHYS + 0x00000000,
+	APMIXED_BASE		= IO_PHYS + 0x00000800,
+	INFRACFG_AO_BASE	= IO_PHYS + 0x00001000,
+	CKSYS_GP2_BASE		= IO_PHYS + 0x0000C000,
+	APMIXEDSYS_GP2_BASE	= IO_PHYS + 0x0000C800,
+	BCRM_INFRA_AO_BASE	= IO_PHYS + 0x00022000,
+	BCRM_INFRA1_AO_BASE	= IO_PHYS + 0x0002A000,
+	GPIO_BASE		= IO_PHYS + 0x0002D000,
+	DRAMC_CHA_AO_BASE	= IO_PHYS + 0x00230000,
+	EMI0_BASE		= IO_PHYS + 0x00469000,
+	EMI0_MPU_BASE		= IO_PHYS + 0x00468000,
+	EMI1_BASE		= IO_PHYS + 0x00569000,
+	DPM_PM_SRAM_BASE	= IO_PHYS + 0x00900000,
+	DPM_DM_SRAM_BASE	= IO_PHYS + 0x00920000,
+	DPM_CFG_BASE		= IO_PHYS + 0x00940000,
+	DPM_PM_SRAM_BASE2	= IO_PHYS + 0x00A00000,
+	DPM_DM_SRAM_BASE2	= IO_PHYS + 0x00A20000,
+	DPM_CFG_BASE2		= IO_PHYS + 0x00A40000,
+	IOCFG_RT_BASE		= IO_PHYS + 0x02000000,
+	IOCFG_RM1_BASE		= IO_PHYS + 0x02020000,
+	IOCFG_RM2_BASE		= IO_PHYS + 0x02040000,
+	IOCFG_RB_BASE		= IO_PHYS + 0x02060000,
+	IOCFG_BM1_BASE		= IO_PHYS + 0x02820000,
+	IOCFG_BM2_BASE		= IO_PHYS + 0x02840000,
+	IOCFG_BM3_BASE		= IO_PHYS + 0x02860000,
+	IOCFG_LT_BASE		= IO_PHYS + 0x03000000,
+	IOCFG_LM1_BASE		= IO_PHYS + 0x03020000,
+	IOCFG_LM2_BASE		= IO_PHYS + 0x03040000,
+	MIPITX0_BASE		= IO_PHYS + 0x030b0000,
+	IOCFG_LB1_BASE		= IO_PHYS + 0x030f0000,
+	IOCFG_LB2_BASE		= IO_PHYS + 0x03110000,
+	EFUSEC_BASE		= IO_PHYS + 0x03260000,
+	IOCFG_TM1_BASE		= IO_PHYS + 0x03800000,
+	IOCFG_TM2_BASE		= IO_PHYS + 0x03820000,
+	IOCFG_TM3_BASE		= IO_PHYS + 0x03860000,
+	THERM_CTRL_BASE		= IO_PHYS + 0x04414000,
+	UART0_BASE		= IO_PHYS + 0x06000000,
+	SPI0_BASE		= IO_PHYS + 0x06110000,
+	SPI1_BASE		= IO_PHYS + 0x06130000,
+	SPI2_BASE		= IO_PHYS + 0x06150000,
+	SPI3_BASE		= IO_PHYS + 0x06170000,
+	SPI4_BASE		= IO_PHYS + 0x06190000,
+	SPI5_BASE		= IO_PHYS + 0x061B0000,
+	SPI6_BASE		= IO_PHYS + 0x0619D000,
+	SPI7_BASE		= IO_PHYS + 0x061F0000,
+	SFLASH_REG_BASE		= IO_PHYS + 0x06340000,
+	PERICFG_AO_BASE		= IO_PHYS + 0x06640000,
+	SSUSB_IPPC_BASE		= IO_PHYS + 0x06703E00,
+	SSUSB_SIF_BASE		= IO_PHYS + 0x06730300,
+	UFSHCI_BASE		= IO_PHYS + 0x06810000,
+	SCP_BASE		= IO_PHYS + 0x0C004000,
+	SCP_PBUS_BASE		= IO_PHYS + 0x0C00D000,
+	RGU_BASE		= IO_PHYS + 0x0C010000,
+	GPT_BASE		= IO_PHYS + 0x0C015000,
+	PMIF_SPMI_P_BASE	= IO_PHYS + 0x0C018000,
+	PMIF_SPMI_BASE		= IO_PHYS + 0x0C01A000,
+	SPMI_MST_BASE		= IO_PHYS + 0x0C01C000,
+	SPMI_MST_P_BASE		= IO_PHYS + 0x0C01C800,
+	SYSTIMER_BASE		= IO_PHYS + 0x0C400000,
+	EINT_BASE		= IO_PHYS + 0x0C54A000,
+	DSI0_BASE		= IO_PHYS + 0x22490000,
+	DISP_DVO0		= IO_PHYS + 0x224C0000,
+	EDP_BASE		= IO_PHYS + 0x2EC40000,
+};
+
+#endif

src/soc/mediatek/mt8196/include/soc/emi.h

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8196 Functional Specification
+ * Chapter number: 10.2
+ */
+
+#ifndef SOC_MEDIATEK_MT8196_EMI_H
+#define SOC_MEDIATEK_MT8196_EMI_H
+
+#include <stddef.h>
+
+size_t sdram_size(void);
+
+#endif /* SOC_MEDIATEK_MT8196_EMI_H */

src/soc/mediatek/mt8196/include/soc/memlayout.ld

@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <soc/memlayout.h>
+
+SECTIONS
+{
+	/* MT8196 has 256KB SRAM. */
+	SRAM_START(0x00100000)
+	/* Regions that need to stay in SRAM. */
+	TTB(0x00100000, 28K)
+	DMA_COHERENT(0x00107000, 4K)
+	STACK(0x00108000, 15K)
+	WATCHDOG_TOMBSTONE(0x0010bc00, 4)
+	/* EMPTY(0x0010bc04, 29K - 4) */
+	/*
+	 * MCUPM exchanges data with kernel driver using SRAM 0x00113000 ~
+	 * 0x0011ffff. The address is hardcoded in MCUPM image.
+	 */
+	REGION(mcufw_reserved, 0x00113000, 52K, 4K)
+	/* End of regions that need to stay in SRAM. */
+	/* Regions can be moved to SRAM_L2C. */
+	CBFS_MCACHE(0x00120000, 16k)
+	VBOOT2_WORK(0x00124000, 12K)
+	FMAP_CACHE(0x00127000, 2k)
+	TPM_LOG(0x00127800, 2k)
+	TIMESTAMP(0x00128000, 1k)
+	/* End of regions that can also be moved to SRAM_L2C. */
+	/* EMPTY(0x00128400, 95K) */
+	SRAM_END(0x00140000)
+
+	/*
+	 * The L3 (can be used as SRAM_L2C) currently using is 2MB.
+	 * The BootROM has configured all cache as SRAM so we can't use them
+	 * unless if we disable L2C and reconfigure.
+	 */
+	SRAM_L2C_START(0x02000000)
+	#if ENV_ROMSTAGE
+	/*
+	 *  The needed size can be obtained by:
+	 *  aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz
+	 */
+	DRAM_INIT_CODE(0x02000000, 600K)
+	/* 4K reserved for BOOTROM until BOOTBLOCK is started */
+	#else
+	BOOTBLOCK(0x02001000, 60K)
+	#endif
+	OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x02096000, 272K)
+	PRERAM_CBFS_CACHE(0x020DA000, 48K)
+	PRERAM_CBMEM_CONSOLE(0x020E6000, 340K)
+	SRAM_L2C_END(0x02200000)
+
+	DRAM_START(0x80000000)
+	DRAM_DMA(0x80000000, 1M)
+	POSTRAM_CBFS_CACHE(0x80100000, 2M)
+	RAMSTAGE(0x80300000, 2M)
+
+	BL31(0x94600000, 0x200000)
+}

src/soc/mediatek/mt8196/include/soc/pll.h

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8196 Functional Specification
+ * Chapter number: 14.1
+ */
+
+#ifndef SOC_MEDIATEK_MT8196_PLL_H
+#define SOC_MEDIATEK_MT8196_PLL_H
+
+#include <soc/pll_common.h>
+
+/* top_div rate */
+enum {
+	CLK26M_HZ	= 26 * MHz,
+};
+
+/* top_mux rate */
+enum {
+	UART_HZ		= CLK26M_HZ,
+};
+
+#endif /* SOC_MEDIATEK_MT8196_PLL_H */

src/soc/mediatek/mt8196/include/soc/spi.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8196 Functional Specification
+ * Chapter number: 13.9
+ */
+
+#ifndef SOC_MEDIATEK_MT8196_SPI_H
+#define SOC_MEDIATEK_MT8196_SPI_H
+
+#include <spi-generic.h>
+
+#endif

src/soc/mediatek/mt8196/include/soc/timer.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8196 Functional Specification
+ * Chapter number: 5.13
+ */
+
+#ifndef SOC_MEDIATEK_MT8196_TIMER_H
+#define SOC_MEDIATEK_MT8196_TIMER_H
+
+#include <soc/timer_v2.h>
+
+#endif

src/soc/mediatek/mt8196/soc.c

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <soc/emi.h>
+#include <symbols.h>
+
+static void soc_read_resources(struct device *dev)
+{
+	ram_range(dev, 0, (uintptr_t)_dram, sdram_size());
+}
+
+static void soc_init(struct device *dev)
+{
+}
+
+static struct device_operations soc_ops = {
+	.read_resources = soc_read_resources,
+	.set_resources = noop_set_resources,
+	.init = soc_init,
+};
+
+static void enable_soc_dev(struct device *dev)
+{
+	dev->ops = &soc_ops;
+}
+
+struct chip_operations soc_mediatek_mt8196_ops = {
+	.name = "SOC Mediatek MT8196",
+	.enable_dev = enable_soc_dev,
+};

src/soc/mediatek/mt8196/spi.c

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8196 Functional Specification
+ * Chapter number: 13.9
+ */
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/spi.h>
+
+static const struct spi_ctrlr spi_flash_ctrlr = {
+	.max_xfer_size = 65535,
+};
+
+const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
+	{
+		.ctrlr = &spi_flash_ctrlr,
+	},
+};
+
+const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);

src/soc/mediatek/mt8196/timer.c

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/lib_helpers.h>
+#include <commonlib/helpers.h>
+#include <delay.h>
+
+void init_timer(void)
+{
+	raw_write_cntfrq_el0(13 * MHz);
+}