Intel: Replace MSR 0xcd with MSR_FSB_FREQ

And move the corresponding #define to speedstep.h

Change-Id: I8c884b8ab9ba54e01cfed7647a59deafeac94f2d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2339
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/cpu/intel/model_1067x/model_1067x_init.c

@@ -99,7 +99,6 @@ static void enable_vmx(void)
 }
 
 #define MSR_BBL_CR_CTL3		0x11e
-#define MSR_FSB_FREQ		0xcd
 
 static void configure_c_states(const int quad)
 {

src/cpu/intel/speedstep/acpi.c

@@ -67,7 +67,7 @@ static int determine_total_number_of_cores(void)
  */
 static int get_fsb(void)
 {
-	const u32 fsbcode = rdmsr(0xcd).lo & 7;
+	const u32 fsbcode = rdmsr(MSR_FSB_FREQ).lo & 7;
 	switch (fsbcode) {
 		case 0: return  800; /*  / 3 == 266 */
 		case 1: return  400; /*  / 3 == 133 */

src/cpu/x86/lapic/apic_timer.c

@@ -25,6 +25,7 @@
 #include <cpu/x86/car.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/lapic.h>
+#include <cpu/intel/speedstep.h>
 
 /* NOTE: This code uses global variables, so it can not be used during
  * memory init.
@@ -53,11 +54,11 @@ static int set_timer_fsb(void)
 	switch (c.x86_model) {
 	case 0xe:  /* Core Solo/Duo */
 	case 0x1c: /* Atom */
-		timer_fsb = core_fsb[rdmsr(0xcd).lo & 7];
+		timer_fsb = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
 		break;
 	case 0xf:  /* Core 2 or Xeon */
 	case 0x17: /* Enhanced Core */
-		timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7];
+		timer_fsb = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
 		break;
 	case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/
 	case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/