Intel: Replace MSR 0xcd with MSR_FSB_FREQ

And move the corresponding #define to speedstep.h

Change-Id: I8c884b8ab9ba54e01cfed7647a59deafeac94f2d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2339
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/cpu/intel/speedstep/acpi.c

@@ -67,7 +67,7 @@ static int determine_total_number_of_cores(void)
  */
 static int get_fsb(void)
 {
-	const u32 fsbcode = rdmsr(0xcd).lo & 7;
+	const u32 fsbcode = rdmsr(MSR_FSB_FREQ).lo & 7;
 	switch (fsbcode) {
 		case 0: return  800; /*  / 3 == 266 */
 		case 1: return  400; /*  / 3 == 133 */