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Intel: Replace MSR 0xcd with MSR_FSB_FREQ

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And move the corresponding #define to speedstep.h

Change-Id: I8c884b8ab9ba54e01cfed7647a59deafeac94f2d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2339
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Patrick Georgi
2013-02-09 15:56:04 +01:00
parent 3b19cbae37
commit 8cc8468971
10 changed files with 20 additions and 11 deletions
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5
src/cpu/x86/lapic/apic_timer.c
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@ -25,6 +25,7 @@
#include <cpu/x86/car.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
#include <cpu/intel/speedstep.h>
/* NOTE: This code uses global variables, so it can not be used during
* memory init.
@ -53,11 +54,11 @@ static int set_timer_fsb(void)
switch (c.x86_model) {
case 0xe: /* Core Solo/Duo */
case 0x1c: /* Atom */
timer_fsb = core_fsb[rdmsr(0xcd).lo & 7];
timer_fsb = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
break;
case 0xf: /* Core 2 or Xeon */
case 0x17: /* Enhanced Core */
timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7];
timer_fsb = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
break;
case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/
case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/