sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37168
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/southbridge/amd/agesa/hudson/bootblock.c

@@ -60,3 +60,48 @@ static void bootblock_southbridge_init(void)
 {
 	hudson_enable_rom();
 }
+
+
+#if !CONFIG(ROMCC_BOOTBLOCK)
+
+#include <bootblock_common.h>
+#include <amdblocks/acpimmio.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+
+void bootblock_soc_early_init(void)
+{
+	pci_devfn_t dev;
+	u32 data;
+
+	bootblock_southbridge_init();
+	hudson_lpc_decode();
+	enable_acpimmio_decode_pm24();
+
+	dev = PCI_DEV(0, 0x14, 3);
+	data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
+	/* enable 0x2e/0x4e IO decoding for SuperIO */
+	pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
+
+	/*
+	 * Enable FCH to decode TPM associated Memory and IO regions for vboot
+	 *
+	 * Enable decoding of TPM cycles defined in TPM 1.2 spec
+	 * Enable decoding of legacy TPM addresses: IO addresses 0x7f-
+	 * 0x7e and 0xef-0xee.
+	 */
+
+	data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE);
+	data |= TPM_12_EN | TPM_LEGACY_EN;
+	pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data);
+
+	/*
+	 *  In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
+	 *  LpcClk[1:0]".  This following register setting has been
+	 *  replicated in every reference design since Parmer, so it is
+	 *  believed to be required even though it is not documented in
+	 *  the SoC BKDGs.  Without this setting, there is no serial
+	 *  output.
+	 */
+	pm_write8(0xd2, 0);
+}
+#endif