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soc/amd/sabrina/acpi: Correct VID decoding on Sabrina

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Sabrina uses the SVI3 spec for VID tables which is incompatible with the
SVI2 spec used on PCO/CZN. Move the defines from common to soc and
update the decoding for sabrina.

See NDA docs #56413 for SVI3 and #48022 for SVI2 VID tables

TEST=timeless builds on mandolin/majolica for PCO/CZN
     build chausie and verify pstate power is correct in ACPI tables

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I915e962f11615246690c6be1bee3533336a808f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65001
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Fred Reitberger
2022-06-07 11:34:28 -04:00
committed by Marshall Dawson
parent ba08c4904d
commit 8d2bfbce23
5 changed files with 15 additions and 6 deletions
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4
src/soc/amd/picasso/include/soc/msr.h
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@@ -25,4 +25,8 @@
#define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT)
#define PSTATE_DEF_LO_CORE_FREQ_BASE 25
/* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */
#define SERIAL_VID_DECODE_MICROVOLTS 6250
#define SERIAL_VID_MAX_MICROVOLTS 1550000L
#endif /* AMD_PICASSO_MSR_H */