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changes to support new ppc arch

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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson
2005-10-20 01:44:21 +00:00
parent 58cb0bf1df
commit 8d4edc2fcd
9 changed files with 79 additions and 47 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/arch/ppc/include/board.h
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@@ -6,4 +6,5 @@
* happens prior to entry into hardwaremain().
*/
extern void board_init(void);
extern void board_init2(void);
#endif /* _BOARD_H */

12
src/arch/ppc/include/ppc74xx.h
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@@ -30,3 +30,15 @@
#define HID0_SGE 0x00000080
#define HID0_BTIC 0x00000020
#define HID0_BHT 0x00000004
/*----------------------------------------------------------------------------+
| Machine State Register. MSR_EE, MSR_PR, MSR_FP, MSR_ME, MSR_FE0, MSR_FE1,
+----------------------------------------------------------------------------*/
#define MSR_APE 0x00080000 /* wait state enable */
#define MSR_WE 0x00040000 /* wait state enable */
#define MSR_CE 0x00020000 /* critical interrupt enable */
#define MSR_DWE 0x00000400 /* debug wait enable */
#define MSR_DE 0x00000200 /* debug interrupt enable */
#define MSR_IR 0x00000020 /* instruction relocale */
#define MSR_DR 0x00000010 /* data relocale */

11
src/arch/ppc/include/ppc750.h
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@@ -31,3 +31,14 @@
#define HID0_BTIC 0x00000020
#define HID0_BHT 0x00000004
/*----------------------------------------------------------------------------+
| Machine State Register. MSR_EE, MSR_PR, MSR_FP, MSR_ME, MSR_FE0, MSR_FE1,
+----------------------------------------------------------------------------*/
#define MSR_APE 0x00080000 /* wait state enable */
#define MSR_WE 0x00040000 /* wait state enable */
#define MSR_CE 0x00020000 /* critical interrupt enable */
#define MSR_DWE 0x00000400 /* debug wait enable */
#define MSR_DE 0x00000200 /* debug interrupt enable */
#define MSR_IR 0x00000020 /* instruction relocale */
#define MSR_DR 0x00000010 /* data relocale */

2
src/arch/ppc/include/sdram.h
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@@ -5,5 +5,5 @@
* Provided for all PPC boards to do SDRAM initialization. This
* happens prior to entry into hardwaremain().
*/
extern void sdram_init(void);
extern void memory_init(void);
#endif /* _SDRAM_H */

4
src/arch/ppc/lib/Config.lb
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@@ -1,10 +1,10 @@
object c_start.S
object setup.o
object pci_ppc_conf1_ops.o
object pci_dev.o
object timer.o
object cpuid.o
object cpu.o
object ppc.o
object timebase.S
object floats.S
object div64.S
@@ -12,6 +12,6 @@ initobject pci_dev.o
initobject printk_init.o
initobject timebase.S
initobject timer.o
initobject setup.o
initobject floats.S
initobject div64.S
initobject ppc.o

49
src/arch/ppc/lib/ppc.c Normal file
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@@ -0,0 +1,49 @@
/* Copyright 2000 AG Electronics Ltd. */
/* This code is distributed without warranty under the GPL v2 (see COPYING) */
#include "ppc.h"
#include "ppcreg.h"
unsigned ppc_getmsr(void)
{
unsigned result;
__asm__ volatile ("mfmsr %0" : "=r" (result));
return result;
}
unsigned ppc_gethid0(void)
{
unsigned result;
__asm__ volatile ("mfspr %0,1008" : "=r" (result));
return result;
}
unsigned ppc_gethid1(void)
{
unsigned result;
__asm__ volatile ("mfspr %0,1009" : "=r" (result));
return result;
}
void ppc_sethid0(unsigned value)
{
__asm__ volatile ("mtspr 1008,%0" : : "r" (value));
}
unsigned ppc_getpvr(void)
{
unsigned result;
__asm__("mfspr %0, 287" : "=r" (result));
return result;
}
void ppc_setmsr(unsigned value)
{
__asm__ volatile ("mtmsr %0; sync" :: "r" (value));
}
void ppc_set1015(unsigned value)
{
__asm__ volatile ("mtspr 1015,%0" : : "r" (value));
}

130
src/arch/ppc/lib/setup.c
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@@ -1,130 +0,0 @@
/* Copyright 2000 AG Electronics Ltd. */
/* This code is distributed without warranty under the GPL v2 (see COPYING) */
#include "ppc.h"
#include "ppcreg.h"
unsigned ppc_getmsr(void)
{
unsigned result;
__asm__ volatile ("mfmsr %0" : "=r" (result));
return result;
}
unsigned ppc_gethid0(void)
{
unsigned result;
__asm__ volatile ("mfspr %0,1008" : "=r" (result));
return result;
}
unsigned ppc_gethid1(void)
{
unsigned result;
__asm__ volatile ("mfspr %0,1009" : "=r" (result));
return result;
}
void ppc_sethid0(unsigned value)
{
__asm__ volatile ("mtspr 1008,%0" : : "r" (value));
}
unsigned ppc_getpvr(void)
{
unsigned result;
__asm__("mfspr %0, 287" : "=r" (result));
return result;
}
void ppc_setmsr(unsigned value)
{
__asm__ volatile ("mtmsr %0; sync" :: "r" (value));
}
void ppc_set1015(unsigned value)
{
__asm__ volatile ("mtspr 1015,%0" : : "r" (value));
}
extern void ppc_init_float_registers(const double *);
/*RODATA static const double dummy_float = 1.0;*/
static const double dummy_float = 1.0;
#define HID0_DCACHE HID0_DCE
#define MSR_DATA MSR_DR
void ppc_setup_cpu(int icache)
{
int type = ppc_getpvr() >> 16;
int version = ppc_getpvr() & 0xffff;
if (type == 0xc)
{
if (version == 0x0200)
ppc_set1015(0x19000004);
else if (((version & 0xff00) == 0x0200) &&
(version != 0x0209))
ppc_set1015(0x01000000);
}
if (icache)
{
ppc_sethid0(HID0_NHR | HID0_BHT | HID0_ICE | HID0_ICFI
| HID0_BTIC | HID0_DCACHE);
ppc_sethid0(HID0_DPM | HID0_NHR | HID0_BHT | HID0_ICE
| HID0_BTIC | HID0_DCACHE);
}
else
{
ppc_sethid0(HID0_DPM | HID0_NHR | HID0_BHT | HID0_BTIC
| HID0_DCACHE);
}
#if 1
/* if (type == 8 || type == 12) */
{
ppc_setmsr(MSR_FP | MSR_DATA);
ppc_init_float_registers(&dummy_float);
}
#endif
}
void ppc_enable_dcache(void)
{
/*
* Already enabled in crt0.S
*/
#if 0
unsigned hid0 = ppc_gethid0();
ppc_sethid0(hid0 | HID0_DCFI | HID0_DCE);
ppc_sethid0(hid0 | HID0_DCE);
#endif
}
void ppc_disable_dcache(void)
{
unsigned hid0 = ppc_gethid0();
ppc_sethid0(hid0 & ~HID0_DCE);
}
void ppc_enable_mmu(void)
{
unsigned msr = ppc_getmsr();
ppc_setmsr(msr | MSR_DR | MSR_IR);
}
void make_coherent(void *base, unsigned length)
{
unsigned hid0 = ppc_gethid0();
if (hid0 & HID0_DCE)
{
unsigned i;
unsigned offset = 0x1f & (unsigned) base;
unsigned adjusted_base = (unsigned) base & ~0x1f;
for(i = 0; i < length + offset; i+= 32)
__asm__ volatile ("dcbf %1,%0" : : "r" (adjusted_base), "r" (i));
if (hid0 & HID0_ICE)
for(i = 0; i < length + offset; i+= 32)
__asm__ volatile ("icbi %1,%0" : : "r" (adjusted_base), "r" (i));
}
}