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Clean up whitespace in fam14 northbridge.c

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Change-Id: Id7947d7f3c67fdda67861065b1bc7a519b97208f
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/789
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
This commit is contained in:
Marc Jones
2012-03-15 12:55:26 -06:00
committed by Peter Stuge
parent 02bb57824c
commit 8d595698bf
1 changed files with 571 additions and 582 deletions
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317
src/northbridge/amd/agesa/family14/northbridge.c
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@@ -38,7 +38,6 @@
#include <sb_cimx.h> #include <sb_cimx.h>
#endif #endif
//#define FX_DEVS NODE_NUMS //#define FX_DEVS NODE_NUMS
#define FX_DEVS 1 #define FX_DEVS 1
@@ -46,32 +45,29 @@ static device_t __f0_dev[FX_DEVS];
static device_t __f1_dev[FX_DEVS]; static device_t __f1_dev[FX_DEVS];
static device_t __f2_dev[FX_DEVS]; static device_t __f2_dev[FX_DEVS];
static device_t __f4_dev[FX_DEVS]; static device_t __f4_dev[FX_DEVS];
static unsigned fx_devs=0; static unsigned fx_devs = 0;
device_t get_node_pci(u32 nodeid, u32 fn) device_t get_node_pci(u32 nodeid, u32 fn)
{ {
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
} }
static void get_fx_devs(void) static void get_fx_devs(void)
{ {
int i; int i;
for(i = 0; i < FX_DEVS; i++) { for (i = 0; i < FX_DEVS; i++) {
__f0_dev[i] = get_node_pci(i, 0); __f0_dev[i] = get_node_pci(i, 0);
__f1_dev[i] = get_node_pci(i, 1); __f1_dev[i] = get_node_pci(i, 1);
__f2_dev[i] = get_node_pci(i, 2); __f2_dev[i] = get_node_pci(i, 2);
__f4_dev[i] = get_node_pci(i, 4); __f4_dev[i] = get_node_pci(i, 4);
if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
fx_devs = i+1; fx_devs = i + 1;
} }
if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
die("Cannot find 0:0x18.[0|1]\n"); die("Cannot find 0:0x18.[0|1]\n");
} }
} }
static u32 f1_read_config32(unsigned reg) static u32 f1_read_config32(unsigned reg)
{ {
if (fx_devs == 0) if (fx_devs == 0)
@@ -79,13 +75,12 @@ static u32 f1_read_config32(unsigned reg)
return pci_read_config32(__f1_dev[0], reg); return pci_read_config32(__f1_dev[0], reg);
} }
static void f1_write_config32(unsigned reg, u32 value) static void f1_write_config32(unsigned reg, u32 value)
{ {
int i; int i;
if (fx_devs == 0) if (fx_devs == 0)
get_fx_devs(); get_fx_devs();
for(i = 0; i < fx_devs; i++) { for (i = 0; i < fx_devs; i++) {
device_t dev; device_t dev;
dev = __f1_dev[i]; dev = __f1_dev[i];
if (dev && dev->enabled) { if (dev && dev->enabled) {
@@ -94,34 +89,29 @@ static void f1_write_config32(unsigned reg, u32 value)
} }
} }
static u32 amdfam14_nodeid(device_t dev) static u32 amdfam14_nodeid(device_t dev)
{ {
return (dev->path.pci.devfn >> 3) - CONFIG_CDB; return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
} }
#include "amdfam14_conf.c" #include "amdfam14_conf.c"
static void northbridge_init(device_t dev) static void northbridge_init(device_t dev)
{ {
printk(BIOS_DEBUG, "Northbridge init\n"); printk(BIOS_DEBUG, "Northbridge init\n");
} }
static void set_vga_enable_reg(u32 nodeid, u32 linkn) static void set_vga_enable_reg(u32 nodeid, u32 linkn)
{ {
u32 val; u32 val;
val = 1 | (nodeid<<4) | (linkn<<12); val = 1 | (nodeid << 4) | (linkn << 12);
/* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb, /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb,
0x3c0:0x3df */ 0x3c0:0x3df */
f1_write_config32(0xf4, val); f1_write_config32(0xf4, val);
} }
static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
unsigned goal_link) unsigned goal_link)
{ {
@@ -129,28 +119,28 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
unsigned nodeid, link = 0; unsigned nodeid, link = 0;
int result; int result;
res = 0; res = 0;
for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
device_t dev; device_t dev;
dev = __f0_dev[nodeid]; dev = __f0_dev[nodeid];
if (!dev) if (!dev)
continue; continue;
for(link = 0; !res && (link < 8); link++) { for (link = 0; !res && (link < 8); link++) {
res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); res = probe_resource(dev, IOINDEX(0x1000 + reg, link));
} }
} }
result = 2; result = 2;
if (res) { if (res) {
result = 0; result = 0;
if ( (goal_link == (link - 1)) && if ((goal_link == (link - 1)) &&
(goal_nodeid == (nodeid - 1)) && (goal_nodeid == (nodeid - 1)) && (res->flags <= 1)) {
(res->flags <= 1)) {
result = 1; result = 1;
} }
} }
return result; return result;
} }
static struct resource *amdfam14_find_iopair(device_t dev, unsigned nodeid, unsigned link) static struct resource *amdfam14_find_iopair(device_t dev, unsigned nodeid,
unsigned link)
{ {
struct resource *resource; struct resource *resource;
u32 result, reg; u32 result, reg;
@@ -161,12 +151,14 @@ static struct resource *amdfam14_find_iopair(device_t dev, unsigned nodeid, unsi
/* I have been allocated this one */ /* I have been allocated this one */
reg = 0xc0; reg = 0xc0;
} }
/* Ext conf space */
//Ext conf space if (!reg) {
if(!reg) { /* Because of Extend conf space, we will never run out of reg,
//because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range * but we need one index to differ them. So ,same node and same
* link can have multi range
*/
u32 index = get_io_addr_index(nodeid, link); u32 index = get_io_addr_index(nodeid, link);
reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255 reg = 0x110 + (index << 24) + (4 << 20); // index could be 0, 255
} }
resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
@@ -174,20 +166,20 @@ static struct resource *amdfam14_find_iopair(device_t dev, unsigned nodeid, unsi
return resource; return resource;
} }
static struct resource *amdfam14_find_mempair(device_t dev, u32 nodeid, u32 link) static struct resource *amdfam14_find_mempair(device_t dev, u32 nodeid,
u32 link)
{ {
struct resource *resource; struct resource *resource;
u32 free_reg, reg; u32 free_reg, reg;
resource = 0; resource = 0;
free_reg = 0; free_reg = 0;
for(reg = 0x80; reg <= 0xb8; reg += 0x8) { for (reg = 0x80; reg <= 0xb8; reg += 0x8) {
int result; int result;
result = reg_useable(reg, dev, nodeid, link); result = reg_useable(reg, dev, nodeid, link);
if (result == 1) { if (result == 1) {
/* I have been allocated this one */ /* I have been allocated this one */
break; break;
} } else if (result > 1) {
else if (result > 1) {
/* I have a free register pair */ /* I have a free register pair */
free_reg = reg; free_reg = reg;
} }
@@ -195,21 +187,20 @@ static struct resource *amdfam14_find_mempair(device_t dev, u32 nodeid, u32 link
if (reg > 0xb8) { if (reg > 0xb8) {
reg = free_reg; reg = free_reg;
} }
/* Ext conf space */
//Ext conf space if (!reg) {
if(!reg) { /* Because of Extend conf space, we will never run out of reg,
//because of Extend conf space, we will never run out of reg, * but we need one index to differ them. So ,same node and same
// but we need one index to differ them. so same node and * link can have multi range
// same link can have multi range */
u32 index = get_mmio_addr_index(nodeid, link); u32 index = get_mmio_addr_index(nodeid, link);
reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63 reg = 0x110 + (index << 24) + (6 << 20); // index could be 0, 63
} }
resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
return resource; return resource;
} }
static void amdfam14_link_read_bases(device_t dev, u32 nodeid, u32 link) static void amdfam14_link_read_bases(device_t dev, u32 nodeid, u32 link)
{ {
struct resource *resource; struct resource *resource;
@@ -219,10 +210,9 @@ static void amdfam14_link_read_bases(device_t dev, u32 nodeid, u32 link)
if (resource) { if (resource) {
u32 align; u32 align;
#if CONFIG_EXT_CONF_SUPPORT == 1 #if CONFIG_EXT_CONF_SUPPORT == 1
if((resource->index & 0x1fff) == 0x1110) { // ext if ((resource->index & 0x1fff) == 0x1110) { // ext
align = 8; align = 8;
} } else
else
#endif #endif
align = log2(HT_IO_HOST_ALIGN); align = log2(HT_IO_HOST_ALIGN);
resource->base = 0; resource->base = 0;
@@ -245,7 +235,7 @@ static void amdfam14_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource->flags |= IORESOURCE_BRIDGE; resource->flags |= IORESOURCE_BRIDGE;
#if CONFIG_EXT_CONF_SUPPORT == 1 #if CONFIG_EXT_CONF_SUPPORT == 1
if((resource->index & 0x1fff) == 0x1110) { // ext if ((resource->index & 0x1fff) == 0x1110) { // ext
normalize_resource(resource); normalize_resource(resource);
} }
#endif #endif
@@ -262,7 +252,7 @@ static void amdfam14_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource->limit = 0xffffffffffULL; resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
#if CONFIG_EXT_CONF_SUPPORT == 1 #if CONFIG_EXT_CONF_SUPPORT == 1
if((resource->index & 0x1fff) == 0x1110) { // ext if ((resource->index & 0x1fff) == 0x1110) { // ext
normalize_resource(resource); normalize_resource(resource);
} }
#endif #endif
@@ -273,7 +263,8 @@ static u32 my_find_pci_tolm(struct bus *bus, u32 tolm)
{ {
struct resource *min; struct resource *min;
min = 0; min = 0;
search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test,
&min);
if (min && tolm > min->base) { if (min && tolm > min->base) {
tolm = min->base; tolm = min->base;
} }
@@ -297,32 +288,34 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
struct dram_base_mask_t d; struct dram_base_mask_t d;
u32 hole; u32 hole;
d = get_dram_base_mask(0); d = get_dram_base_mask(0);
if(d.mask & 1) { if (d.mask & 1) {
hole = pci_read_config32(__f1_dev[0], 0xf0); hole = pci_read_config32(__f1_dev[0], 0xf0);
if(hole & 1) { // we find the hole if (hole & 1) { // we find the hole
mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;
mem_hole.node_id = 0; // record the node No with hole mem_hole.node_id = 0; // record the node No with hole
} }
} }
#if 0 #if 0
// We need to double check if there is speical set on base reg and limit reg /* We need to double check if there is speical set on base reg and limit reg
// are not continous instead of hole, it will find out it's hole_startk * are not continous instead of hole, it will find out it's hole_startk
if(mem_hole.node_id==-1) { */
if (mem_hole.node_id == -1) {
resource_t limitk_pri = 0; resource_t limitk_pri = 0;
struct dram_base_mask_t d; struct dram_base_mask_t d;
resource_t base_k, limit_k; resource_t base_k, limit_k;
d = get_dram_base_mask(0); d = get_dram_base_mask(0);
if(d.base & 1) { if (d.base & 1) {
base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; base_k = ((resource_t) (d.base & 0x1fffff00)) << 9;
if(base_k <= 4 *1024 * 1024) { if (base_k <= 4 * 1024 * 1024) {
if(limitk_pri != base_k) { // we find the hole if (limitk_pri != base_k) { // we find the hole
mem_hole.hole_startk = (unsigned)limitk_pri; // must be below 4G mem_hole.hole_startk = (unsigned)limitk_pri; // must be below 4G
mem_hole.node_id = 0; mem_hole.node_id = 0;
} }
} }
limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; limit_k =
((resource_t) ((d.mask + 0x00000100) & 0x1fffff00))
<< 9;
limitk_pri = limit_k; limitk_pri = limit_k;
} }
} }
@@ -362,16 +355,14 @@ static void read_resources(device_t dev)
printk(BIOS_DEBUG, "\nFam14h - read_resources.\n"); printk(BIOS_DEBUG, "\nFam14h - read_resources.\n");
nodeid = amdfam14_nodeid(dev); nodeid = amdfam14_nodeid(dev);
for(link = dev->link_list; link; link = link->next) { for (link = dev->link_list; link; link = link->next) {
if (link->children) { if (link->children) {
amdfam14_link_read_bases(dev, nodeid, link->link_num); amdfam14_link_read_bases(dev, nodeid, link->link_num);
} }
} }
} }
static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
static void set_resource(device_t dev, struct resource *resource,
u32 nodeid)
{ {
resource_t rbase, rend; resource_t rbase, rend;
unsigned reg, link_num; unsigned reg, link_num;
@@ -408,18 +399,17 @@ static void set_resource(device_t dev, struct resource *resource,
link_num = IOINDEX_LINK(resource->index); link_num = IOINDEX_LINK(resource->index);
if (resource->flags & IORESOURCE_IO) { if (resource->flags & IORESOURCE_IO) {
set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); set_io_addr_reg(dev, nodeid, link_num, reg, rbase >> 8,
} rend >> 8);
else if (resource->flags & IORESOURCE_MEM) { } else if (resource->flags & IORESOURCE_MEM) {
set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, 1) ;// [39:8] set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >> 24),
rbase >> 8, rend >> 8, 1); // [39:8]
} }
resource->flags |= IORESOURCE_STORED; resource->flags |= IORESOURCE_STORED;
sprintf(buf, " <node %x link %x>", sprintf(buf, " <node %x link %x>", nodeid, link_num);
nodeid, link_num);
report_resource_stored(dev, resource, buf); report_resource_stored(dev, resource, buf);
} }
#if CONFIG_CONSOLE_VGA_MULTI #if CONFIG_CONSOLE_VGA_MULTI
extern device_t vga_pri; // the primary vga device, defined in device.c extern device_t vga_pri; // the primary vga device, defined in device.c
#endif #endif
@@ -435,12 +425,13 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
for (link = dev->link_list; link; link = link->next) { for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
#if CONFIG_CONSOLE_VGA_MULTI #if CONFIG_CONSOLE_VGA_MULTI
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, printk(BIOS_DEBUG,
link->secondary,link->subordinate); "VGA: vga_pri bus num = %d bus range [%d,%d]\n",
vga_pri->bus->secondary, link->secondary,
link->subordinate);
/* We need to make sure the vga_pri is under the link */ /* We need to make sure the vga_pri is under the link */
if((vga_pri->bus->secondary >= link->secondary ) && if ((vga_pri->bus->secondary >= link->secondary) &&
(vga_pri->bus->secondary <= link->subordinate ) (vga_pri->bus->secondary <= link->subordinate))
)
#endif #endif
break; break;
} }
@@ -450,11 +441,11 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
if (link == NULL) if (link == NULL)
return; return;
printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num); printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n",
dev_path(dev), nodeid, link->link_num);
set_vga_enable_reg(nodeid, link->link_num); set_vga_enable_reg(nodeid, link->link_num);
} }
static void set_resources(device_t dev) static void set_resources(device_t dev)
{ {
unsigned nodeid; unsigned nodeid;
@@ -469,18 +460,17 @@ static void set_resources(device_t dev)
create_vga_resource(dev, nodeid); create_vga_resource(dev, nodeid);
/* Set each resource we have found */ /* Set each resource we have found */
for(res = dev->resource_list; res; res = res->next) { for (res = dev->resource_list; res; res = res->next) {
set_resource(dev, res, nodeid); set_resource(dev, res, nodeid);
} }
for(bus = dev->link_list; bus; bus = bus->next) { for (bus = dev->link_list; bus; bus = bus->next) {
if (bus->children) { if (bus->children) {
assign_resources(bus); assign_resources(bus);
} }
} }
} }
/* Domain/Root Complex related code */ /* Domain/Root Complex related code */
static void domain_read_resources(device_t dev) static void domain_read_resources(device_t dev)
@@ -491,7 +481,7 @@ static void domain_read_resources(device_t dev)
/* Find the already assigned resource pairs */ /* Find the already assigned resource pairs */
get_fx_devs(); get_fx_devs();
for(reg = 0x80; reg <= 0xc0; reg+= 0x08) { for (reg = 0x80; reg <= 0xc0; reg += 0x08) {
u32 base, limit; u32 base, limit;
base = f1_read_config32(reg); base = f1_read_config32(reg);
limit = f1_read_config32(reg + 0x04); limit = f1_read_config32(reg + 0x04);
@@ -499,17 +489,20 @@ static void domain_read_resources(device_t dev)
if ((base & 3) != 0) { if ((base & 3) != 0) {
unsigned nodeid, reg_link; unsigned nodeid, reg_link;
device_t reg_dev; device_t reg_dev;
if(reg<0xc0) { // mmio if (reg < 0xc0) { // mmio
nodeid = (limit & 0xf) + (base&0x30); nodeid = (limit & 0xf) + (base & 0x30);
} else { // io } else { // io
nodeid = (limit & 0xf) + ((base>>4)&0x30); nodeid = (limit & 0xf) + ((base >> 4) & 0x30);
} }
reg_link = (limit >> 4) & 7; reg_link = (limit >> 4) & 7;
reg_dev = __f0_dev[nodeid]; reg_dev = __f0_dev[nodeid];
if (reg_dev) { if (reg_dev) {
/* Reserve the resource */ /* Reserve the resource */
struct resource *res; struct resource *res;
res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); res =
new_resource(reg_dev,
IOINDEX(0x1000 + reg,
reg_link));
if (res) { if (res) {
res->flags = 1; res->flags = 1;
} }
@@ -524,31 +517,30 @@ static void domain_read_resources(device_t dev)
#else #else
struct bus *link; struct bus *link;
struct resource *resource; struct resource *resource;
for(link=dev->link_list; link; link = link->next) { for (link = dev->link_list; link; link = link->next) {
/* Initialize the system wide io space constraints */ /* Initialize the system wide io space constraints */
resource = new_resource(dev, 0|(link->link_num<<2)); resource = new_resource(dev, 0 | (link->link_num << 2));
resource->base = 0x400; resource->base = 0x400;
resource->limit = 0xffffUL; resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO; resource->flags = IORESOURCE_IO;
/* Initialize the system wide prefetchable memory resources constraints */ /* Initialize the system wide prefetchable memory resources constraints */
resource = new_resource(dev, 1|(link->link_num<<2)); resource = new_resource(dev, 1 | (link->link_num << 2));
resource->limit = 0xfcffffffffULL; resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
/* Initialize the system wide memory resources constraints */ /* Initialize the system wide memory resources constraints */
resource = new_resource(dev, 2|(link->link_num<<2)); resource = new_resource(dev, 2 | (link->link_num << 2));
resource->limit = 0xfcffffffffULL; resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM; resource->flags = IORESOURCE_MEM;
} }
#endif #endif
} }
static void domain_set_resources(device_t dev) static void domain_set_resources(device_t dev)
{ {
printk(BIOS_DEBUG, "\nFam14h - domain_set_resources.\n"); printk(BIOS_DEBUG, "\nFam14h - domain_set_resources.\n");
printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n",(u32)dev); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev);
#if CONFIG_PCI_64BIT_PREF_MEM == 1 #if CONFIG_PCI_64BIT_PREF_MEM == 1
struct resource *io, *mem1, *mem2; struct resource *io, *mem1, *mem2;
@@ -565,23 +557,27 @@ static void domain_set_resources(device_t dev)
#if CONFIG_PCI_64BIT_PREF_MEM == 1 #if CONFIG_PCI_64BIT_PREF_MEM == 1
printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n"); printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n");
for(link = dev->link_list; link; link = link->next) { for (link = dev->link_list; link; link = link->next) {
/* Now reallocate the pci resources memory with the /* Now reallocate the pci resources memory with the
* highest addresses I can manage. * highest addresses I can manage.
*/ */
mem1 = find_resource(dev, 1|(link->link_num<<2)); mem1 = find_resource(dev, 1 | (link->link_num << 2));
mem2 = find_resource(dev, 2|(link->link_num<<2)); mem2 = find_resource(dev, 2 | (link->link_num << 2));
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", printk(BIOS_DEBUG,
(u32)(mem1->base), (u32)(mem1->limit), (u32)(mem1->size), u32)(mem1->align)); "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", (u32) (mem1->base), (u32) (mem1->limit),
(u32)(mem2->base), (u32)(mem2->limit), (u32)(mem2->size), (u32)(mem2->align)); (u32) (mem1->size), u32) (mem1->align));
printk(BIOS_DEBUG,
"base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
(u32) (mem2->base), (u32) (mem2->limit),
(u32) (mem2->size), (u32) (mem2->align));
/* See if both resources have roughly the same limits */ /* See if both resources have roughly the same limits */
if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff))
((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) || ((mem1->limit > 0xffffffff)
{ && (mem2->limit > 0xffffffff))) {
/* If so place the one with the most stringent alignment first /* If so place the one with the most stringent alignment first
*/ */
if (mem2->align > mem1->align) { if (mem2->align > mem1->align) {
@@ -594,21 +590,21 @@ printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n");
mem2->base = resource_max(mem2); mem2->base = resource_max(mem2);
mem1->limit = mem2->base - 1; mem1->limit = mem2->base - 1;
mem1->base = resource_max(mem1); mem1->base = resource_max(mem1);
} } else {
else {
/* Place the resources as high up as they will go */ /* Place the resources as high up as they will go */
mem2->base = resource_max(mem2); mem2->base = resource_max(mem2);
mem1->base = resource_max(mem1); mem1->base = resource_max(mem1);
} }
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", printk(BIOS_DEBUG,
"base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align); mem1->base, mem1->limit, mem1->size, mem1->align);
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", printk(BIOS_DEBUG,
"base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align); mem2->base, mem2->limit, mem2->size, mem2->align);
} }
for(res = &dev->resource_list; res; res = res->next) for (res = &dev->resource_list; res; res = res->next) {
{
res->flags |= IORESOURCE_ASSIGNED; res->flags |= IORESOURCE_ASSIGNED;
res->flags |= IORESOURCE_STORED; res->flags |= IORESOURCE_STORED;
report_resource_stored(dev, res, ""); report_resource_stored(dev, res, "");
@@ -616,7 +612,7 @@ printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n");
#endif #endif
pci_tolm = 0xffffffffUL; pci_tolm = 0xffffffffUL;
for(link = dev->link_list; link; link = link->next) { for (link = dev->link_list; link; link = link->next) {
pci_tolm = my_find_pci_tolm(link, pci_tolm); pci_tolm = my_find_pci_tolm(link, pci_tolm);
} }
@@ -624,12 +620,12 @@ printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n");
// amdk8, too. // amdk8, too.
mmio_basek = pci_tolm >> 10; mmio_basek = pci_tolm >> 10;
/* Round mmio_basek to something the processor can support */ /* Round mmio_basek to something the processor can support */
mmio_basek &= ~((1 << 6) -1); mmio_basek &= ~((1 << 6) - 1);
// FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
// MMIO hole. If you fix this here, please fix amdk8, too. // MMIO hole. If you fix this here, please fix amdk8, too.
/* Round the mmio hole to 64M */ /* Round the mmio hole to 64M */
mmio_basek &= ~((64*1024) - 1); mmio_basek &= ~((64 * 1024) - 1);
#if CONFIG_HW_MEM_HOLE_SIZEK != 0 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
/* if the hw mem hole is already set in raminit stage, here we will compare /* if the hw mem hole is already set in raminit stage, here we will compare
@@ -655,74 +651,83 @@ printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n");
d = get_dram_base_mask(0); d = get_dram_base_mask(0);
if (d.mask & 1) { if (d.mask & 1) {
basek = ((resource_t)((u64)d.base)) << 8; basek = ((resource_t) ((u64) d.base)) << 8;
limitk = (resource_t)(((u64)d.mask << 8) | 0xFFFFFF); limitk = (resource_t) (((u64) d.mask << 8) | 0xFFFFFF);
printk(BIOS_DEBUG, "adsr: (before) basek = %llx, limitk = %llx.\n",basek,limitk); printk(BIOS_DEBUG,
"adsr: (before) basek = %llx, limitk = %llx.\n", basek,
limitk);
/* Convert these values to multiples of 1K for ease of math. */ /* Convert these values to multiples of 1K for ease of math. */
basek >>= 10; basek >>= 10;
limitk >>= 10; limitk >>= 10;
sizek = limitk - basek + 1; sizek = limitk - basek + 1;
printk(BIOS_DEBUG, "adsr: (after) basek = %llx, limitk = %llx, sizek = %llx.\n",basek,limitk,sizek); printk(BIOS_DEBUG,
"adsr: (after) basek = %llx, limitk = %llx, sizek = %llx.\n",
basek, limitk, sizek);
/* see if we need a hole from 0xa0000 to 0xbffff */ /* see if we need a hole from 0xa0000 to 0xbffff */
if ((basek < 640) && (sizek > 768)) { if ((basek < 640) && (sizek > 768)) {
printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); printk(BIOS_DEBUG,"adsr - 0xa0000 to 0xbffff resource.\n");
ram_resource(dev, (idx | 0), basek, 640 - basek); ram_resource(dev, (idx | 0), basek, 640 - basek);
idx += 0x10; idx += 0x10;
basek = 768; basek = 768;
sizek = limitk - 768; sizek = limitk - 768;
} }
printk(BIOS_DEBUG,
printk(BIOS_DEBUG, "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", mmio_basek, basek, limitk); "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
mmio_basek, basek, limitk);
/* split the region to accomodate pci memory space */ /* split the region to accomodate pci memory space */
if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) {
if (basek <= mmio_basek) { if (basek <= mmio_basek) {
unsigned pre_sizek; unsigned pre_sizek;
pre_sizek = mmio_basek - basek; pre_sizek = mmio_basek - basek;
if(pre_sizek>0) { if (pre_sizek > 0) {
ram_resource(dev, idx, basek, pre_sizek); ram_resource(dev, idx, basek,
pre_sizek);
idx += 0x10; idx += 0x10;
sizek -= pre_sizek; sizek -= pre_sizek;
#if CONFIG_WRITE_HIGH_TABLES==1 #if CONFIG_WRITE_HIGH_TABLES==1
if (high_tables_base==0) { if (high_tables_base == 0) {
/* Leave some space for ACPI, PIRQ and MP tables */ /* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA == 1 #if CONFIG_GFXUMA == 1
high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); high_tables_base =
uma_memory_base -
(HIGH_TABLES_SIZE * 1024);
#else #else
high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
#endif #endif
high_tables_size = HIGH_TABLES_SIZE * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024;
printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE, printk(BIOS_DEBUG,
high_tables_base); " split: %dK table at =%08llx\n",
HIGH_TABLES_SIZE, high_tables_base);
} }
#endif #endif
} }
basek = mmio_basek; basek = mmio_basek;
} }
if ((basek + sizek) <= 4*1024*1024) { if ((basek + sizek) <= 4 * 1024 * 1024) {
sizek = 0; sizek = 0;
} } else {
else { basek = 4 * 1024 * 1024;
basek = 4*1024*1024; sizek -= (4 * 1024 * 1024 - mmio_basek);
sizek -= (4*1024*1024 - mmio_basek);
} }
} }
ram_resource(dev, (idx | 0), basek, sizek); ram_resource(dev, (idx | 0), basek, sizek);
idx += 0x10; idx += 0x10;
#if CONFIG_WRITE_HIGH_TABLES==1 #if CONFIG_WRITE_HIGH_TABLES==1
printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", printk(BIOS_DEBUG,
0, mmio_basek, basek, limitk); "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0,
if (high_tables_base==0) { mmio_basek, basek, limitk);
if (high_tables_base == 0) {
/* Leave some space for ACPI, PIRQ and MP tables */ /* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA == 1 #if CONFIG_GFXUMA == 1
high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx.\n",uma_memory_base); printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx.\n", uma_memory_base);
#else #else
high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024;
#endif #endif
@@ -730,25 +735,24 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", mmi
} }
#endif #endif
} }
printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n",mmio_basek); printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek);
printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n",high_tables_size); printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n",
high_tables_size);
#if CONFIG_GFXUMA == 1 #if CONFIG_GFXUMA == 1
printk(BIOS_DEBUG, "adsr - adding uma resource.\n"); printk(BIOS_DEBUG, "adsr - adding uma resource.\n");
add_uma_resource(dev, 7); add_uma_resource(dev, 7);
#endif #endif
for(link = dev->link_list; link; link = link->next) { for (link = dev->link_list; link; link = link->next) {
if (link->children) { if (link->children) {
assign_resources(link); assign_resources(link);
} }
} }
printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n");
} }
static void domain_enable_resources(device_t dev) {
static void domain_enable_resources(device_t dev)
{
u32 val; u32 val;
#if CONFIG_AMD_SB_CIMX #if CONFIG_AMD_SB_CIMX
@@ -758,33 +762,29 @@ static void domain_enable_resources(device_t dev)
/* Must be called after PCI enumeration and resource allocation */ /* Must be called after PCI enumeration and resource allocation */
printk(BIOS_DEBUG, "\nFam14h - domain_enable_resources: AmdInitMid.\n"); printk(BIOS_DEBUG, "\nFam14h - domain_enable_resources: AmdInitMid.\n");
val = agesawrapper_amdinitmid (); val = agesawrapper_amdinitmid();
if(val) { if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val); printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val);
} }
printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n");
} }
/* Bus related code */ /* Bus related code */
static void cpu_bus_read_resources(device_t dev) {
static void cpu_bus_read_resources(device_t dev)
{
printk(BIOS_DEBUG, "\nFam14h - cpu_bus_read_resources.\n"); printk(BIOS_DEBUG, "\nFam14h - cpu_bus_read_resources.\n");
#if CONFIG_MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
struct resource *resource = new_resource(dev, 0xc0010058); struct resource *resource = new_resource(dev, 0xc0010058);
resource->base = CONFIG_MMCONF_BASE_ADDRESS; resource->base = CONFIG_MMCONF_BASE_ADDRESS;
resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
#endif #endif
} }
static void cpu_bus_set_resources(device_t dev) static void cpu_bus_set_resources(device_t dev) {
{
struct resource *resource = find_resource(dev, 0xc0010058); struct resource *resource = find_resource(dev, 0xc0010058);
printk(BIOS_DEBUG, "\nFam14h - cpu_bus_set_resources.\n"); printk(BIOS_DEBUG, "\nFam14h - cpu_bus_set_resources.\n");
@@ -795,8 +795,7 @@ static void cpu_bus_set_resources(device_t dev)
pci_dev_set_resources(dev); pci_dev_set_resources(dev);
} }
static void cpu_bus_init(device_t dev) static void cpu_bus_init(device_t dev) {
{
struct device_path cpu_path; struct device_path cpu_path;
device_t cpu; device_t cpu;
int apic_id; int apic_id;
@@ -808,14 +807,14 @@ static void cpu_bus_init(device_t dev)
cpu_path.type = DEVICE_PATH_APIC; cpu_path.type = DEVICE_PATH_APIC;
cpu_path.apic.apic_id = apic_id; cpu_path.apic.apic_id = apic_id;
cpu = alloc_dev(dev->link_list, &cpu_path); cpu = alloc_dev(dev->link_list, &cpu_path);
if (!cpu) return; if (!cpu)
return;
cpu->enabled = 1; cpu->enabled = 1;
cpu->path.apic.node_id = 0; cpu->path.apic.node_id = 0;
cpu->path.apic.core_id = apic_id; cpu->path.apic.core_id = apic_id;
} }
} }
/* North Bridge Structures */ /* North Bridge Structures */
static struct device_operations northbridge_operations = { static struct device_operations northbridge_operations = {
@@ -823,27 +822,22 @@ static struct device_operations northbridge_operations = {
.set_resources = set_resources, .set_resources = set_resources,
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
.init = northbridge_init, .init = northbridge_init,
.enable = 0, .enable = 0,.ops_pci = 0,
.ops_pci = 0,
}; };
static const struct pci_driver northbridge_driver __pci_driver = { static const struct pci_driver northbridge_driver __pci_driver = {
.ops = &northbridge_operations, .ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_AMD, .vendor = PCI_VENDOR_ID_AMD,
.device = 0x1510, .device = 0x1510,
}; };
struct chip_operations northbridge_amd_agesa_family14_ops = { struct chip_operations northbridge_amd_agesa_family14_ops = {
CHIP_NAME("AMD Family 14h Northbridge") CHIP_NAME("AMD Family 14h Northbridge")
.enable_dev = 0, .enable_dev = 0,
}; };
/* Root Complex Structures */ /* Root Complex Structures */
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
.read_resources = domain_read_resources, .read_resources = domain_read_resources,
.set_resources = domain_set_resources, .set_resources = domain_set_resources,
@@ -852,7 +846,6 @@ static struct device_operations pci_domain_ops = {
.scan_bus = pci_domain_scan_bus, .scan_bus = pci_domain_scan_bus,
}; };
static struct device_operations cpu_bus_ops = { static struct device_operations cpu_bus_ops = {
.read_resources = cpu_bus_read_resources, .read_resources = cpu_bus_read_resources,
.set_resources = cpu_bus_set_resources, .set_resources = cpu_bus_set_resources,
@@ -861,19 +854,15 @@ static struct device_operations cpu_bus_ops = {
.scan_bus = NULL, .scan_bus = NULL,
}; };
static void root_complex_enable_dev(struct device *dev) {
static void root_complex_enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */ /* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
dev->ops = &pci_domain_ops; dev->ops = &pci_domain_ops;
} } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
dev->ops = &cpu_bus_ops; dev->ops = &cpu_bus_ops;
} }
} }
struct chip_operations northbridge_amd_agesa_family14_root_complex_ops = { struct chip_operations northbridge_amd_agesa_family14_root_complex_ops = {
CHIP_NAME("AMD Family 14h Root Complex") CHIP_NAME("AMD Family 14h Root Complex")
.enable_dev = root_complex_enable_dev, .enable_dev = root_complex_enable_dev,