Clean up whitespace in fam14 northbridge.c
Change-Id: Id7947d7f3c67fdda67861065b1bc7a519b97208f Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/789 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
This commit is contained in:
Marc Jones
Peter Stuge
@@ -38,7 +38,6 @@
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#include <sb_cimx.h>
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#endif
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//#define FX_DEVS NODE_NUMS
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#define FX_DEVS 1
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@@ -48,13 +47,11 @@ static device_t __f2_dev[FX_DEVS];
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static device_t __f4_dev[FX_DEVS];
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static unsigned fx_devs = 0;
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device_t get_node_pci(u32 nodeid, u32 fn)
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{
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return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
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}
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static void get_fx_devs(void)
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{
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int i;
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@@ -71,7 +68,6 @@ static void get_fx_devs(void)
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}
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}
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static u32 f1_read_config32(unsigned reg)
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{
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if (fx_devs == 0)
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@@ -79,7 +75,6 @@ static u32 f1_read_config32(unsigned reg)
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return pci_read_config32(__f1_dev[0], reg);
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}
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static void f1_write_config32(unsigned reg, u32 value)
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{
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int i;
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@@ -94,22 +89,18 @@ static void f1_write_config32(unsigned reg, u32 value)
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}
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}
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static u32 amdfam14_nodeid(device_t dev)
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{
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return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
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}
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#include "amdfam14_conf.c"
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static void northbridge_init(device_t dev)
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{
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printk(BIOS_DEBUG, "Northbridge init\n");
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}
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static void set_vga_enable_reg(u32 nodeid, u32 linkn)
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{
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u32 val;
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@@ -121,7 +112,6 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)
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}
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static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
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unsigned goal_link)
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{
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@@ -142,15 +132,15 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
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if (res) {
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result = 0;
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if ((goal_link == (link - 1)) &&
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(goal_nodeid == (nodeid - 1)) &&
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(res->flags <= 1)) {
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(goal_nodeid == (nodeid - 1)) && (res->flags <= 1)) {
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result = 1;
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}
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}
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return result;
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}
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static struct resource *amdfam14_find_iopair(device_t dev, unsigned nodeid, unsigned link)
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static struct resource *amdfam14_find_iopair(device_t dev, unsigned nodeid,
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unsigned link)
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{
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struct resource *resource;
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u32 result, reg;
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@@ -161,10 +151,12 @@ static struct resource *amdfam14_find_iopair(device_t dev, unsigned nodeid, unsi
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/* I have been allocated this one */
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reg = 0xc0;
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}
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//Ext conf space
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/* Ext conf space */
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if (!reg) {
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//because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range
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/* Because of Extend conf space, we will never run out of reg,
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* but we need one index to differ them. So ,same node and same
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* link can have multi range
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*/
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u32 index = get_io_addr_index(nodeid, link);
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reg = 0x110 + (index << 24) + (4 << 20); // index could be 0, 255
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}
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@@ -174,7 +166,8 @@ static struct resource *amdfam14_find_iopair(device_t dev, unsigned nodeid, unsi
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return resource;
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}
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static struct resource *amdfam14_find_mempair(device_t dev, u32 nodeid, u32 link)
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static struct resource *amdfam14_find_mempair(device_t dev, u32 nodeid,
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u32 link)
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{
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struct resource *resource;
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u32 free_reg, reg;
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@@ -186,8 +179,7 @@ static struct resource *amdfam14_find_mempair(device_t dev, u32 nodeid, u32 link
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if (result == 1) {
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/* I have been allocated this one */
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break;
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}
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else if (result > 1) {
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} else if (result > 1) {
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/* I have a free register pair */
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free_reg = reg;
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}
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@@ -195,12 +187,12 @@ static struct resource *amdfam14_find_mempair(device_t dev, u32 nodeid, u32 link
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if (reg > 0xb8) {
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reg = free_reg;
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}
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//Ext conf space
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/* Ext conf space */
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if (!reg) {
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//because of Extend conf space, we will never run out of reg,
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// but we need one index to differ them. so same node and
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// same link can have multi range
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/* Because of Extend conf space, we will never run out of reg,
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* but we need one index to differ them. So ,same node and same
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* link can have multi range
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*/
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u32 index = get_mmio_addr_index(nodeid, link);
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reg = 0x110 + (index << 24) + (6 << 20); // index could be 0, 63
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@@ -209,7 +201,6 @@ static struct resource *amdfam14_find_mempair(device_t dev, u32 nodeid, u32 link
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return resource;
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}
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static void amdfam14_link_read_bases(device_t dev, u32 nodeid, u32 link)
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{
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struct resource *resource;
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@@ -221,8 +212,7 @@ static void amdfam14_link_read_bases(device_t dev, u32 nodeid, u32 link)
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#if CONFIG_EXT_CONF_SUPPORT == 1
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if ((resource->index & 0x1fff) == 0x1110) { // ext
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align = 8;
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}
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else
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} else
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#endif
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align = log2(HT_IO_HOST_ALIGN);
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resource->base = 0;
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@@ -273,7 +263,8 @@ static u32 my_find_pci_tolm(struct bus *bus, u32 tolm)
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{
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struct resource *min;
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min = 0;
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search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
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search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test,
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&min);
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if (min && tolm > min->base) {
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tolm = min->base;
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}
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@@ -304,10 +295,10 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
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mem_hole.node_id = 0; // record the node No with hole
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}
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}
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#if 0
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// We need to double check if there is speical set on base reg and limit reg
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// are not continous instead of hole, it will find out it's hole_startk
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/* We need to double check if there is speical set on base reg and limit reg
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* are not continous instead of hole, it will find out it's hole_startk
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*/
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if (mem_hole.node_id == -1) {
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resource_t limitk_pri = 0;
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struct dram_base_mask_t d;
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@@ -322,7 +313,9 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
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}
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}
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limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9;
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limit_k =
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((resource_t) ((d.mask + 0x00000100) & 0x1fffff00))
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<< 9;
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limitk_pri = limit_k;
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}
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}
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@@ -369,9 +362,7 @@ static void read_resources(device_t dev)
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}
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}
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static void set_resource(device_t dev, struct resource *resource,
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u32 nodeid)
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static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
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{
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resource_t rbase, rend;
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unsigned reg, link_num;
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@@ -408,18 +399,17 @@ static void set_resource(device_t dev, struct resource *resource,
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link_num = IOINDEX_LINK(resource->index);
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if (resource->flags & IORESOURCE_IO) {
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set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8);
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}
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else if (resource->flags & IORESOURCE_MEM) {
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set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, 1) ;// [39:8]
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set_io_addr_reg(dev, nodeid, link_num, reg, rbase >> 8,
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rend >> 8);
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} else if (resource->flags & IORESOURCE_MEM) {
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set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >> 24),
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rbase >> 8, rend >> 8, 1); // [39:8]
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}
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resource->flags |= IORESOURCE_STORED;
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sprintf(buf, " <node %x link %x>",
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nodeid, link_num);
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sprintf(buf, " <node %x link %x>", nodeid, link_num);
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report_resource_stored(dev, resource, buf);
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}
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#if CONFIG_CONSOLE_VGA_MULTI
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extern device_t vga_pri; // the primary vga device, defined in device.c
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#endif
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@@ -435,12 +425,13 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
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for (link = dev->link_list; link; link = link->next) {
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if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
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#if CONFIG_CONSOLE_VGA_MULTI
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printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
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link->secondary,link->subordinate);
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printk(BIOS_DEBUG,
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"VGA: vga_pri bus num = %d bus range [%d,%d]\n",
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vga_pri->bus->secondary, link->secondary,
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link->subordinate);
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/* We need to make sure the vga_pri is under the link */
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if ((vga_pri->bus->secondary >= link->secondary) &&
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(vga_pri->bus->secondary <= link->subordinate )
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)
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(vga_pri->bus->secondary <= link->subordinate))
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#endif
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break;
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}
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@@ -450,11 +441,11 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
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if (link == NULL)
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return;
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printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num);
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printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n",
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dev_path(dev), nodeid, link->link_num);
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set_vga_enable_reg(nodeid, link->link_num);
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}
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static void set_resources(device_t dev)
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{
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unsigned nodeid;
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@@ -480,7 +471,6 @@ static void set_resources(device_t dev)
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}
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}
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/* Domain/Root Complex related code */
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static void domain_read_resources(device_t dev)
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@@ -509,7 +499,10 @@ static void domain_read_resources(device_t dev)
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if (reg_dev) {
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/* Reserve the resource */
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struct resource *res;
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res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link));
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res =
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new_resource(reg_dev,
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IOINDEX(0x1000 + reg,
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reg_link));
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if (res) {
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res->flags = 1;
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}
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@@ -544,7 +537,6 @@ static void domain_read_resources(device_t dev)
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#endif
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}
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static void domain_set_resources(device_t dev)
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{
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printk(BIOS_DEBUG, "\nFam14h - domain_set_resources.\n");
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@@ -573,15 +565,19 @@ printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n");
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mem1 = find_resource(dev, 1 | (link->link_num << 2));
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mem2 = find_resource(dev, 2 | (link->link_num << 2));
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printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
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(u32)(mem1->base), (u32)(mem1->limit), (u32)(mem1->size), u32)(mem1->align));
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printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
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(u32)(mem2->base), (u32)(mem2->limit), (u32)(mem2->size), (u32)(mem2->align));
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printk(BIOS_DEBUG,
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"base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
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(u32) (mem1->base), (u32) (mem1->limit),
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(u32) (mem1->size), u32) (mem1->align));
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printk(BIOS_DEBUG,
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"base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
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(u32) (mem2->base), (u32) (mem2->limit),
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(u32) (mem2->size), (u32) (mem2->align));
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/* See if both resources have roughly the same limits */
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if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
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((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
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{
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if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff))
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|| ((mem1->limit > 0xffffffff)
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&& (mem2->limit > 0xffffffff))) {
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/* If so place the one with the most stringent alignment first
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*/
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if (mem2->align > mem1->align) {
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@@ -594,21 +590,21 @@ printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n");
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mem2->base = resource_max(mem2);
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mem1->limit = mem2->base - 1;
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mem1->base = resource_max(mem1);
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}
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else {
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} else {
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/* Place the resources as high up as they will go */
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mem2->base = resource_max(mem2);
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mem1->base = resource_max(mem1);
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}
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printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
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printk(BIOS_DEBUG,
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"base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
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mem1->base, mem1->limit, mem1->size, mem1->align);
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printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
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printk(BIOS_DEBUG,
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"base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
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mem2->base, mem2->limit, mem2->size, mem2->align);
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}
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for(res = &dev->resource_list; res; res = res->next)
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{
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for (res = &dev->resource_list; res; res = res->next) {
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res->flags |= IORESOURCE_ASSIGNED;
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res->flags |= IORESOURCE_STORED;
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report_resource_stored(dev, res, "");
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@@ -657,14 +653,18 @@ printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n");
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if (d.mask & 1) {
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basek = ((resource_t) ((u64) d.base)) << 8;
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limitk = (resource_t) (((u64) d.mask << 8) | 0xFFFFFF);
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printk(BIOS_DEBUG, "adsr: (before) basek = %llx, limitk = %llx.\n",basek,limitk);
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printk(BIOS_DEBUG,
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"adsr: (before) basek = %llx, limitk = %llx.\n", basek,
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limitk);
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/* Convert these values to multiples of 1K for ease of math. */
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basek >>= 10;
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limitk >>= 10;
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sizek = limitk - basek + 1;
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printk(BIOS_DEBUG, "adsr: (after) basek = %llx, limitk = %llx, sizek = %llx.\n",basek,limitk,sizek);
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printk(BIOS_DEBUG,
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"adsr: (after) basek = %llx, limitk = %llx, sizek = %llx.\n",
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basek, limitk, sizek);
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/* see if we need a hole from 0xa0000 to 0xbffff */
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if ((basek < 640) && (sizek > 768)) {
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@@ -675,8 +675,9 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n");
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sizek = limitk - 768;
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}
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printk(BIOS_DEBUG, "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", mmio_basek, basek, limitk);
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printk(BIOS_DEBUG,
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"adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
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mmio_basek, basek, limitk);
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/* split the region to accomodate pci memory space */
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if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) {
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@@ -684,20 +685,24 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", mmi
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unsigned pre_sizek;
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pre_sizek = mmio_basek - basek;
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if (pre_sizek > 0) {
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ram_resource(dev, idx, basek, pre_sizek);
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ram_resource(dev, idx, basek,
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pre_sizek);
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idx += 0x10;
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sizek -= pre_sizek;
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#if CONFIG_WRITE_HIGH_TABLES==1
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if (high_tables_base == 0) {
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/* Leave some space for ACPI, PIRQ and MP tables */
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#if CONFIG_GFXUMA == 1
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high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
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high_tables_base =
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uma_memory_base -
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(HIGH_TABLES_SIZE * 1024);
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#else
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high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
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#endif
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high_tables_size = HIGH_TABLES_SIZE * 1024;
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printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE,
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high_tables_base);
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printk(BIOS_DEBUG,
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" split: %dK table at =%08llx\n",
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HIGH_TABLES_SIZE, high_tables_base);
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}
|
||||
#endif
|
||||
}
|
||||
@@ -706,8 +711,7 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", mmi
|
||||
}
|
||||
if ((basek + sizek) <= 4 * 1024 * 1024) {
|
||||
sizek = 0;
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
basek = 4 * 1024 * 1024;
|
||||
sizek -= (4 * 1024 * 1024 - mmio_basek);
|
||||
}
|
||||
@@ -716,8 +720,9 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", mmi
|
||||
ram_resource(dev, (idx | 0), basek, sizek);
|
||||
idx += 0x10;
|
||||
#if CONFIG_WRITE_HIGH_TABLES==1
|
||||
printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
|
||||
0, mmio_basek, basek, limitk);
|
||||
printk(BIOS_DEBUG,
|
||||
"%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0,
|
||||
mmio_basek, basek, limitk);
|
||||
if (high_tables_base == 0) {
|
||||
/* Leave some space for ACPI, PIRQ and MP tables */
|
||||
#if CONFIG_GFXUMA == 1
|
||||
@@ -731,7 +736,8 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", mmi
|
||||
#endif
|
||||
}
|
||||
printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek);
|
||||
printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n",high_tables_size);
|
||||
printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n",
|
||||
high_tables_size);
|
||||
|
||||
#if CONFIG_GFXUMA == 1
|
||||
printk(BIOS_DEBUG, "adsr - adding uma resource.\n");
|
||||
@@ -746,9 +752,7 @@ printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n",high_tables_size);
|
||||
printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n");
|
||||
}
|
||||
|
||||
|
||||
static void domain_enable_resources(device_t dev)
|
||||
{
|
||||
static void domain_enable_resources(device_t dev) {
|
||||
u32 val;
|
||||
|
||||
#if CONFIG_AMD_SB_CIMX
|
||||
@@ -766,12 +770,9 @@ static void domain_enable_resources(device_t dev)
|
||||
printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n");
|
||||
}
|
||||
|
||||
|
||||
/* Bus related code */
|
||||
|
||||
|
||||
static void cpu_bus_read_resources(device_t dev)
|
||||
{
|
||||
static void cpu_bus_read_resources(device_t dev) {
|
||||
printk(BIOS_DEBUG, "\nFam14h - cpu_bus_read_resources.\n");
|
||||
|
||||
#if CONFIG_MMCONF_SUPPORT
|
||||
@@ -783,8 +784,7 @@ static void cpu_bus_read_resources(device_t dev)
|
||||
#endif
|
||||
}
|
||||
|
||||
static void cpu_bus_set_resources(device_t dev)
|
||||
{
|
||||
static void cpu_bus_set_resources(device_t dev) {
|
||||
struct resource *resource = find_resource(dev, 0xc0010058);
|
||||
|
||||
printk(BIOS_DEBUG, "\nFam14h - cpu_bus_set_resources.\n");
|
||||
@@ -795,8 +795,7 @@ static void cpu_bus_set_resources(device_t dev)
|
||||
pci_dev_set_resources(dev);
|
||||
}
|
||||
|
||||
static void cpu_bus_init(device_t dev)
|
||||
{
|
||||
static void cpu_bus_init(device_t dev) {
|
||||
struct device_path cpu_path;
|
||||
device_t cpu;
|
||||
int apic_id;
|
||||
@@ -808,14 +807,14 @@ static void cpu_bus_init(device_t dev)
|
||||
cpu_path.type = DEVICE_PATH_APIC;
|
||||
cpu_path.apic.apic_id = apic_id;
|
||||
cpu = alloc_dev(dev->link_list, &cpu_path);
|
||||
if (!cpu) return;
|
||||
if (!cpu)
|
||||
return;
|
||||
cpu->enabled = 1;
|
||||
cpu->path.apic.node_id = 0;
|
||||
cpu->path.apic.core_id = apic_id;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* North Bridge Structures */
|
||||
|
||||
static struct device_operations northbridge_operations = {
|
||||
@@ -823,27 +822,22 @@ static struct device_operations northbridge_operations = {
|
||||
.set_resources = set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = northbridge_init,
|
||||
.enable = 0,
|
||||
.ops_pci = 0,
|
||||
.enable = 0,.ops_pci = 0,
|
||||
};
|
||||
|
||||
|
||||
static const struct pci_driver northbridge_driver __pci_driver = {
|
||||
.ops = &northbridge_operations,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = 0x1510,
|
||||
};
|
||||
|
||||
|
||||
struct chip_operations northbridge_amd_agesa_family14_ops = {
|
||||
CHIP_NAME("AMD Family 14h Northbridge")
|
||||
.enable_dev = 0,
|
||||
};
|
||||
|
||||
|
||||
/* Root Complex Structures */
|
||||
|
||||
|
||||
static struct device_operations pci_domain_ops = {
|
||||
.read_resources = domain_read_resources,
|
||||
.set_resources = domain_set_resources,
|
||||
@@ -852,7 +846,6 @@ static struct device_operations pci_domain_ops = {
|
||||
.scan_bus = pci_domain_scan_bus,
|
||||
};
|
||||
|
||||
|
||||
static struct device_operations cpu_bus_ops = {
|
||||
.read_resources = cpu_bus_read_resources,
|
||||
.set_resources = cpu_bus_set_resources,
|
||||
@@ -861,19 +854,15 @@ static struct device_operations cpu_bus_ops = {
|
||||
.scan_bus = NULL,
|
||||
};
|
||||
|
||||
|
||||
static void root_complex_enable_dev(struct device *dev)
|
||||
{
|
||||
static void root_complex_enable_dev(struct device *dev) {
|
||||
/* Set the operations if it is a special bus type */
|
||||
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
|
||||
dev->ops = &pci_domain_ops;
|
||||
}
|
||||
else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
|
||||
} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
|
||||
dev->ops = &cpu_bus_ops;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
struct chip_operations northbridge_amd_agesa_family14_root_complex_ops = {
|
||||
CHIP_NAME("AMD Family 14h Root Complex")
|
||||
.enable_dev = root_complex_enable_dev,
|
||||
|
||||
Reference in New Issue
Block a user