soc/intel/braswell: Set GNVS DPTE via devicetree

Introduce the `dptf_enable` devicetree setting to set the DPTE GNVS
field, as newer Intel platforms do.

Change-Id: I88b746c64ca57604f946eefb00a70487a2fb27c0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>

src/mainboard/facebook/fbg1701/acpi_tables.c

@@ -15,9 +15,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs)
 	gnvs->s5u0 = 0;
 	gnvs->s5u1 = 0;
 
-	/* Disable DPTF */
-	gnvs->dpte = 0;
-
 	/* PMIC is configured in I2C1, hide it for the OS */
 	struct device_nvs *dev_nvs = acpi_get_device_nvs();
 	dev_nvs->lpss_en[LPSS_NVS_I2C2] = 0;

src/mainboard/google/cyan/acpi_tables.c

@@ -15,9 +15,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs)
 	gnvs->s5u0 = 0;
 	gnvs->s5u1 = 0;
 
-	/* Enable DPTF */
-	gnvs->dpte = 1;
-
 	/* Disable PMIC I2C port for ACPI for all boards except cyan */
 	struct device_nvs *dev_nvs = acpi_get_device_nvs();
 	if (!CONFIG(BOARD_GOOGLE_CYAN))

src/mainboard/google/cyan/devicetree.cb

@@ -77,6 +77,8 @@ chip soc/intel/braswell
 	# LPE audio codec settings
 	register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
 
+	register "dptf_enable" = "true"
+
 	# Enable LPSS and LPE devices in ACPI mode
 	register "lpss_acpi_mode" = "1"
 	register "emmc_acpi_mode" = "0"

src/mainboard/intel/strago/acpi_tables.c

@@ -15,9 +15,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs)
 	gnvs->s5u0 = 0;
 	gnvs->s5u1 = 0;
 
-	/* Enable DPTF */
-	gnvs->dpte = 1;
-
 	/* PMIC is configured in I2C1, hidden it from OS */
 	struct device_nvs *dev_nvs = acpi_get_device_nvs();
 	dev_nvs->lpss_en[LPSS_NVS_I2C2] = 0;

src/mainboard/intel/strago/devicetree.cb

@@ -66,6 +66,8 @@ chip soc/intel/braswell
 	# LPE audio codec settings
 	register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
 
+	register "dptf_enable" = "true"
+
 	# Enable devices in ACPI mode
 	register "lpss_acpi_mode" = "1"
 	register "emmc_acpi_mode" = "1"

src/mainboard/portwell/m107/acpi_tables.c

@@ -15,9 +15,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs)
 	gnvs->s5u0 = 0;
 	gnvs->s5u1 = 0;
 
-	/* Disable DPTF */
-	gnvs->dpte = 0;
-
 	/* PMIC is configured in I2C1, hide it for the OS */
 	struct device_nvs *dev_nvs = acpi_get_device_nvs();
 	dev_nvs->lpss_en[LPSS_NVS_I2C2] = 0;

src/soc/intel/braswell/acpi.c

@@ -26,6 +26,8 @@
 #include <types.h>
 #include <wrdd.h>
 
+#include "chip.h"
+
 #define MWAIT_RES(state, sub_state)                         \
 	{                                                   \
 		.addrl = (((state) << 4) | (sub_state)),    \
@@ -68,6 +70,10 @@ size_t size_of_dnvs(void)
 
 void soc_fill_gnvs(struct global_nvs *gnvs)
 {
+	const struct soc_intel_braswell_config *config = config_of_soc();
+
+	gnvs->dpte = config->dptf_enable;
+
 	/* Fill in the Wi-Fi Region ID */
 	if (CONFIG(HAVE_REGULATORY_DOMAIN))
 		gnvs->cid1 = wifi_regulatory_domain();

src/soc/intel/braswell/chip.h

@@ -42,6 +42,8 @@ enum usb_comp_bg_value {
 struct soc_intel_braswell_config {
 	bool enable_xdp_tap;
 
+	bool dptf_enable;
+
 	enum serirq_mode serirq_mode;
 
 	/* Disable SLP_X stretching after SUS power well loss */