diff --git a/src/mainboard/system76/cfl-h/devicetree.cb b/src/mainboard/system76/cfl-h/devicetree.cb
index b947b8205a..2f7dd690e6 100644
--- a/src/mainboard/system76/cfl-h/devicetree.cb
+++ b/src/mainboard/system76/cfl-h/devicetree.cb
@@ -130,9 +130,9 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcClkReq[8]" = "8"
 
 	# Misc
-	register "Device4Enable" = "1"
+	register "Device4Enable" = "0"
 	register "HeciEnabled" = "1"
-	register "AcousticNoiseMitigation" = "1"
+	#register "AcousticNoiseMitigation" = "1"
 	#register "dmipwroptimize" = "1"
 	#register "satapwroptimize" = "1"
 
diff --git a/src/mainboard/system76/cfl-h/ramstage.c b/src/mainboard/system76/cfl-h/ramstage.c
index e7e5bdbcd2..5261374d1b 100644
--- a/src/mainboard/system76/cfl-h/ramstage.c
+++ b/src/mainboard/system76/cfl-h/ramstage.c
@@ -14,11 +14,44 @@
  */
 
 #include <console/console.h>
+#include <delay.h>
 #include <device/device.h>
+#include <gpio.h>
 #include <pc80/keyboard.h>
 #include <soc/ramstage.h>
 #include <variant/gpio.h>
 
+#ifdef GPU_RESET
+
+#define DGPU_RSTN GPP_F22
+#define DGPU_PWR_EN GPP_F23
+#define DGPU_PWRGD GPP_K22
+
+static void gpu_reset(void) {
+	// Set DGPU_PWR_EN and Wait for DGPU_PWRGD
+	printk(BIOS_INFO, "system76: DGPU reset start\n");
+	gpio_set(DGPU_RSTN, 0);
+
+	printk(BIOS_INFO, "system76: DGPU disable power\n");
+	gpio_set(DGPU_PWR_EN, 0);
+	while (gpio_get(DGPU_PWRGD)) {
+		printk(BIOS_INFO, "system76: DGPU wait for disabled power\n");
+		mdelay(4);
+	}
+
+	printk(BIOS_INFO, "system76: DGPU enable power\n");
+	gpio_set(DGPU_PWR_EN, 1);
+	while (! gpio_get(DGPU_PWRGD)) {
+		printk(BIOS_INFO, "system76: DGPU wait for enabled power\n");
+		mdelay(4);
+	}
+
+	printk(BIOS_INFO, "system76: DGPU reset finished\n");
+	gpio_set(DGPU_RSTN, 1);
+}
+
+#endif
+
 void mainboard_silicon_init_params(FSP_S_CONFIG *params) {
 	/* Configure pads prior to SiliconInit() in case there's any
 	 * dependencies during hardware initialization. */
@@ -31,6 +64,10 @@ static void mainboard_init(struct device *dev) {
 }
 
 static void mainboard_enable(struct device *dev) {
+#ifdef GPU_RESET
+	gpu_reset();
+#endif
+
 	dev->ops->init = mainboard_init;
 }
 
diff --git a/src/mainboard/system76/cfl-h/variants/gaze14_1650_15/include/variant/gpio.h b/src/mainboard/system76/cfl-h/variants/gaze14_1650_15/include/variant/gpio.h
index 9b4ec81c1b..4f5926a937 100644
--- a/src/mainboard/system76/cfl-h/variants/gaze14_1650_15/include/variant/gpio.h
+++ b/src/mainboard/system76/cfl-h/variants/gaze14_1650_15/include/variant/gpio.h
@@ -72,13 +72,13 @@ static const struct pad_config gpio_table[] = {
 		// SB_KBCRST#
 		PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
 		// LPC_AD0
-		PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
 		// LPC_AD1
-		PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
 		// LPC_AD2
-		PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
 		// LPC_AD3
-		PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
 		// LPC_FRAME#
 		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
 		// SERIRQ