- Minor mod to reset16.inc to work with newer binutils hopefully this works with older ones...
- Update apic.h to include the APIC_TASK_PRI register definition - Update mptable.c to have a reasonable board OEM and productid - Additional testfiles for romcc. - Split out auto.c and early failover.c moving their generic bits elsewere - Enable cache of the rom - Fixes to amd8111_lpc.c so that we successfully setup virtual wire mode on the ioapic git-svn-id: svn://svn.coreboot.org/coreboot/trunk@880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
@@ -68,6 +68,11 @@ static void interrupts_on()
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low |= APIC_DEFAULT_BASE;
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wrmsr(APIC_BASE_MSR, low, high);
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/*
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* Set Task Priority to 'accept all'.
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*/
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apic_write_around(APIC_TASKPRI,
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apic_read_around(APIC_TASKPRI) & ~APIC_TPRI_MASK);
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/* Put the local apic in virtual wire mode */
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apic_write_around(APIC_SPIV,
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@@ -91,10 +96,9 @@ static void interrupts_on()
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| (APIC_LVT_REMOTE_IRR |APIC_SEND_PENDING |
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APIC_DELIVERY_MODE_NMI)
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);
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#if 1
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printk_debug(" apic_id: %d ",
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apic_read(APIC_ID));
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#endif
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#else /* APIC */
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#ifdef i686
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@@ -13,7 +13,7 @@ EXT(reset_vector):
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* other assemblers to tell it where the segment registers
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* are pointing in memory right now.
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*/
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jmp EXT(_start_offset)
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jmp EXT(_start)
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#elif (_ROMBASE < 0x100000)
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ljmp $((_ROMBASE & 0xf0000)>>4),$EXT(_start_offset);
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#else
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@@ -46,7 +46,7 @@ set_var_mtrr:
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wrmsr
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#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
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/* enable write back cachine so we can do execute in place
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/* enable write base caching so we can do execute in place
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* on the flash rom.
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*/
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movl $0x202, %ecx
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@@ -10,6 +10,8 @@
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#define APIC_ID 0x020
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#define APIC_LVR 0x030
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#define APIC_TASKPRI 0x80
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#define APIC_TPRI_MASK 0xFF
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#define APIC_ARBID 0x090
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#define APIC_RRR 0x0C0
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#define APIC_SVR 0x0f0
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@@ -20,7 +20,9 @@ static int boot_cpu(void)
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msr = rdmsr(0x1b);
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bsp = !!(msr.lo & (1 << 8));
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if (bsp) {
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print_debug("Bootstrap cpu\r\n");
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print_debug("Bootstrap processor\r\n");
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} else {
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print_debug("Application processor\r\n");
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}
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return bsp;
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@@ -110,14 +112,19 @@ static void dump_spd_registers(void)
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}
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}
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static void main(void)
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{
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uart_init();
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console_init();
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#if 0
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print_debug(" XIP_ROM_BASE: ");
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print_debug_hex32(XIP_ROM_BASE);
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print_debug(" XIP_ROM_SIZE: ");
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print_debug_hex32(XIP_ROM_SIZE);
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print_debug("\r\n");
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#endif
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if (boot_cpu() && !cpu_init_detected()) {
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setup_default_resource_map();
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setup_coherent_ht_domain();
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enumerate_ht_chain();
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print_pci_devices();
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@@ -125,17 +132,7 @@ static void main(void)
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sdram_initialize();
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dump_spd_registers();
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#if 0
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ram_fill( 0x00100000, 0x00180000);
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ram_verify(0x00100000, 0x00180000);
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#endif
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#ifdef MEMORY_1024MB
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ram_fill( 0x00000000, 0x00001000);
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ram_verify(0x00000000, 0x00001000);
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#endif
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#ifdef MEMROY_512MB
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ram_fill( 0x00000000, 0x01ffffff);
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ram_verify(0x00000000, 0x01ffffff);
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#endif
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/* Check the first 8M */
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ram_check(0x00100000, 0x00800000);
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}
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}
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@@ -7,8 +7,8 @@
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void *smp_write_config_table(void *v, unsigned long * processor_map)
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{
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static const char sig[4] = "PCMP";
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static const char oem[8] = "LNXI ";
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static const char productid[12] = "P4DPR ";
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static const char oem[8] = "AMD ";
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static const char productid[12] = "SOLO7 ";
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struct mp_config_table *mc;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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@@ -1,3 +1,11 @@
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#define COHERENT_AMD_SOLO 1 /* AMD Solo motherboard */
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#define COHERENT_ARIMA_HDAMA 2 /* Arima HDAMA motherboard */
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#ifndef COHERENT_CONFIG
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#define COHERENT_CONFIG COHERENT_AMD_SOLO
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#endif
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static void setup_coherent_ht_domain(void)
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{
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static const unsigned int register_values[] = {
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@@ -296,278 +304,6 @@ static void setup_coherent_ht_domain(void)
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* F0:0xB8 i = 1,
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* F0:0xD8 i = 2,
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*/
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/* Careful set limit registers before base registers which contain the enables */
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/* DRAM Limit i Registers
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* F1:0x44 i = 0
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* F1:0x4C i = 1
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* F1:0x54 i = 2
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* F1:0x5C i = 3
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* F1:0x64 i = 4
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* F1:0x6C i = 5
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* F1:0x74 i = 6
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* F1:0x7C i = 7
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* [ 2: 0] Destination Node ID
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* 000 = Node 0
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* 001 = Node 1
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* 010 = Node 2
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* 011 = Node 3
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* 100 = Node 4
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* 101 = Node 5
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* 110 = Node 6
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* 111 = Node 7
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* [ 7: 3] Reserved
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* [10: 8] Interleave select
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* specifies the values of A[14:12] to use with interleave enable.
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* [15:11] Reserved
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* [31:16] DRAM Limit Address i Bits 39-24
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* This field defines the upper address bits of a 40 bit address
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* that define the end of the DRAM region.
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*/
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#if MEMORY_1024MB
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PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x003f0000,
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#endif
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#if MEMORY_512MB
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PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x001f0000,
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#endif
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PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
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PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
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PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
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PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
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PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
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PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
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PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
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/* DRAM Base i Registers
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* F1:0x40 i = 0
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* F1:0x48 i = 1
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* F1:0x50 i = 2
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* F1:0x58 i = 3
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* F1:0x60 i = 4
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* F1:0x68 i = 5
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* F1:0x70 i = 6
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* F1:0x78 i = 7
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* [ 0: 0] Read Enable
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* 0 = Reads Disabled
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* 1 = Reads Enabled
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* [ 1: 1] Write Enable
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* 0 = Writes Disabled
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* 1 = Writes Enabled
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* [ 7: 2] Reserved
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* [10: 8] Interleave Enable
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* 000 = No interleave
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* 001 = Interleave on A[12] (2 nodes)
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* 010 = reserved
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* 011 = Interleave on A[12] and A[14] (4 nodes)
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* 100 = reserved
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* 101 = reserved
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* 110 = reserved
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* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
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* [15:11] Reserved
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* [13:16] DRAM Base Address i Bits 39-24
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* This field defines the upper address bits of a 40-bit address
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* that define the start of the DRAM region.
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*/
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PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000003,
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#if MEMORY_1024MB
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PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00400000,
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PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00400000,
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PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00400000,
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PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00400000,
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PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00400000,
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PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00400000,
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PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00400000,
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#endif
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#if MEMORY_512MB
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PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00200000,
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PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00200000,
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PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00200000,
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PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00200000,
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PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00200000,
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PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00200000,
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PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00200000,
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#endif
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/* Memory-Mapped I/O Limit i Registers
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* F1:0x84 i = 0
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* F1:0x8C i = 1
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* F1:0x94 i = 2
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* F1:0x9C i = 3
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* F1:0xA4 i = 4
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* F1:0xAC i = 5
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* F1:0xB4 i = 6
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* F1:0xBC i = 7
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* [ 2: 0] Destination Node ID
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* 000 = Node 0
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* 001 = Node 1
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* 010 = Node 2
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* 011 = Node 3
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* 100 = Node 4
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* 101 = Node 5
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* 110 = Node 6
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* 111 = Node 7
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* [ 3: 3] Reserved
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* [ 5: 4] Destination Link ID
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* 00 = Link 0
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* 01 = Link 1
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* 10 = Link 2
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* 11 = Reserved
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* [ 6: 6] Reserved
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* [ 7: 7] Non-Posted
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* 0 = CPU writes may be posted
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* 1 = CPU writes must be non-posted
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* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
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* This field defines the upp adddress bits of a 40-bit address that
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* defines the end of a memory-mapped I/O region n
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*/
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PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00e1ff00,
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PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00dfff00,
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PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00e3ff00,
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PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000b00,
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PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00fe0b00,
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/* Memory-Mapped I/O Base i Registers
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* F1:0x80 i = 0
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* F1:0x88 i = 1
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* F1:0x90 i = 2
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* F1:0x98 i = 3
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* F1:0xA0 i = 4
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* F1:0xA8 i = 5
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* F1:0xB0 i = 6
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* F1:0xB8 i = 7
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* [ 0: 0] Read Enable
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* 0 = Reads disabled
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* 1 = Reads Enabled
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* [ 1: 1] Write Enable
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* 0 = Writes disabled
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* 1 = Writes Enabled
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* [ 2: 2] Cpu Disable
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* 0 = Cpu can use this I/O range
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* 1 = Cpu requests do not use this I/O range
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* [ 3: 3] Lock
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* 0 = base/limit registers i are read/write
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* 1 = base/limit registers i are read-only
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* [ 7: 4] Reserved
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* [31: 8] Memory-Mapped I/O Base Address i (39-16)
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* This field defines the upper address bits of a 40bit address
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* that defines the start of memory-mapped I/O region i
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*/
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PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00e00003,
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PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00d80003,
|
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PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00e20003,
|
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PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
|
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PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
|
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PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
|
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PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000a03,
|
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#if MEMORY_1024MB
|
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PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00400003,
|
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#endif
|
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#if MEMORY_512MB
|
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PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00200003,
|
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#endif
|
||||
|
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/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = reserved
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x0000d000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x000ff000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
|
||||
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x0000d003,
|
||||
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00001013,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Reserved
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration regin i
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003,
|
||||
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
|
||||
|
||||
};
|
||||
int i;
|
||||
int max;
|
||||
@@ -598,4 +334,3 @@ static void setup_coherent_ht_domain(void)
|
||||
}
|
||||
print_debug("done.\r\n");
|
||||
}
|
||||
|
||||
|
||||
@@ -1,7 +1,43 @@
|
||||
#define MEMORY_512MB 0 /* SuSE Solo configuration */
|
||||
#define MEMORY_1024MB 1 /* LNXI Solo configuration */
|
||||
#define MEMORY_SUSE_SOLO 1 /* SuSE Solo configuration */
|
||||
#define MEMORY_LNXI_SOLO 2 /* LNXI Solo configuration */
|
||||
#define MEMORY_LNXI_HDAMA 3 /* LNXI HDAMA configuration */
|
||||
|
||||
static void sdram_set_registers(void)
|
||||
|
||||
#ifndef MEMORY_CONFIG
|
||||
#define MEMORY_CONFIG MEMORY_SUSE_SOLO
|
||||
#endif
|
||||
|
||||
static void setup_resource_map(const unsigned int *register_values, int max)
|
||||
{
|
||||
int i;
|
||||
print_debug("setting up resource map....\r\n");
|
||||
for(i = 0; i < max; i += 3) {
|
||||
device_t dev;
|
||||
unsigned where;
|
||||
unsigned long reg;
|
||||
#if 0
|
||||
print_debug_hex32(register_values[i]);
|
||||
print_debug(" <-");
|
||||
print_debug_hex32(register_values[i+2]);
|
||||
print_debug("\r\n");
|
||||
#endif
|
||||
dev = register_values[i] & ~0xff;
|
||||
where = register_values[i] & 0xff;
|
||||
reg = pci_read_config32(dev, where);
|
||||
reg &= register_values[i+1];
|
||||
reg |= register_values[i+2];
|
||||
pci_write_config32(dev, where, reg);
|
||||
#if 0
|
||||
reg = pci_read_config32(register_values[i]);
|
||||
reg &= register_values[i+1];
|
||||
reg |= register_values[i+2] & ~register_values[i+1];
|
||||
pci_write_config32(register_values[i], reg);
|
||||
#endif
|
||||
}
|
||||
print_debug("done.\r\n");
|
||||
}
|
||||
|
||||
static void setup_default_resource_map(void)
|
||||
{
|
||||
static const unsigned int register_values[] = {
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
@@ -31,12 +67,7 @@ static void sdram_set_registers(void)
|
||||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
#if MEMORY_1024MB
|
||||
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x003f0000,
|
||||
#endif
|
||||
#if MEMORY_512MB
|
||||
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x001f0000,
|
||||
#endif
|
||||
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
|
||||
PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
|
||||
PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
|
||||
@@ -74,25 +105,14 @@ static void sdram_set_registers(void)
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000003,
|
||||
#if MEMORY_1024MB
|
||||
PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00400000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00400000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00400000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00400000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00400000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00400000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00400000,
|
||||
#endif
|
||||
#if MEMORY_512MB
|
||||
PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00200000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00200000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00200000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00200000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00200000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00200000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00200000,
|
||||
#endif
|
||||
PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
@@ -126,14 +146,14 @@ static void sdram_set_registers(void)
|
||||
* This field defines the upp adddress bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00e1ff00,
|
||||
PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00dfff00,
|
||||
PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00e3ff00,
|
||||
PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000b00,
|
||||
PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00fe0b00,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
@@ -161,19 +181,14 @@ static void sdram_set_registers(void)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00e00003,
|
||||
PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00d80003,
|
||||
PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00e20003,
|
||||
PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000a03,
|
||||
#if MEMORY_1024MB
|
||||
PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00400003,
|
||||
#endif
|
||||
#if MEMORY_512MB
|
||||
PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00200003,
|
||||
#endif
|
||||
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00000000,
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
@@ -200,8 +215,8 @@ static void sdram_set_registers(void)
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x0000d000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x000ff000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
|
||||
|
||||
@@ -230,8 +245,8 @@ static void sdram_set_registers(void)
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x0000d003,
|
||||
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00001013,
|
||||
PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
|
||||
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
|
||||
|
||||
@@ -275,6 +290,350 @@ static void sdram_set_registers(void)
|
||||
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
|
||||
};
|
||||
int max;
|
||||
max = sizeof(register_values)/sizeof(register_values[0]);
|
||||
setup_resource_map(register_values, max);
|
||||
}
|
||||
|
||||
static void sdram_set_registers(void)
|
||||
{
|
||||
static const unsigned int register_values[] = {
|
||||
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
* F1:0x4C i = 1
|
||||
* F1:0x54 i = 2
|
||||
* F1:0x5C i = 3
|
||||
* F1:0x64 i = 4
|
||||
* F1:0x6C i = 5
|
||||
* F1:0x74 i = 6
|
||||
* F1:0x7C i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 3] Reserved
|
||||
* [10: 8] Interleave select
|
||||
* specifies the values of A[14:12] to use with interleave enable.
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Limit Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
#if MEMORY_CONFIG == MEMORY_LNXI_SOLO
|
||||
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x003f0000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
|
||||
#endif
|
||||
#if MEMORY_CONFIG == MEMORY_SUSE_SOLO
|
||||
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x001f0000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
|
||||
#endif
|
||||
#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
|
||||
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x003f0000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x007f0001,
|
||||
#endif
|
||||
PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
|
||||
PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
|
||||
PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
|
||||
PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
|
||||
PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
|
||||
PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [13:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000003,
|
||||
#if MEMORY_CONFIG == MEMORY_LNXI_SOLO
|
||||
PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00400000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00400000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00400000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00400000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00400000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00400000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00400000,
|
||||
#endif
|
||||
#if MEMORY_CONFIG == MEMORY_SUSE_SOLO
|
||||
PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00200000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00200000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00200000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00200000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00200000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00200000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00200000,
|
||||
#endif
|
||||
#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
|
||||
PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00400003,
|
||||
PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00800000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00800000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00800000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00800000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00800000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00800000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00800000,
|
||||
#endif
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Reserved
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp adddress bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
#if (MEMORY_CONFIG == MEMORY_LNXI_SOLO) || (MEMORY_CONFIG == MEMORY_SUSE_SOLO)
|
||||
PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00e1ff00,
|
||||
PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00dfff00,
|
||||
PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00e3ff00,
|
||||
PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000b00,
|
||||
PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00fe0b00,
|
||||
#endif
|
||||
#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
|
||||
PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00fe2f00,
|
||||
PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00fec000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x0000b000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00000000,
|
||||
#endif
|
||||
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
#if (MEMORY_CONFIG == MEMORY_LNXI_SOLO) || (MEMORY_CONFIG == MEMORY_SUSE_SOLO)
|
||||
PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00e00003,
|
||||
PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00d80003,
|
||||
PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00e20003,
|
||||
PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000a03,
|
||||
#endif
|
||||
#if MEMORY_CONFIG == MEMORY_LNXI_SOLO
|
||||
PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00400003,
|
||||
#endif
|
||||
#if MEMORY_CONFIG == MEMORY_SUSE_SOLO
|
||||
PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00200003,
|
||||
#endif
|
||||
#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
|
||||
PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00fc0003,
|
||||
PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00fec00e,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000a03,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00000000,
|
||||
#endif
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = reserved
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
#if (MEMORY_CONFIG == MEMORY_LNXI_SOLO) || (MEMORY_CONFIG == MEMORY_SUSE_SOLO)
|
||||
PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x0000d000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x000ff000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
|
||||
#endif
|
||||
#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
|
||||
PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
|
||||
#endif
|
||||
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
#if (MEMORY_CONFIG == MEMORY_LNXI_SOLO) || (MEMORY_CONFIG == MEMORY_SUSE_SOLO)
|
||||
PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x0000d003,
|
||||
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00001013,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
|
||||
#endif
|
||||
#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
|
||||
PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
|
||||
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
|
||||
#endif
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Reserved
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration regin i
|
||||
*/
|
||||
#if (MEMORY_CONFIG == MEMORY_LNXI_SOLO) || (MEMORY_CONFIG == MEMORY_SUSE_SOLO)
|
||||
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003,
|
||||
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
|
||||
#endif
|
||||
#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
|
||||
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003,
|
||||
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
|
||||
#endif
|
||||
|
||||
/* DRAM CS Base Address i Registers
|
||||
* F2:0x40 i = 0
|
||||
@@ -298,15 +657,20 @@ static void sdram_set_registers(void)
|
||||
* bits decode 32-MByte blocks of memory.
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 2, 0x40), 0x001f01fe, 0x00000001,
|
||||
#if MEMORY_1024MB
|
||||
#if MEMORY_CONFIG == MEMORY_LNXI_SOLO
|
||||
PCI_ADDR(0, 0x18, 2, 0x44), 0x001f01fe, 0x01000001,
|
||||
PCI_ADDR(0, 0x18, 2, 0x48), 0x001f01fe, 0x02000001,
|
||||
PCI_ADDR(0, 0x18, 2, 0x4C), 0x001f01fe, 0x03000001,
|
||||
#endif
|
||||
#if MEMORY_512MB
|
||||
#if MEMORY_CONFIG == MEMORY_SUSE_SOLO
|
||||
PCI_ADDR(0, 0x18, 2, 0x44), 0x001f01fe, 0x00800001,
|
||||
PCI_ADDR(0, 0x18, 2, 0x48), 0x001f01fe, 0x01000001,
|
||||
PCI_ADDR(0, 0x18, 2, 0x4C), 0x001f01fe, 0x01800001,
|
||||
#endif
|
||||
#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
|
||||
PCI_ADDR(0, 0x18, 2, 0x44), 0x001f01fe, 0x00001001,
|
||||
PCI_ADDR(0, 0x18, 2, 0x48), 0x001f01fe, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 2, 0x4C), 0x001f01fe, 0x00000000,
|
||||
#endif
|
||||
PCI_ADDR(0, 0x18, 2, 0x50), 0x001f01fe, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 2, 0x54), 0x001f01fe, 0x00000000,
|
||||
@@ -331,17 +695,23 @@ static void sdram_set_registers(void)
|
||||
* [31:30] Reserved
|
||||
*
|
||||
*/
|
||||
#if MEMORY_1024MB
|
||||
#if MEMORY_CONFIG == MEMORY_LNXI_SOLO
|
||||
PCI_ADDR(0, 0x18, 2, 0x60), 0xC01f01ff, 0x00e0fe00,
|
||||
PCI_ADDR(0, 0x18, 2, 0x64), 0xC01f01ff, 0x00e0fe00,
|
||||
PCI_ADDR(0, 0x18, 2, 0x68), 0xC01f01ff, 0x00e0fe00,
|
||||
PCI_ADDR(0, 0x18, 2, 0x6C), 0xC01f01ff, 0x00e0fe00,
|
||||
#endif
|
||||
#if MEMORY_512MB
|
||||
#if MEMORY_CONFIG == MEMORY_SUSE_SOLO
|
||||
PCI_ADDR(0, 0x18, 2, 0x60), 0xC01f01ff, 0x0060fe00,
|
||||
PCI_ADDR(0, 0x18, 2, 0x64), 0xC01f01ff, 0x0060fe00,
|
||||
PCI_ADDR(0, 0x18, 2, 0x68), 0xC01f01ff, 0x0060fe00,
|
||||
PCI_ADDR(0, 0x18, 2, 0x6C), 0xC01f01ff, 0x0060fe00,
|
||||
#endif
|
||||
#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
|
||||
PCI_ADDR(0, 0x18, 2, 0x60), 0xC01f01ff, 0x03e0ee00,
|
||||
PCI_ADDR(0, 0x18, 2, 0x64), 0xC01f01ff, 0x03e0ee00,
|
||||
PCI_ADDR(0, 0x18, 2, 0x68), 0xC01f01ff, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 2, 0x6C), 0xC01f01ff, 0x00000000,
|
||||
#endif
|
||||
PCI_ADDR(0, 0x18, 2, 0x70), 0xC01f01ff, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 2, 0x74), 0xC01f01ff, 0x00000000,
|
||||
@@ -367,11 +737,14 @@ static void sdram_set_registers(void)
|
||||
* [11:11] Reserved
|
||||
* [31:15]
|
||||
*/
|
||||
#if MEMORY_1024MB
|
||||
#if MEMORY_CONFIG == MEMORY_LNXI_SOLO
|
||||
PCI_ADDR(0, 0x18, 2, 0x80), 0xffff8888, 0x00000033,
|
||||
#endif
|
||||
#if MEMORY_512MB
|
||||
#if MEMORY_CONFIG == MEMORY_SUSE_SOLO
|
||||
PCI_ADDR(0, 0x18, 2, 0x80), 0xffff8888, 0x00000022,
|
||||
#endif
|
||||
#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
|
||||
PCI_ADDR(0, 0x18, 2, 0x80), 0xffff8888, 0x00000003,
|
||||
#endif
|
||||
/* DRAM Timing Low Register
|
||||
* F2:0x88
|
||||
@@ -437,7 +810,12 @@ static void sdram_set_registers(void)
|
||||
* 1 = 3 bus clocks
|
||||
* [31:29] Reserved
|
||||
*/
|
||||
#if (MEMORY_CONFIG == MEMORY_LNXI_SOLO) || (MEMORY_CONFIG == MEMORY_SUSE_SOLO)
|
||||
PCI_ADDR(0, 0x18, 2, 0x88), 0xe8088008, 0x03623125,
|
||||
#endif
|
||||
#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
|
||||
PCI_ADDR(0, 0x18, 2, 0x88), 0xe8088008, 0x13723335,
|
||||
#endif
|
||||
/* DRAM Timing High Register
|
||||
* F2:0x8C
|
||||
* [ 0: 0] Twtr (Write to Read Delay)
|
||||
@@ -467,13 +845,15 @@ static void sdram_set_registers(void)
|
||||
* 001 = 2 Mem clocks after CAS# (Registered Dimms)
|
||||
* [31:23] Reserved
|
||||
*/
|
||||
#if MEMORY_1024MB
|
||||
#if MEMORY_CONFIG == MEMORY_LNXI_SOLO
|
||||
PCI_ADDR(0, 0x18, 2, 0x8c), 0xff8fe08e, 0x00000930,
|
||||
#endif
|
||||
#if MEMORY_512MB
|
||||
#if MEMORY_CONFIG == MEMORY_SUSE_SOLO
|
||||
PCI_ADDR(0, 0x18, 2, 0x8c), 0xff8fe08e, 0x00000130,
|
||||
#endif
|
||||
|
||||
#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
|
||||
PCI_ADDR(0, 0x18, 2, 0x8c), 0xff8fe08e, 0x00100a20,
|
||||
#endif
|
||||
/* DRAM Config Low Register
|
||||
* F2:0x90
|
||||
* [ 0: 0] DLL Disable
|
||||
@@ -544,6 +924,7 @@ static void sdram_set_registers(void)
|
||||
* 111 = Oldest entry in DCQ can be bypassed 7 times
|
||||
* [31:28] Reserved
|
||||
*/
|
||||
#if (MEMORY_CONFIG == MEMORY_LNXI_SOLO) || (MEMORY_CONFIG == MEMORY_SUSE_SOLO)
|
||||
PCI_ADDR(0, 0x18, 2, 0x90), 0xf0000000,
|
||||
(4 << 25)|(0 << 24)|
|
||||
(0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)|
|
||||
@@ -551,6 +932,16 @@ static void sdram_set_registers(void)
|
||||
(2 << 14)|(0 << 13)|(0 << 12)|
|
||||
(0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)|
|
||||
(0 << 3) |(0 << 1) |(0 << 0),
|
||||
#endif
|
||||
#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
|
||||
PCI_ADDR(0, 0x18, 2, 0x90), 0xf0000000,
|
||||
(4 << 25)|(0 << 24)|
|
||||
(0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)|
|
||||
(0 << 19)|(0 << 18)|(0 << 17)|(1 << 16)|
|
||||
(2 << 14)|(0 << 13)|(0 << 12)|
|
||||
(0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)|
|
||||
(0 << 3) |(0 << 1) |(0 << 0),
|
||||
#endif
|
||||
/* DRAM Config High Register
|
||||
* F2:0x94
|
||||
* [ 0: 3] Maximum Asynchronous Latency
|
||||
@@ -615,11 +1006,14 @@ static void sdram_set_registers(void)
|
||||
* 1 = Enabled
|
||||
* [31:30] Reserved
|
||||
*/
|
||||
#if MEMORY_1024MB
|
||||
#if MEMORY_CONFIG == MEMORY_LNXI_SOLO
|
||||
PCI_ADDR(0, 0x18, 2, 0x94), 0xc180f0f0, 0x0e2b0a05,
|
||||
#endif
|
||||
#if MEMORY_512MB
|
||||
#if MEMORY_CONFIG == MEMORY_SUSE_SOLO
|
||||
PCI_ADDR(0, 0x18, 2, 0x94), 0xc180f0f0, 0x0e2b0a06,
|
||||
#endif
|
||||
#if MEMORY_CONFIG == MEMORY_LNXI_HDAMA
|
||||
PCI_ADDR(0, 0x18, 2, 0x94), 0xc180f0f0, 0x065b0b08,
|
||||
#endif
|
||||
/* DRAM Delay Line Register
|
||||
* F2:0x98
|
||||
|
||||
@@ -1,6 +1,13 @@
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <part/fallback_boot.h>
|
||||
|
||||
#ifndef MAX_REBOOT_CNT
|
||||
#error "MAX_REBOOT_CNT not defined"
|
||||
#endif
|
||||
#if MAX_REBOOT_CNT > 15
|
||||
#error "MAX_REBOOT_CNT too high"
|
||||
#endif
|
||||
|
||||
static unsigned char cmos_read(unsigned char addr)
|
||||
{
|
||||
outb(addr, RTC_BASE_PORT + 0);
|
||||
|
||||
@@ -1,8 +1,24 @@
|
||||
#if defined(i786)
|
||||
#define HAVE_MOVNTI 1
|
||||
#endif
|
||||
#if defined(k8)
|
||||
#define HAVE_MOVNTI 1
|
||||
#endif
|
||||
|
||||
static void write_phys(unsigned long addr, unsigned long value)
|
||||
{
|
||||
#if HAVE_MOVNTI
|
||||
asm volatile(
|
||||
"movnti %1, (%0)"
|
||||
: /* outputs */
|
||||
: "r" (addr), "r" (value) /* inputs */
|
||||
: /* clobbers */
|
||||
);
|
||||
#else
|
||||
volatile unsigned long *ptr;
|
||||
ptr = (void *)addr;
|
||||
*ptr = value;
|
||||
#endif
|
||||
}
|
||||
|
||||
static unsigned long read_phys(unsigned long addr)
|
||||
@@ -12,7 +28,7 @@ static unsigned long read_phys(unsigned long addr)
|
||||
return *ptr;
|
||||
}
|
||||
|
||||
void ram_fill(unsigned long start, unsigned long stop)
|
||||
static void ram_fill(unsigned long start, unsigned long stop)
|
||||
{
|
||||
unsigned long addr;
|
||||
/*
|
||||
@@ -25,7 +41,7 @@ void ram_fill(unsigned long start, unsigned long stop)
|
||||
print_debug("\r\n");
|
||||
for(addr = start; addr < stop ; addr += 4) {
|
||||
/* Display address being filled */
|
||||
if ((addr & 0xffff) == 0) {
|
||||
if (!(addr & 0xffff)) {
|
||||
print_debug_hex32(addr);
|
||||
print_debug("\r");
|
||||
}
|
||||
@@ -36,7 +52,7 @@ void ram_fill(unsigned long start, unsigned long stop)
|
||||
print_debug("\r\nDRAM filled\r\n");
|
||||
}
|
||||
|
||||
void ram_verify(unsigned long start, unsigned long stop)
|
||||
static void ram_verify(unsigned long start, unsigned long stop)
|
||||
{
|
||||
unsigned long addr;
|
||||
/*
|
||||
@@ -50,7 +66,7 @@ void ram_verify(unsigned long start, unsigned long stop)
|
||||
for(addr = start; addr < stop ; addr += 4) {
|
||||
unsigned long value;
|
||||
/* Display address being tested */
|
||||
if ((addr & 0xffff) == 0) {
|
||||
if (!(addr & 0xffff)) {
|
||||
print_debug_hex32(addr);
|
||||
print_debug("\r");
|
||||
}
|
||||
@@ -69,7 +85,7 @@ void ram_verify(unsigned long start, unsigned long stop)
|
||||
}
|
||||
|
||||
|
||||
void ramcheck(unsigned long start, unsigned long stop)
|
||||
void ram_check(unsigned long start, unsigned long stop)
|
||||
{
|
||||
int result;
|
||||
/*
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* (C) 2003 Linux Networx
|
||||
* (C) 2003 Linux Networx, SuSE Linux AG
|
||||
*/
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
@@ -28,38 +28,33 @@ static struct ioapicreg ioapicregvalues[] = {
|
||||
#define NMI (4 << 8)
|
||||
#define SMI (2 << 8)
|
||||
#define INT (1 << 8)
|
||||
/* IO-APIC virtual wire mode configuration */
|
||||
/* mask, trigger, polarity, destination, delivery, vector */
|
||||
{0x00, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT | 0, 0},
|
||||
{0x01, DISABLED, NONE},
|
||||
{0x02, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | INT | 0, 0},
|
||||
{0x03, DISABLED, NONE},
|
||||
{0x04, DISABLED, NONE},
|
||||
{0x05, DISABLED, NONE},
|
||||
{0x06, DISABLED, NONE},
|
||||
{0x07, DISABLED, NONE},
|
||||
{0x08, DISABLED, NONE},
|
||||
{0x09, DISABLED, NONE},
|
||||
{0x0a, DISABLED, NONE},
|
||||
{0x0b, DISABLED, NONE},
|
||||
{0x0c, DISABLED, NONE},
|
||||
{0x0d, DISABLED, NONE},
|
||||
{0x0e, DISABLED, NONE},
|
||||
{0x0f, DISABLED, NONE},
|
||||
{0x10, DISABLED, NONE},
|
||||
{0x11, DISABLED, NONE},
|
||||
{0x12, DISABLED, NONE},
|
||||
{0x13, DISABLED, NONE},
|
||||
{0x14, DISABLED, NONE},
|
||||
{0x14, DISABLED, NONE},
|
||||
{0x15, DISABLED, NONE},
|
||||
{0x16, DISABLED, NONE},
|
||||
{0x17, DISABLED, NONE},
|
||||
{0x18, DISABLED, NONE},
|
||||
{0x19, DISABLED, NONE},
|
||||
{0x20, DISABLED, NONE},
|
||||
{0x21, DISABLED, NONE},
|
||||
{0x22, DISABLED, NONE},
|
||||
{0x23, DISABLED, NONE},
|
||||
{ 0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
|
||||
{ 1, DISABLED, NONE},
|
||||
{ 2, DISABLED, NONE},
|
||||
{ 3, DISABLED, NONE},
|
||||
{ 4, DISABLED, NONE},
|
||||
{ 5, DISABLED, NONE},
|
||||
{ 6, DISABLED, NONE},
|
||||
{ 7, DISABLED, NONE},
|
||||
{ 8, DISABLED, NONE},
|
||||
{ 9, DISABLED, NONE},
|
||||
{ 10, DISABLED, NONE},
|
||||
{ 11, DISABLED, NONE},
|
||||
{ 12, DISABLED, NONE},
|
||||
{ 13, DISABLED, NONE},
|
||||
{ 14, DISABLED, NONE},
|
||||
{ 15, DISABLED, NONE},
|
||||
{ 16, DISABLED, NONE},
|
||||
{ 17, DISABLED, NONE},
|
||||
{ 18, DISABLED, NONE},
|
||||
{ 19, DISABLED, NONE},
|
||||
{ 20, DISABLED, NONE},
|
||||
{ 21, DISABLED, NONE},
|
||||
{ 22, DISABLED, NONE},
|
||||
{ 23, DISABLED, NONE},
|
||||
/* Be careful and don't write past the end... */
|
||||
};
|
||||
|
||||
static void setup_ioapic(void)
|
||||
@@ -71,6 +66,7 @@ static void setup_ioapic(void)
|
||||
struct ioapicreg *a = ioapicregvalues;
|
||||
|
||||
l = (unsigned long *) ioapic_base;
|
||||
|
||||
for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
|
||||
i++, a++) {
|
||||
l[0] = (a->reg * 2) + 0x10;
|
||||
@@ -95,13 +91,11 @@ static void lpc_init(struct device *dev)
|
||||
|
||||
printk_debug("lpc_init\n");
|
||||
|
||||
#if 0
|
||||
/* IO APIC initialization */
|
||||
byte = pci_read_config8(dev, 0x4B);
|
||||
byte |= 1;
|
||||
pci_write_config8(dev, 0x4B, byte);
|
||||
setup_ioapic();
|
||||
#endif
|
||||
|
||||
/* posted memory write enable */
|
||||
byte = pci_read_config8(dev, 0x46);
|
||||
|
||||
Reference in New Issue
Block a user