mb/asus/p8z77-series: Add P8Z77-V as a variant of P8Z77 series

Mainboard information can be found in the included documentation.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Ic56ac0e5f93a6e818ef0666e41996718471b1cf6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Bill XIE
2021-05-11 15:27:43 +08:00
committed by Patrick Georgi
parent e395cf926a
commit 8dd8f66807
17 changed files with 630 additions and 0 deletions

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# ASUS P8Z77-V
This page describes how to run coreboot on the [ASUS P8Z77-V].
## Flashing coreboot
```eval_rst
+---------------------+----------------+
| Type | Value |
+=====================+================+
| Socketed flash | yes |
+---------------------+----------------+
| Model | W25Q64FVA1Q |
+---------------------+----------------+
| Size | 8 MiB |
+---------------------+----------------+
| Package | DIP-8 |
+---------------------+----------------+
| Write protection | yes |
+---------------------+----------------+
| Dual BIOS feature | no |
+---------------------+----------------+
| Internal flashing | no |
+---------------------+----------------+
```
The flash IC is located between the black and white PCI Express x16 slots (circled):
![](p8z77-v.jpg)
### How to flash
The main SPI flash cannot be written because the vendor firmware disables BIOSWE
and enables BLE/SMM_BWP flags in BIOS_CNTL for their latest BIOSes. An external
programmer is required. You must flash standalone, flashing in-circuit doesn't
work. The flash chip is socketed, so it's easy to remove and reflash.
## Working
- PS/2 keyboard with SeaBIOS 1.14.0 and Debian GNU/Linux with kernel 5.10.28
- Integrated Ethernet NIC
- S3 Suspend to RAM
- USB2 on rear and front panel connectors
- USB3 (Z77's and ASMedia's works)
- Integrated SATA of Z77
- Integrated SATA of ASM1061 (works under GNU/Linux but not under SeaBIOS)
- CPU Temp sensors (tested PSensor on GNU/Linux)
- TPM on TPM-header (tested tpm-tools with TPM 1.2 Infineon SLB9635TT12)
- Native raminit
- Integrated graphics with libgfxinit (VGA/DVI-D/HDMI tested and working)
- PCIe in PCIe-16x/8x slots (tested using an S3 Matrix GPU)
- Debug output from serial port
- Atheros AR9485 half-height mini PCIe WNIC adapted with Wi-Fi Go! Adapter
- Default PCIe config (PCIEX_16_3 as 1x, PCIe Port 4 to ASM1061 SATA, see below
for other potential options)
## Untested
- EHCI debugging
- S/PDIF audio
- PS/2 mouse
## Not working
- PCIEX_1_2 (expected under default PCIe config)
- Other PCIe configs (see below)
## PCIe config
On Asus vendor firmware, other than the default config already supported here,
there remain another two configs: "PCIEX_16_3 as x4, with PCIEX_1_1, PCIEX_1_2
and onboard ASM1061 disabled" and "PCIEX_16_3 as x1, but PCIe Port 4 to PCIEX_1_2,
with onboard ASM1061 disabled".
Configuring PCIEX_16_3 as x4 needs to program 0x3 to the LSB of PCHSTRP9, but
also needs to configure GPIOs in the Super I/O chip different than the default
config in this board's override tree.
Configuring PCIe Port 4 to PCIEX_1_2 needs to configure GPIOs in the Super I/O
chip differently than the default config.
I have tried a lot, but sadly I am unable to produce the same result as the vendor
firmware.
## Asus Wi-Fi Go!
Asus Wi-Fi Go! has several versions. P8Z77-V has the earliest version.
See [Asus Wi-Fi Go! v1].
## Technology
```eval_rst
+------------------+--------------------------------------------------+
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+
| Southbridge | bd82x6x |
+------------------+--------------------------------------------------+
| CPU | model_206ax |
+------------------+--------------------------------------------------+
| Super I/O | Nuvoton NCT6779D |
+------------------+--------------------------------------------------+
| EC | None |
+------------------+--------------------------------------------------+
| Coprocessor | Intel Management Engine |
+------------------+--------------------------------------------------+
```
## Extra resources
- [Flash chip datasheet][W25Q64FVA1Q]
[ASUS P8Z77-V]: https://www.asus.com/supportonly/p8z77v/helpdesk_knowledge/
[W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
[flashrom]: https://flashrom.org/Flashrom
[Asus Wi-Fi Go! v1]: ./wifigo_v1.md

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# Asus Wi-Fi Go! v1
In this version, a standard half-length mPCIe card is mounted on the Asus Wi-Fi
Go! daughter board, and the daughter board is connected to the motherboard
through a proprietary 16-1 pin connector.
![](wifigo_v1_connector.jpg)
I managed to grope the most pinout of the proprietary connector.
See [Mini PCIe pinout] for more info.
```eval_rst
+------------+----------+-----------+------------+----------+-----------+
| WIFIGO Pin | Usage | mPCIe pin | WIFIGO Pin | Usage | mPCIe pin |
+============+==========+===========+============+==========+===========+
| 1 | 3.3v | (many) | 2 | REFCLK- | 11 |
+------------+----------+-----------+------------+----------+-----------+
| 3 | GND | (many) | 4 | REFCLK+ | 13 |
+------------+----------+-----------+------------+----------+-----------+
| 5 | WAKE# | 1 | 6 | PERn0 | 23 |
+------------+----------+-----------+------------+----------+-----------+
| 7 | (absent) | | 8 | PERp0 | 25 |
+------------+----------+-----------+------------+----------+-----------+
| 9 | GND | | 10 | PETn0 | 31 |
+------------+----------+-----------+------------+----------+-----------+
| 11 | PERST# | 20 | 12 | PETp0 | 33 |
+------------+----------+-----------+------------+----------+-----------+
| 13 | GND | | 14 | (USBD-?) | (36?) |
+------------+----------+-----------+------------+----------+-----------+
| 15 | 3.3v | | 16 | (USBD+?) | (38?) |
+------------+----------+-----------+------------+----------+-----------+
```
There are two kinds of daughter boards using this connector. One among them has
one MMCX antenna connector, the other has two antenna connectors and USB lane
wired (this kind may be called BT Go!). I can only obtain the former, so I
cannot confirm the exact way the USB data lane gets wired.
![](wifigo_v1_board.jpg)
## Extra resources
[Mini PCIe pinout]: https://pinoutguide.com/Slots/mini_pcie_pinout.shtml

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@@ -22,6 +22,7 @@ This section contains documentation about coreboot on specific mainboards.
- [P8H61-M LX](asus/p8h61-m_lx.md)
- [P8H61-M Pro](asus/p8h61-m_pro.md)
- [P8Z77-M Pro](asus/p8z77-m_pro.md)
- [P8Z77-V](asus/p8z77-v.md)
## Cavium