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soc/intel/apollolake: Add CQOS config for CAR common code

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Change-Id: I5947170a96e888cea2f3faac92355e72b63c1fef
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18735
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik
2017-03-10 13:51:11 +05:30
committed by Aaron Durbin
parent f0637e71c7
commit 8e1c12f12e
3 changed files with 15 additions and 8 deletions
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4
src/soc/intel/apollolake/bootblock/cache_as_ram.S
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@@ -142,7 +142,7 @@ clear_var_mtrr:
#endif
#if IS_ENABLED(CONFIG_CAR_CQOS)
#if (CONFIG_DCACHE_RAM_SIZE == L2_CACHE_SIZE)
#if (CONFIG_DCACHE_RAM_SIZE == CONFIG_L2_CACHE_SIZE)
/*
* If CAR size is set to full L2 size, mask is calculated as all-zeros.
* This is not supported by the CPU/uCode.
@@ -152,7 +152,7 @@ clear_var_mtrr:
/* Calculate how many bits to be used for CAR */
xor %edx, %edx
mov $CONFIG_DCACHE_RAM_SIZE, %eax /* dividend */
mov $CACHE_QOS_SIZE_PER_BIT, %ecx /* divisor */
mov $CONFIG_CACHE_QOS_SIZE_PER_BIT, %ecx /* divisor */
div %ecx /* result is in eax */
mov %eax, %ecx /* save to ecx */
mov $1, %ebx