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mb/pcengines/apu2/OemCustomize.c: make AGESA AmdInitPost happy

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Bank interleaving does not work on this platform, disable it.
Additionally enable ECC feature on SKUs supporting it. AmdIntPost
returns success thanks to these settings.

TEST=boot apu2 4GB ECC and apu3 2GB no ECC and see AGESA_SUCCESS after
AmdInitPost

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I010645f53b404341895d0545855905e81c89165e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Michał Żygowski 2021-04-29 17:53:10 +02:00 committed by Felix Held
parent 27be90424b
commit 8e23270405
1 changed files with 16 additions and 0 deletions
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16
src/mainboard/pcengines/apu2/OemCustomize.c
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@ -3,6 +3,8 @@
#include <AGESA.h> #include <AGESA.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
#include "gpio_ftns.h"
static const PCIe_PORT_DESCRIPTOR PortList[] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
{ {
0, 0,
@ -78,3 +80,17 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
InitEarly->PlatformConfig.CStateMode = CStateModeC6; InitEarly->PlatformConfig.CStateMode = CStateModeC6;
InitEarly->PlatformConfig.CpbMode = CpbModeAuto; InitEarly->PlatformConfig.CpbMode = CpbModeAuto;
} }
void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
{
/*
* Bank interleaving does not work on this platform.
* Disable it so AGESA will return success.
*/
Post->MemConfig.EnableBankIntlv = FALSE;
/* 4GB variants have ECC */
if (get_spd_offset())
Post->MemConfig.EnableEccFeature = TRUE;
else
Post->MemConfig.EnableEccFeature = FALSE;
}