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intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessor

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Remove cases of __PRE_RAM__ and other preprocessor guards.

Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34928
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2019-08-17 06:47:50 +03:00
parent 12b121cdb4
commit 8e23bac97e
25 changed files with 41 additions and 132 deletions
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6
src/drivers/intel/fsp1_0/fastboot_cache.c
View File

@@ -116,10 +116,6 @@ static struct mrc_data_container *find_current_mrc_cache_local
return mrc_cache;
}
/* SPI code needs malloc/free.
* Also unknown if writing flash from XIP-flash code is a good idea
*/
#if !defined(__PRE_RAM__)
/* find the first empty block in the MRC cache area.
* If there's none, return NULL.
*
@@ -221,8 +217,6 @@ void update_mrc_cache(void *unused)
current->mrc_data_size + sizeof(*current), current);
}
#endif /* !defined(__PRE_RAM__) */
void *find_and_set_fastboot_cache(void)
{
struct mrc_data_container *mrc_cache = NULL;

26
src/drivers/intel/fsp1_0/fsp_util.c
View File

@@ -25,7 +25,6 @@
#include <cpu/intel/microcode.h>
#include <cf9_reset.h>
#ifndef __PRE_RAM__
/* Globals pointers for FSP structures */
void *FspHobListPtr = NULL;
FSP_INFO_HEADER *fsp_header_ptr = NULL;
@@ -60,9 +59,6 @@ void FspNotify (u32 Phase)
if (Status != 0)
printk(BIOS_ERR,"FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n", Phase, Status);
}
#endif /* #ifndef __PRE_RAM__ */
#ifdef __PRE_RAM__
/* The FSP returns here after the fsp_early_init call */
static void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr)
@@ -115,12 +111,10 @@ void __noreturn fsp_early_init (FSP_INFO_HEADER *fsp_ptr)
/* Should never return. Control will continue from ContinuationFunc */
die("Uh Oh! FspInitApi returned");
}
#endif /* __PRE_RAM__ */
volatile u8 *find_fsp()
{
#ifdef __PRE_RAM__
#if ENV_ROMSTAGE
volatile register u8 *fsp_ptr asm ("eax");
/* Entry point for CAR assembly routine */
@@ -130,7 +124,7 @@ volatile u8 *find_fsp()
);
#else
volatile u8 *fsp_ptr;
#endif /* __PRE_RAM__ */
#endif
/* The FSP is stored in CBFS */
fsp_ptr = (u8 *) CONFIG_FSP_LOC;
@@ -225,8 +219,6 @@ void *find_fsp_reserved_mem(void *hob_list_ptr)
}
#endif /* FSP_RESERVE_MEMORY_SIZE */
#ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */
void print_fsp_info(void) {
if (fsp_header_ptr == NULL)
@@ -249,12 +241,10 @@ void print_fsp_info(void) {
(u8)(fsp_header_ptr->ImageRevision & 0xff));
}
#if CONFIG(ENABLE_MRC_CACHE)
/**
* Save the FSP memory HOB (mrc data) to the MRC area in CBMEM
*/
int save_mrc_data(void *hob_start)
static int save_mrc_data(void *hob_start)
{
u32 *mrc_hob;
u32 *mrc_hob_data;
@@ -307,7 +297,6 @@ int save_mrc_data(void *hob_start)
hexdump32(BIOS_SPEW, (void *)mrc_data->mrc_data, output_len / 4);
return (1);
}
#endif /* CONFIG_ENABLE_MRC_CACHE */
static void find_fsp_hob_update_mrc(void *unused)
{
@@ -319,13 +308,13 @@ static void find_fsp_hob_update_mrc(void *unused)
} else {
/* 0x0000: Print all types */
print_hob_type_structure(0x000, FspHobListPtr);
}
#if CONFIG(ENABLE_MRC_CACHE)
if (CONFIG(ENABLE_MRC_CACHE)) {
if (save_mrc_data(FspHobListPtr))
update_mrc_cache(NULL);
else
printk(BIOS_DEBUG,"Not updating MRC data in flash.\n");
#endif
}
}
@@ -356,11 +345,10 @@ static void fsp_finalize(void *unused)
printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseReadyToBoot)\n");
}
/* Set up for the ramstage FSP calls */
BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, fsp_after_pci_enum, NULL);
BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, fsp_finalize, NULL);
/* Update the MRC/fast boot cache as part of the late table writing stage */
BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY,
find_fsp_hob_update_mrc, NULL);
#endif /* #ifndef __PRE_RAM__ */
BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, find_fsp_hob_update_mrc, NULL);

10
src/drivers/intel/fsp1_0/fsp_util.h
View File

@@ -21,10 +21,7 @@
#include "fsp_values.h"
#if CONFIG(ENABLE_MRC_CACHE)
int save_mrc_data(void *hob_start);
void *find_and_set_fastboot_cache(void);
#endif
volatile u8 *find_fsp(void);
void fsp_early_init(FSP_INFO_HEADER *fsp_info);
@@ -65,7 +62,6 @@ void printguid(EFI_GUID *guid);
#define EFI_HOB_TYPE_HANDOFF 0x0001
#define EFI_HOB_TYPE_MEMORY_POOL 0x0007
#if CONFIG(ENABLE_MRC_CACHE)
#define MRC_DATA_ALIGN 0x1000
#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
@@ -79,11 +75,7 @@ struct mrc_data_container {
struct mrc_data_container *find_current_mrc_cache(void);
#if !defined(__PRE_RAM__)
void update_mrc_cache(void *unused);
#endif
#endif
/* The offset in bytes from the start of the info structure */
#define FSP_IMAGE_SIG_LOC 0
@@ -99,9 +91,7 @@ void update_mrc_cache(void *unused);
#define ERROR_INFO_HEAD_SIG_MISMATCH 5
#define ERROR_FSP_SIG_MISMATCH 6
#ifndef __PRE_RAM__
extern void *FspHobListPtr;
#endif
#define UPD_DEFAULT_CHECK(member) \
if (config->member != UPD_DEFAULT) { \