intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessor

Remove cases of __PRE_RAM__ and other preprocessor guards.

Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34928
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c

@@ -26,12 +26,6 @@
 #include <fspbootmode.h>
 #include "../chip.h"
 
-#ifdef __PRE_RAM__
-#include <southbridge/intel/fsp_rangeley/romstage.h>
-#endif
-
-#ifdef __PRE_RAM__
-
 /* Copy the default UPD region and settings to a buffer for modification */
 static void GetUpdDefaultFromFsp
 	(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData)
@@ -96,9 +90,9 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
 	if (config->MrcRmtCpgcNumBursts) {
 		UpdData->PcdMrcRmtCpgcNumBursts = config->MrcRmtCpgcNumBursts;
 	}
-#if CONFIG(ENABLE_FSP_FAST_BOOT)
-	UpdData->PcdFastboot = UPD_ENABLE;
-#endif
+	if (CONFIG(ENABLE_FSP_FAST_BOOT))
+		UpdData->PcdFastboot = UPD_ENABLE;
+
 	/*
 	 * Loop through all the SOC devices in the devicetree
 	 *  enabling and disabling them as requested.
@@ -164,5 +158,3 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams,
 
 	return;
 }
-
-#endif	/* __PRE_RAM__ */