sravan/system76-coreboot
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Changelog:

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* src/cpu/amd/model_lx/model_lx_init.c
  L2 cache initialization removed (moved to northbridge.c)
* src/include/cpu/amd/lxdef.h 
  more checked values
* src/northbridge/amd/lx/northbridge.c
  L2 cache initialization added
  cpubug() commented out
* src/northbridge/amd/lx/raminit.c
  empty function sdram_set_registers() is in use, don't remove
* src/mainboard/artecgroup/dbe61/Config.lb
  irqmap changes
* src/mainboard/artecgroup/dbe61/irq_tables.c
  tentative changes to irq table (currently not in use)
* src/mainboard/artecgroup/dbe61/mainboard.c
  irq assigned manually to NIC
* src/mainboard/artecgroup/dbe61/Options.lb
  gcc 4.0 is OK
* targets/artecgroup/dbe61/Config.lb
  64K for VSA is OK at moment
 
Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee>
Signed-off-by: Andrei Birjukov <andrei.birjukov@artecdesign.ee>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Indrek Kruusa
2006-08-03 16:48:18 +00:00
committed by Stefan Reinauer
parent 8ad7c06535
commit 8e3464109e
9 changed files with 128 additions and 78 deletions
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6
targets/artecgroup/dbe61/Config.lb
View File

@@ -1,11 +1,11 @@
# Config file for the olpc rev_a
# Config file for the ThinCan dbe61
target dbe61
mainboard artecgroup/dbe61
# leave 128k for vsa
# leave 64k for vsa
option CONFIG_COMPRESSED_ROM_STREAM=0
option ROM_SIZE=1024*256-128*1024
option ROM_SIZE=1024*256-64*1024
option FALLBACK_SIZE=ROM_SIZE
option DEFAULT_CONSOLE_LOGLEVEL = 11