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soc/intel/alderlake: mb/intel/sm: Add tcss code

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Enable FSP 'MultiPhaseSilicon' init to execute tcss configure during
silicon init.
Type-c aux lines DC bias changes are propagated from tigerlake
platform.

TEST=Verified superspeed pendrive detection on coldboot.

Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com>
Change-Id: Ifce6abb0fce20e408931b904426131a42a5a4a36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Deepti Deshatty
2021-05-12 17:45:37 +05:30
committed by Patrick Georgi
parent d5433afb28
commit 8e7facf343
4 changed files with 35 additions and 19 deletions
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17
src/soc/intel/alderlake/chip.h
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@@ -212,17 +212,14 @@ struct soc_intel_alderlake_config {
bool CnviBtAudioOffload;
/*
* IOM Port Config
* If a port orientation needs to be controlled by the SOC this setting must be
* updated to reflect the correct GPIOs being used for the SOC port flipping.
* There are 4 ports each with a pair of GPIOs for Pull Up and Pull Down
* 0,1 are pull up and pull down for port 0
* 2,3 are pull up and pull down for port 1
* 4,5 are pull up and pull down for port 2
* 6,7 are pull up and pull down for port 3
* values to be programmed correspond to the GPIO family and offsets
* These GPIOs will be programmed by the IOM to handle biasing of the
* Type-C aux (SBU) signals when certain alternate modes are used.
* `pad_auxn_dc` should be assigned to the GPIO pad providing negative
* bias (name usually contains `AUXN_DC` or `AUX_N`); similarly,
* `pad_auxp_dc` should be assigned to the GPIO providing positive bias
* (name often contains `AUXP_DC` or `_AUX_P`).
*/
uint32_t IomTypeCPortPadCfg[8];
struct typec_aux_bias_pads typec_aux_bias_pads[MAX_TYPE_C_PORTS];
/*
* SOC Aux orientation override: