soc/intel/alderlake: mb/intel/sm: Add tcss code
Enable FSP 'MultiPhaseSilicon' init to execute tcss configure during silicon init. Type-c aux lines DC bias changes are propagated from tigerlake platform. TEST=Verified superspeed pendrive detection on coldboot. Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Change-Id: Ifce6abb0fce20e408931b904426131a42a5a4a36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Patrick Georgi
parent
d5433afb28
commit
8e7facf343
@@ -212,17 +212,14 @@ struct soc_intel_alderlake_config {
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bool CnviBtAudioOffload;
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/*
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* IOM Port Config
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* If a port orientation needs to be controlled by the SOC this setting must be
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* updated to reflect the correct GPIOs being used for the SOC port flipping.
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* There are 4 ports each with a pair of GPIOs for Pull Up and Pull Down
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* 0,1 are pull up and pull down for port 0
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* 2,3 are pull up and pull down for port 1
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* 4,5 are pull up and pull down for port 2
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* 6,7 are pull up and pull down for port 3
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* values to be programmed correspond to the GPIO family and offsets
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* These GPIOs will be programmed by the IOM to handle biasing of the
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* Type-C aux (SBU) signals when certain alternate modes are used.
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* `pad_auxn_dc` should be assigned to the GPIO pad providing negative
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* bias (name usually contains `AUXN_DC` or `AUX_N`); similarly,
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* `pad_auxp_dc` should be assigned to the GPIO providing positive bias
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* (name often contains `AUXP_DC` or `_AUX_P`).
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*/
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uint32_t IomTypeCPortPadCfg[8];
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struct typec_aux_bias_pads typec_aux_bias_pads[MAX_TYPE_C_PORTS];
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/*
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* SOC Aux orientation override:
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