Add AMD Family 10h PH-E0 support
the patch file comes from src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE /F10MicrocodePatch010000bf.c Change-Id: If701c8a908edf1c486665d3ce4df65da0f65c802 Signed-off-by: QingPei Wang <wangqingpei@gmail.com> Reviewed-on: http://review.coreboot.org/202 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
This commit is contained in:
QingPei Wang
committed by
Peter Stuge
Peter Stuge
parent
62ff00e13f
commit
8eb4273290
164
src/cpu/amd/model_10xxx/mc_patch_010000bf.h
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164
src/cpu/amd/model_10xxx/mc_patch_010000bf.h
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@ -0,0 +1,164 @@
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/*
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============================================================
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Copyright (c) Advanced Micro Devices, Inc., 2004-2008
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The enclosed microcode is intended to be used with AMD
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Microprocessors. You may copy, view and install the
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enclosed microcode only for development and deployment of
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firmware, BIOS, or operating system code for computer
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systems that contain AMD processors. You are not
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authorized to use the enclosed microcode for any other
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purpose.
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THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR
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IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
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WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT,
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TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES
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ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
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AMD does not assume any responsibility for any errors which
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may appear in this microcode or any other related
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information provided to you by AMD, or result from use of
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this microcode. AMD is not obligated to furnish, support,
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or make any further information, software, technical
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information, know-how, or show-how available related to this
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microcode.
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The microcode is provided with "RESTRICTED RIGHTS." Use,
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duplication, or disclosure by the U.S. Government is subject
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to the restrictions as set forth in FAR 52.227-14 and
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DFAR252.227-7013, et seq., or its successor. Use of the
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microcode by the U.S. Government constitutes
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acknowledgement of AMD's proprietary rights in them.
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============================================================
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*/
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|
||||
@ -157,6 +157,7 @@ static struct cpu_device_id cpu_table[] = {
|
||||
{ X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */
|
||||
{ X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */
|
||||
{ X86_VENDOR_AMD, 0x100F81 }, /* HY-D1 */
|
||||
{ X86_VENDOR_AMD, 0x100FA0 }, /* PH-E0 */
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
|
||||
@ -51,6 +51,7 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = {
|
||||
* 00100F62h (DA-C2) 1062h 0100009Fh
|
||||
* 00100F63h (DA-C3) 1043h 010000b6h
|
||||
* 00100F81h (HY-D1) 1081h 010000c4h
|
||||
* 00100FA0h (PH-E0) 10A0h 010000bfh
|
||||
*/
|
||||
|
||||
#include CONFIG_AMD_UCODE_PATCH_FILE
|
||||
@ -78,6 +79,7 @@ static u32 get_equivalent_processor_rev_id(u32 orig_id) {
|
||||
0x100f62, 0x1062,
|
||||
0x100f63, 0x1043,
|
||||
0x100f81, 0x1081,
|
||||
0x100fa0, 0x10A0,
|
||||
};
|
||||
|
||||
u32 new_id;
|
||||
|
||||
Reference in New Issue
Block a user