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soc/intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPL

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The RPL FSP currently uses HECI commands to retrieve the chipset
initialization version because the MBP HOB creation is disabled
(SkipMbpHob=1). This has resulted in an approximate 150ms increase in
boot time. Investigations are ongoing to determine the cause of the
delay when using HECI commands. As an interim solution, this patch sets
SkipMbpHob=0, enabling the use of MBP HOB or acquiring the chipset
initialization version, which is expected to reduce the boot time.

BUG=b:328430167
TEST= Able to build,boot and collect boot time data of brya.

With this patch:
  963:returning from FspMultiPhaseSiInit     1,337,481 (249,046)

Without this patch:
  963:returning from FspMultiPhaseSiInit     1,496,268 (408,194)

Signed-off-by: Kilari Raasi <kilari.raasi@intel.com>
Change-Id: I8a99a57b644732074e41051d99e63576f1edd229
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
This commit is contained in:
Kilari Raasi 2024-03-27 15:00:31 +05:30 committed by Martin L Roth
parent 619535778c
commit 8ec17cf3e5
1 changed files with 2 additions and 3 deletions
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5
src/soc/intel/alderlake/Kconfig
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@ -517,7 +517,7 @@ config INTEL_GMA_BCLM_WIDTH
config FSP_PUBLISH_MBP_HOB config FSP_PUBLISH_MBP_HOB
bool bool
default n if CHROMEOS && (SOC_INTEL_RAPTORLAKE || SOC_INTEL_ALDERLAKE_PCH_N) default n if CHROMEOS && (SOC_INTEL_ALDERLAKE_PCH_N)
default y default y
help help
This is to control creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. This is to control creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP.
@ -526,8 +526,7 @@ config FSP_PUBLISH_MBP_HOB
Note: It cannot be disabled for ADL-P based platforms because ADL-P FSP relies on Note: It cannot be disabled for ADL-P based platforms because ADL-P FSP relies on
MBP HOB for ChipsetInit version for ChipsetInit sync. As ChipsetInit sync doesn't MBP HOB for ChipsetInit version for ChipsetInit sync. As ChipsetInit sync doesn't
occur if no MBP HOB, so it results S0ix issue. This limitation is addressed in the occur if no MBP HOB, so it results S0ix issue. This limitation is addressed in the
later platforms so creation of MBP HOB can be skipped for ADL-N and RPL based later platforms so creation of MBP HOB can be skipped for ADL-N based platforms.
platforms.
config INCLUDE_HSPHY_IN_FMAP config INCLUDE_HSPHY_IN_FMAP
bool "Include PCIe 5.0 HSPHY firmware in flash" bool "Include PCIe 5.0 HSPHY firmware in flash"